From 1fc7bb27e932a6d73038301f3be09f19dcb56fba Mon Sep 17 00:00:00 2001 From: splash5 <2173030+splash5@users.noreply.github.com> Date: Fri, 18 Oct 2019 22:29:48 +0800 Subject: [PATCH 1/4] Adjust clk count for unlocking MMC --- Cart_Reader/WS.ino | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/Cart_Reader/WS.ino b/Cart_Reader/WS.ino index 2309013..5976d0a 100644 --- a/Cart_Reader/WS.ino +++ b/Cart_Reader/WS.ino @@ -58,11 +58,11 @@ static boolean wsWitch = false; void setup_WS() { - // A0 - A7 + // A-1 - A6 DDRF = 0xff; - // A8 - A15 + // A7 - A14 DDRK = 0xff; - // A16 - A23 + // A15 - A22 DDRL = 0xff; // D0 - D15 @@ -1159,8 +1159,6 @@ void generateEepromInstruction_WS(uint8_t *instruction, uint8_t opcode, uint16_t // All signals' timing are analyzed by using LogicAnalyzer boolean unlockMMC2003_WS() { - dataOut_WS(); - // initialize all control pin state // RST(PH0) and CLK(PE3) to LOW // CART(PH3) MMC(PH4) WE(PH5) OE(PH6) to HIGH @@ -1171,24 +1169,21 @@ boolean unlockMMC2003_WS() // switch RST(PH0) to HIGH PORTH |= (1 << 0); - // data = 0x00ff - PORTC = 0xff; - PORTA = 0x00; - PORTF = 0x0a; PORTL = 0x05; - pulseCLK_WS(5); + pulseCLK_WS(3); PORTF = 0x05; PORTL = 0x0a; pulseCLK_WS(4); // MMC is outputing something on IO? pin synchronized with CLK - // so still need to pulse CLK until everything is ok - pulseCLK_WS(19); + // so still need to pulse CLK until MMC is ok to work + pulseCLK_WS(18); // unlock procedure finished // see if we can set bank number to MMC + dataOut_WS(); writeByte_WSPort(0xc2, 0xaa); writeByte_WSPort(0xc3, 0x55); From d615f433f32efc17b4f4df565b46e59abf2e244a Mon Sep 17 00:00:00 2001 From: splash5 <2173030+splash5@users.noreply.github.com> Date: Tue, 29 Oct 2019 20:30:37 +0800 Subject: [PATCH 2/4] Add WonderSwan adapter PCB and schematics --- Cart_Reader/WS.ino | 16 ---------------- pcb/README.md | 4 ++++ pcb/wonderswan_adapter.zip | Bin 0 -> 70034 bytes pcb/wonderswan_adapter_schematics.png | Bin 0 -> 91028 bytes 4 files changed, 4 insertions(+), 16 deletions(-) create mode 100755 pcb/wonderswan_adapter.zip create mode 100644 pcb/wonderswan_adapter_schematics.png diff --git a/Cart_Reader/WS.ino b/Cart_Reader/WS.ino index 5976d0a..2f35978 100644 --- a/Cart_Reader/WS.ino +++ b/Cart_Reader/WS.ino @@ -21,22 +21,6 @@ // C45 : /CART? (L when accessing cartridge (ROM/SRAM/PORT)) // C46 : INT (for RTC alarm interrupt) // C47 : CLK (384KHz on WS) -// ------------------------------------------ -// how to connect to CartReader -// ------------------------------------------ -// /RST : PH0 -// /CART? : PH3 -// /MMC : PH4 -// /WE : PH5 -// /OE : PH6 -// CLK : PE3 -// /IO? : PE4 -// INT : PG5 -// A(-1)-A6: PF0-PF7 -// A7-A14: PK0-PK7 -// A15-A18: PL0-PL3 -// D0-D7 : PC0-PC7 -// D8-D15 : PA0-PA7 /****************************************** Menu diff --git a/pcb/README.md b/pcb/README.md index cd7f0d2..a95a933 100644 --- a/pcb/README.md +++ b/pcb/README.md @@ -14,6 +14,10 @@ ![image](https://dl.dropboxusercontent.com/s/r6lavgoaccjtrz7/sms_adapter.png?dl=1) +#### wonderswan_adapter.zip is an add-on for reading WonderSwan carts. [PCB thickness needs to be changed to 1.2mm], this is very important or else it won't fit into the SNES slot. + +![image]( https://www.dropbox.com/s/755249v8smcuoft/wonderswan_adapter.png?dl=1 ) + #### flash_adapter.zip is an add-on for writing flashroms like the 29F032, 29L3211, 29LV160, [PCB thickness needs to be changed to 1.2mm](https://dl.dropboxusercontent.com/s/va1c72073cqfy90/pcb12.jpg?dl=1), this is very important or else it won't fit into the SNES slot. ![image](https://dl.dropboxusercontent.com/s/afrfmiuwvmvg9px/flash_adapter.png?dl=1) diff --git a/pcb/wonderswan_adapter.zip b/pcb/wonderswan_adapter.zip new file mode 100755 index 0000000000000000000000000000000000000000..0b6757078390841af34a4a404f1156cc123f5a06 GIT binary patch literal 70034 zcmagERZJyJur-Pe?k
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