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V21A Fixed GB Flashrom bug

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Thanks once again to skaman:
"The problem occurs because of the bank switch to 0xAA (0xAA * 0x4000 = 0x2A8000).  I'm assuming that the code you're using writes the bank to address 0x2000 (or similar) then follows with the flash sequence to program the byte.  Since 0xAA is also a flash command, the flash chip misinterprets the bank switch as the flash command and misses the command sequence to write the first byte in the bank."
This commit is contained in:
sanni 2017-01-30 22:48:08 +01:00 committed by GitHub
parent 6a9099be8c
commit 5c5b2fecce
2 changed files with 12 additions and 10 deletions
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6
Cart_Reader/Cart_Reader.ino
View File

@ -3,7 +3,7 @@
Author: sanni
Date: 2017-01-30
Version: V21
Version: V21A
SD lib: https://github.com/greiman/SdFat
LCD lib: https://github.com/adafruit/Adafruit_SSD1306
@ -16,7 +16,7 @@
MichlK - ROM-Reader for Super Nintendo
Jeff Saltzman - 4-Way Button
Wayne and Layne - Video-Game-Shield menu
skaman - SNES enhancements and SA1 sram support
skaman - SNES enhancements, SA1 sram support and GB flash fix
nocash - Nintendo Power and GBA Eeprom commands and lots of other info
crazynation - N64 bus timing
hkz/themanbehindthecurtain - N64 flashram commands
@ -34,7 +34,7 @@
YamaArashi - GBA flashrom bank switch command
**********************************************************************************/
char ver[5] = "V21";
char ver[5] = "V21A";
/******************************************
Define Output

16
Cart_Reader/GB.ino
View File

@ -825,6 +825,8 @@ void writeFlash_GB() {
// Set ROM bank
writeByte_GB(0x2000, currBank);
// 0x2A8000 fix
writeByte_GB(0x4000, 0x0);
for (unsigned int currAddr = 0x4000; currAddr < 0x7FFF; currAddr += 512) {
myFile.read(sdBuffer, 512);
@ -844,14 +846,14 @@ void writeFlash_GB() {
PORTH &= ~((1 << 3) | (1 << 6));
// Busy check
int timeout = 0;
//int timeout = 0;
while ((PINC & 0x80) != (sdBuffer[currByte] & 0x80)) {
__asm__("nop\n\t");
// Writing to 0x2A8000 fails for some unknown reason so a timeout is needed
timeout++;
if (timeout > 32760) {
break;
}
/* __asm__("nop\n\t");
// timeout in case writing fails
timeout++;
if (timeout > 32760) {
break;
}*/
}
// Switch CS(PH3) and OE/RD(PH6) to HIGH