Add files via upload

extras/snesCIC/PIC12F629.dev

@@ -0,0 +1,220 @@
+######################################################################
+#
+# MPLAB IDE .dev File Generated by `pic2dev.py'
+#
+# Device: PIC12F629
+# Family: 16xxxx
+# Datasheet: 41190
+# Programming Spec: 41191
+# Date: Mon Jul  8 10:02:41 2013
+#
+######################################################################
+
+
+######################################################################
+#
+# Memory Regions & Other General Device Information
+#
+######################################################################
+
+vpp (range=12.750-13.250 dflt=13.000)
+vdd (range=2.500-5.500 dfltrange=3.000-5.500 nominal=5.000)
+pgming (memtech=ee tries=1 lvpthresh=4.500)
+    wait (pgm=2000 eedata=6000 cfg=2500 userid=2500 erase=8000 lvpgm=2500)
+    latches (pgm=1 eedata=1 cfg=1 userid=1)
+EraseAlg=4
+HWStackDepth=8
+UndefCfgBits=0
+breakpoints (numhwbp=1 datacapture=false idbyte=x)
+calmem (region=0x3ff-0x3ff)
+userid (region=0x2000-0x2003)
+testmem (region=0x2000-0x200f)
+devid (region=0x2006-0x2006 idmask=0x3fe0 id=0xf80)
+cfgmem (region=0x2007-0x2007)
+eedata (region=0x0-0x7f)
+bkbgvectmem (region=0x2004-0x2004)
+pgmmem (region=0x0-0x3ff)
+NumBanks=2
+MirrorRegs (0xa-0xb 0x8a-0x8b)
+MirrorRegs (0x2-0x4 0x82-0x84)
+MirrorRegs (0x0-0x0 0x80-0x80)
+MirrorRegs (0x20-0x5f 0xa0-0xdf)
+UnusedRegs (0x60-0x7f)
+UnusedRegs (0xe0-0xff)
+
+######################################################################
+#
+# Special Function Registers
+#
+######################################################################
+
+sfr (key=INDF addr=0x0 size=1 flags=i access='u u u u u u u u')
+    reset (por='--------' mclr='--------')
+    bit (names='INDF' width='8')
+sfr (key=TMR0 addr=0x1 size=1 access='rw rw rw rw rw rw rw rw')
+    reset (por='xxxxxxxx' mclr='uuuuuuuu')
+    bit (names='TMR0' width='8')
+    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
+sfr (key=PCL addr=0x2 size=1 access='rw rw rw rw rw rw rw rw')
+    reset (por='00000000' mclr='00000000')
+    bit (names='PCL' width='8')
+    stimulus (scl=rwb pcfiles=rw regfiles=w)
+sfr (key=STATUS addr=0x3 size=1 access='r r rw r r rw rw rw')
+    reset (por='00011xxx' mclr='000qquuu')
+    bit (names='IRP RP nTO nPD Z DC C' width='1 2 1 1 1 1 1')
+sfr (key=FSR addr=0x4 size=1 access='rw rw rw rw rw rw rw rw')
+    reset (por='xxxxxxxx' mclr='uuuuuuuu')
+    bit (names='FSR' width='8')
+    stimulus (scl=rwb pcfiles=rw regfiles=w type=int)
+sfr (key=GPIO addr=0x5 size=1 access='u u rw rw r rw rw rw')
+    reset (por='--xxxxxx' mclr='--uuuuuu')
+    bit (names='- - GP5 GP4 GP3 GP2 GP1 GP0' width='1 1 1 1 1 1 1 1')
+    bit (tag=scl names='GP' width='8')
+    stimulus (scl=rwb pcfiles=rw regfiles=rw)
+UnusedRegs (0x6-0x9)
+sfr (key=PCLATH addr=0xa size=1 access='u u u rw rw rw rw rw')
+    reset (por='---00000' mclr='---00000')
+    bit (names='- - - PCLATH' width='1 1 1 5')
+    stimulus (scl=rwb pcfiles=rw regfiles=w type=int)
+sfr (key=INTCON addr=0xb size=1 access='rw rw rw rw rw rw rw rw')
+    reset (por='00000000' mclr='0000000u')
+    bit (names='GIE PEIE T0IE INTE GPIE T0IF INTF GPIF' width='1 1 1 1 1 1 1 1')
+    stimulus (scl=rwb pcfiles=rw regfiles=w)
+sfr (key=PIR1 addr=0xc size=1 access='rw rw u u rw u u rw')
+    reset (por='00--0--0' mclr='00--0--0')
+    bit (names='EEIF ADIF - - CMIF - - TMR1IF' width='1 1 1 1 1 1 1 1')
+    stimulus (scl=rwb pcfiles=rw regfiles=w)
+UnusedRegs (0xd-0xd)
+sfr (key=TMR1 addr=0xe size=2 flags=j)
+    bit (names='TMR1' width='16')
+    stimulus (scl=rwb regfiles=w type=int)
+sfr (key=TMR1L addr=0xe size=1 access='rw rw rw rw rw rw rw rw')
+    reset (por='xxxxxxxx' mclr='uuuuuuuu')
+    bit (names='TMR1L' width='8')
+    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
+sfr (key=TMR1H addr=0xf size=1 access='rw rw rw rw rw rw rw rw')
+    reset (por='xxxxxxxx' mclr='uuuuuuuu')
+    bit (names='TMR1H' width='8')
+    stimulus (scl=rwb pcfiles=w regfiles=w type=int)
+sfr (key=T1CON addr=0x10 size=1 access='u rw rw rw rw rw rw rw')
+    reset (por='-0000000' mclr='-uuuuuuu')
+    bit (names='- TMR1GE T1CKPS T1OSCEN nT1SYNC TMR1CS TMR1ON' width='1 1 2 1 1 1 1')
+    stimulus (scl=rwb regfiles=w)
+UnusedRegs (0x11-0x18)
+sfr (key=CMCON addr=0x19 size=1 access='u r u rw rw rw rw rw')
+    reset (por='-0-00000' mclr='-0-00000')
+    bit (names='- COUT - CINV CIS CM' width='1 1 1 1 1 3')
+    stimulus (scl=rwb regfiles=w)
+UnusedRegs (0x1a-0x1f)
+sfr (key=OPTION_REG addr=0x81 size=1 access='rw rw rw rw rw rw rw rw')
+    reset (por='11111111' mclr='11111111')
+    bit (names='nGPPU INTEDG T0CS T0SE PSA PS' width='1 1 1 1 1 3')
+    stimulus (scl=rwb regfiles=w)
+sfr (key=TRISIO addr=0x85 size=1 access='u u rw rw r rw rw rw')
+    reset (por='--111111' mclr='--111111')
+    bit (names='- - TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0' width='1 1 1 1 1 1 1 1')
+    bit (tag=scl names='TRISIO' width='8')
+    stimulus (scl=rwb regfiles=w)
+UnusedRegs (0x86-0x89)
+sfr (key=PIE1 addr=0x8c size=1 access='rw rw u u rw u u rw')
+    reset (por='00--0--0' mclr='00--0--0')
+    bit (names='EEIE ADIE - - CMIE - - TMR1IE' width='1 1 1 1 1 1 1 1')
+    stimulus (scl=rwb pcfiles=rw regfiles=w)
+UnusedRegs (0x8d-0x8d)
+sfr (key=PCON addr=0x8e size=1 access='u u u u u u rw rw')
+    reset (por='------0x' mclr='------uu')
+    bit (names='- - - - - - nPOR nBOR' width='1 1 1 1 1 1 1 1')
+    stimulus (scl=rwb regfiles=w)
+UnusedRegs (0x8f-0x8f)
+sfr (key=OSCCAL addr=0x90 size=1 access='rw rw rw rw rw rw u u')
+    reset (por='100000--' mclr='100000--')
+    bit (names='CAL - -' width='6 1 1')
+    stimulus (scl=rwb regfiles=w)
+UnusedRegs (0x91-0x94)
+sfr (key=WPU addr=0x95 size=1 access='u u rw rw u rw rw rw')
+    reset (por='--11-111' mclr='--11-111')
+    bit (names='- - WPU5 WPU4 - WPU2 WPU1 WPU0' width='1 1 1 1 1 1 1 1')
+    stimulus (scl=rwb regfiles=w)
+sfr (key=IOC addr=0x96 size=1 access='u u rw rw rw rw rw rw')
+    reset (por='--000000' mclr='--000000')
+    bit (names='- - IOC5 IOC4 IOC3 IOC2 IOC1 IOC0' width='1 1 1 1 1 1 1 1')
+    stimulus (scl=rwb regfiles=w)
+UnusedRegs (0x97-0x98)
+sfr (key=VRCON addr=0x99 size=1 access='rw u rw u rw rw rw rw')
+    reset (por='0-0-0000' mclr='0-0-0000')
+    bit (names='VREN - VRR - VR' width='1 1 1 1 4')
+    stimulus (scl=rwb regfiles=w)
+sfr (key=EEDATA addr=0x9a size=1 access='rw rw rw rw rw rw rw rw')
+    reset (por='00000000' mclr='00000000')
+    bit (names='EEDATA' width='8')
+    stimulus (scl=rwb pcfiles=rw regfiles=rw)
+sfr (key=EEADR addr=0x9b size=1 access='u rw rw rw rw rw rw rw')
+    reset (por='-0000000' mclr='-0000000')
+    bit (names='- EEADR' width='1 7')
+    stimulus (scl=rwb pcfiles=rw regfiles=w)
+sfr (key=EECON1 addr=0x9c size=1 access='u u u u rw rw rs rs')
+    reset (por='----x000' mclr='----q000')
+    bit (names='- - - - WRERR WREN WR RD' width='1 1 1 1 1 1 1 1')
+    stimulus (scl=rwb pcfiles=rw regfiles=w)
+sfr (key=EECON2 addr=0x9d size=1 access='w w w w w w w w')
+    reset (por='--------' mclr='--------')
+    bit (names='EECON2' width='8')
+UnusedRegs (0x9e-0x9f)
+
+######################################################################
+#
+# Non Memory-Mapped Registers
+#
+# (Conditionally visible SFRs appear as NMMRs in the "Special Function
+# Registers" section.)
+#
+######################################################################
+
+HasNMMR=1
+nmmr (key=WREG addr=0x0 size=1 access='rw rw rw rw rw rw rw rw')
+    reset (por='00000000' mclr='00000000')
+nmmr (key=STKPTR addr=0x1 size=1 flags=h access='rw rw rw rw rw rw rw')
+    reset (por='00000000' mclr='00000000')
+NMMRObjSize=2
+
+######################################################################
+#
+# Configuration Registers
+#
+######################################################################
+
+cfgbits (key=CONFIG addr=0x2007 unused=0x3e00)
+    field (key=FOSC mask=0x7 desc="Oscillator Selection bits")
+        setting (req=0x7 value=0x7 desc="RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN")
+        setting (req=0x7 value=0x6 desc="RC oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN")
+        setting (req=0x7 value=0x5 desc="INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN")
+        setting (req=0x7 value=0x4 desc="INTOSC oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN")
+        setting (req=0x7 value=0x3 desc="EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN")
+        setting (req=0x7 value=0x2 desc="HS oscillator: High speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN")
+        setting (req=0x7 value=0x1 desc="XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN")
+        setting (req=0x7 value=0x0 desc="LP oscillator: Low power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN")
+    field (key=WDTE mask=0x8 desc="Watchdog Timer Enable bit")
+        setting (req=0x8 value=0x8 desc="Enabled")
+        setting (req=0x8 value=0x0 desc="Disabled")
+    field (key=PWRTE mask=0x10 desc="Power-Up Timer Enable bit")
+        setting (req=0x10 value=0x10 desc="Disabled")
+        setting (req=0x10 value=0x0 desc="Enabled")
+    field (key=MCLRE mask=0x20 desc="GP3/MCLR pin function select")
+        setting (req=0x20 value=0x20 desc="Enabled")
+        setting (req=0x20 value=0x0 desc="Disabled")
+    field (key=BOREN mask=0x40 desc="Brown-out Detect Enable bit")
+        setting (req=0x40 value=0x40 desc="Enabled")
+        setting (req=0x40 value=0x0 desc="Disabled")
+    field (key=CP mask=0x80 desc="Code Protection bit")
+        setting (req=0x80 value=0x80 desc="Disabled")
+            checksum (type=0x0 protregion=0x0-0x0)
+        setting (req=0x80 value=0x0 desc="Enabled")
+            checksum (type=0x20 protregion=0x0-0x3fe)
+    field (key=CPD mask=0x100 desc="Data Code Protection bit")
+        setting (req=0x100 value=0x100 desc="Disabled")
+        setting (req=0x100 value=0x0 desc="Enabled")
+    field (key=Reserved mask=0xe00 desc="Reserved" init=0x0 flags=xh)
+        setting (req=0xe00 value=0x0 desc="Reserved")
+    field (key=BG mask=0x3000 desc="Bandgap Calibration bits for BOD and POR voltage" flags=xh)
+        setting (req=0x3000 value=0x3000 desc="Highest bandgap voltage")
+        setting (req=0x3000 value=0x0 desc="Lowest bandgap voltage")