mirror of
https://github.com/sanni/cartreader.git
synced 2024-11-14 08:55:06 +01:00
SRAM Fixes
This commit is contained in:
sakman55
GitHub
parent
932ca584b4
commit
840f50d063
@ -954,19 +954,74 @@ void writeSRAM (boolean browseFile) {
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if (romType == LO) {
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// Sram size
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long lastByte = (long(sramSize) * 128);
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for (long currByte = 0; currByte < lastByte; currByte++) {
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writeBank_SNES(0x70, currByte, myFile.read());
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if ((romChips == 19) || (romChips == 20) || (romChips == 21) || (romChips == 26)) { // SuperFX
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if (lastByte > 0x10000) { // Large SuperFX SRAM (no known carts)
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sramBanks = lastByte / 0x10000;
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for (int currBank = 0x70; currBank < sramBanks + 0x70; currBank++) {
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for (long currByte = 0x0000; currByte < 0x10000; currByte++) {
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writeBank_SNES(currBank, currByte, myFile.read());
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}
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}
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}
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else { // SuperFX SRAM
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for (long currByte = 0; currByte < lastByte; currByte++) {
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writeBank_SNES(0x70, currByte, myFile.read());
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}
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}
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}
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else if (lastByte > 0x8000) { // Large SRAM Fix
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sramBanks = lastByte / 0x8000;
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for (int currBank = 0x70; currBank < sramBanks + 0x70; currBank++) {
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for (long currByte = 0x0000; currByte < 0x8000; currByte++) {
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writeBank_SNES(currBank, currByte, myFile.read());
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}
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}
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}
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else {
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for (long currByte = 0; currByte < lastByte; currByte++) {
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writeBank_SNES(0x70, currByte, myFile.read());
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}
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}
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}
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// HiRom
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else if (romType == HI) {
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// Writing SRAM on HiRom needs CS(PH3) to be high
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PORTH |= (1 << 3);
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// Sram size
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long lastByte = (long(sramSize) * 128) + 0x6000;
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for (long currByte = 0x6000; currByte < lastByte; currByte++) {
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writeBank_SNES(0x30, currByte, myFile.read());
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if ((romChips == 245) || (romChips == 249)) { // SPC7110 SRAM
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// Configure SPC7110 SRAM Register
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// Set 0x4830 to 0x80
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writeBank_SNES(0, 0x4830, 0x80);
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// Sram size
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long lastByte = (long(sramSize) * 128) + 0x6000;
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// Write to sram bank
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for (long currByte = 0x6000; currByte < lastByte; currByte++) {
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writeBank_SNES(0x30, currByte, myFile.read());
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}
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// Reset SPC7110 SRAM Register
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dataOut();
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// Reset 0x4830 to 0x0
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writeBank_SNES(0, 0x4830, 0);
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dataIn();
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}
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else {
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// Writing SRAM on HiRom needs CS(PH3) to be high
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PORTH |= (1 << 3);
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// Sram size
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long lastByte = (long(sramSize) * 128);
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if (lastByte > 0x2000) { // Large SRAM Fix
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sramBanks = lastByte / 0x2000;
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for (int currBank = 0x30; currBank < sramBanks + 0x30; currBank++) {
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for (long currByte = 0x6000; currByte < 0x8000; currByte++) {
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writeBank_SNES(currBank, currByte, myFile.read());
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}
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}
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}
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else {
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lastByte += 0x6000;
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// Write to sram bank
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for (long currByte = 0x6000; currByte < lastByte; currByte++) {
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writeBank_SNES(0x30, currByte, myFile.read());
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}
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}
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}
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}
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// ExHiRom
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@ -981,8 +1036,7 @@ void writeSRAM (boolean browseFile) {
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}
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// SA1
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else if (romType == SA) {
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long lastByte = (long(sramSize) * 0x80);
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long lastByte = (long(sramSize) * 128);
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// Enable CPU Clock
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clockgen.set_freq(357954500ULL, SI5351_CLK1);
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clockgen.output_enable(SI5351_CLK1, 1);
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@ -1022,6 +1076,7 @@ void writeSRAM (boolean browseFile) {
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// Disable CPU clock
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clockgen.output_enable(SI5351_CLK1, 0);
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/* // MOVED RESET TO AFTER VERIFY
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// Reset SA1
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// Set pins to input
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dataIn();
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@ -1040,6 +1095,7 @@ void writeSRAM (boolean browseFile) {
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display_Update();
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delay(3000); // wait 3 secs to switch to next game
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asm volatile (" jmp 0");
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*/
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}
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// Set pins to input
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@ -1078,20 +1134,75 @@ void readSRAM () {
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if (!myFile.open(fileName, O_RDWR | O_CREAT)) {
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print_Error(F("SD Error"), true);
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}
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int sramBanks = 0;
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if (romType == LO) {
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// Sram size
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long lastByte = (long(sramSize) * 128);
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for (long currByte = 0; currByte < lastByte; currByte++) {
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myFile.write(readBank_SNES(0x70, currByte));
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if ((romChips == 19) || (romChips == 20) || (romChips == 21) || (romChips == 26)) { // SuperFX
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if (lastByte > 0x10000) { // Large SuperFX SRAM (no known carts)
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sramBanks = lastByte / 0x10000;
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for (int currBank = 0x70; currBank < sramBanks + 0x70; currBank++) {
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for (long currByte = 0x0000; currByte < 0x10000; currByte++) {
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myFile.write(readBank_SNES(currBank, currByte));
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}
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}
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}
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else { // SuperFX SRAM
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for (long currByte = 0; currByte < lastByte; currByte++) {
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myFile.write(readBank_SNES(0x70, currByte));
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}
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}
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}
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else if (lastByte > 0x8000) { // Large SRAM Fix
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sramBanks = lastByte / 0x8000;
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for (int currBank = 0x70; currBank < sramBanks + 0x70; currBank++) {
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for (long currByte = 0x0000; currByte < 0x8000; currByte++) {
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myFile.write(readBank_SNES(currBank, currByte));
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}
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}
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}
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else {
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for (long currByte = 0; currByte < lastByte; currByte++) {
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myFile.write(readBank_SNES(0x70, currByte));
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}
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}
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}
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else if (romType == HI) {
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// Dumping SRAM on HiRom needs CS(PH3) to be high
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PORTH |= (1 << 3);
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// Sram size
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long lastByte = (long(sramSize) * 128) + 0x6000;
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for (long currByte = 0x6000; currByte < lastByte; currByte++) {
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myFile.write(readBank_SNES(0x30, currByte));
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if ((romChips == 245) || (romChips == 249)) { // SPC7110 SRAM
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// Configure SPC7110 SRAM Register
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dataOut();
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// Set 0x4830 to 0x80
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writeBank_SNES(0, 0x4830, 0x80);
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dataIn();
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// Sram size
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long lastByte = (long(sramSize) * 128) + 0x6000;
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for (long currByte = 0x6000; currByte < lastByte; currByte++) {
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myFile.write(readBank_SNES(0x30, currByte));
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}
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dataOut();
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// Reset 0x4830 to 0x0
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writeBank_SNES(0, 0x4830, 0);
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dataIn();
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}
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else {
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// Dumping SRAM on HiRom needs CS(PH3) to be high
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PORTH |= (1 << 3);
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// Sram size
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long lastByte = (long(sramSize) * 128);
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if (lastByte > 0x2000) { // Large SRAM Fix
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sramBanks = lastByte / 0x2000;
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for (int currBank = 0x30; currBank < sramBanks + 0x30; currBank++) {
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for (long currByte = 0x6000; currByte < 0x8000; currByte++) {
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myFile.write(readBank_SNES(currBank, currByte));
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}
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}
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}
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else {
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lastByte += 0x6000;
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for (long currByte = 0x6000; currByte < lastByte; currByte++) {
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myFile.write(readBank_SNES(0x30, currByte));
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}
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}
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}
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}
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else if (romType == EX) {
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@ -1108,8 +1219,18 @@ void readSRAM () {
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PORTH |= (1 << 3);
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// Sram size
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long lastByte = (long(sramSize) * 128);
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for (long currByte = 0x0; currByte < lastByte; currByte++) {
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myFile.write(readBank_SNES(0x40, currByte));
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if (lastByte > 0x10000) {
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sramBanks = lastByte / 0x10000;
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for (int currBank = 0x40; currBank < sramBanks + 0x40; currBank++) {
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for (long currByte = 0; currByte < 0x10000; currByte++) {
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myFile.write(readBank_SNES(currBank, currByte));
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}
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}
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}
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else {
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for (long currByte = 0x0; currByte < lastByte; currByte++) {
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myFile.write(readBank_SNES(0x40, currByte));
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}
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}
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}
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@ -1135,30 +1256,115 @@ unsigned long verifySRAM() {
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// Set control
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controlIn_SNES();
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int sramBanks = 0;
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if (romType == LO) {
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// Sram size
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long lastByte = (long(sramSize) * 128);
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for (long currByte = 0; currByte < lastByte; currByte += 512) {
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//fill sdBuffer
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myFile.read(sdBuffer, 512);
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for (int c = 0; c < 512; c++) {
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if ((readBank_SNES(0x70, currByte + c)) != sdBuffer[c]) {
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writeErrors++;
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if ((romChips == 19) || (romChips == 20) || (romChips == 21) || (romChips == 26)) { // SuperFX
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if (lastByte > 0x10000) { // Large SuperFX SRAM (no known carts)
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sramBanks = lastByte / 0x10000;
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for (int currBank = 0x70; currBank < sramBanks + 0x70; currBank++) {
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for (long currByte = 0; currByte < 0x10000; currByte += 512) {
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//fill sdBuffer
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myFile.read(sdBuffer, 512);
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for (int c = 0; c < 512; c++) {
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if ((readBank_SNES(currBank, currByte + c)) != sdBuffer[c]) {
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writeErrors++;
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}
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}
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}
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}
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}
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else { // SuperFX SRAM
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for (long currByte = 0; currByte < lastByte; currByte += 512) {
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//fill sdBuffer
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myFile.read(sdBuffer, 512);
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for (int c = 0; c < 512; c++) {
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if ((readBank_SNES(0x70, currByte + c)) != sdBuffer[c]) {
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writeErrors++;
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}
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}
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}
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}
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}
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else if (lastByte > 0x8000) { // Large SRAM Fix
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sramBanks = lastByte / 0x8000;
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for (int currBank = 0x70; currBank < sramBanks + 0x70; currBank++) {
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for (long currByte = 0; currByte < 0x8000; currByte += 512) {
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//fill sdBuffer
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myFile.read(sdBuffer, 512);
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for (int c = 0; c < 512; c++) {
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if ((readBank_SNES(currBank, currByte + c)) != sdBuffer[c]) {
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writeErrors++;
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}
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}
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}
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}
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}
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else {
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for (long currByte = 0; currByte < lastByte; currByte += 512) {
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//fill sdBuffer
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myFile.read(sdBuffer, 512);
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for (int c = 0; c < 512; c++) {
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if ((readBank_SNES(0x70, currByte + c)) != sdBuffer[c]) {
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writeErrors++;
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}
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}
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}
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}
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}
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else if (romType == HI) {
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// Dumping SRAM on HiRom needs CS(PH3) to be high
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PORTH |= (1 << 3);
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// Sram size
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long lastByte = (long(sramSize) * 128) + 0x6000;
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for (long currByte = 0x6000; currByte < lastByte; currByte += 512) {
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//fill sdBuffer
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myFile.read(sdBuffer, 512);
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for (int c = 0; c < 512; c++) {
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if ((readBank_SNES(0x30, currByte + c)) != sdBuffer[c]) {
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writeErrors++;
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if ((romChips == 245) || (romChips == 249)) { // SPC7110 SRAM
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// Configure SPC7110 SRAM Register
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dataOut();
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// Set 0x4830 to 0x80
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writeBank_SNES(0, 0x4830, 0x80);
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dataIn();
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// Sram size
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long lastByte = (long(sramSize) * 128) + 0x6000;
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for (long currByte = 0x6000; currByte < lastByte; currByte += 512) {
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//fill sdBuffer
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myFile.read(sdBuffer, 512);
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for (int c = 0; c < 512; c++) {
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if ((readBank_SNES(0x30, currByte + c)) != sdBuffer[c]) {
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writeErrors++;
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}
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}
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}
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dataOut();
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// Reset 0x4830 to 0x0
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writeBank_SNES(0, 0x4830, 0);
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dataIn();
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}
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else {
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// Dumping SRAM on HiRom needs CS(PH3) to be high
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PORTH |= (1 << 3);
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// Sram size
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long lastByte = (long(sramSize) * 128);
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if (lastByte > 0x2000) { // Large SRAM Fix
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sramBanks = lastByte / 0x2000;
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for (int currBank = 0x30; currBank < sramBanks + 0x30; currBank++) {
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for (long currByte = 0x6000; currByte < 0x8000; currByte += 512) {
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//fill sdBuffer
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myFile.read(sdBuffer, 512);
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for (int c = 0; c < 512; c++) {
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if ((readBank_SNES(currBank, currByte + c)) != sdBuffer[c]) {
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writeErrors++;
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}
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}
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}
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}
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}
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else {
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lastByte += 0x6000;
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for (long currByte = 0x6000; currByte < lastByte; currByte += 512) {
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//fill sdBuffer
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myFile.read(sdBuffer, 512);
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for (int c = 0; c < 512; c++) {
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if ((readBank_SNES(0x30, currByte + c)) != sdBuffer[c]) {
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writeErrors++;
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}
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}
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}
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}
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}
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@ -1183,15 +1389,57 @@ unsigned long verifySRAM() {
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PORTH |= (1 << 3);
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// Sram size
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long lastByte = (long(sramSize) * 128);
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for (long currByte = 0x0; currByte < lastByte; currByte += 512) {
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//fill sdBuffer
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myFile.read(sdBuffer, 512);
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for (int c = 0; c < 512; c++) {
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if ((readBank_SNES(0x40, currByte + c)) != sdBuffer[c]) {
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writeErrors++;
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if (lastByte > 0x10000) {
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sramBanks = lastByte / 0x10000;
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for (int currBank = 0x40; currBank < sramBanks + 0x40; currBank++) {
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for (long currByte = 0x0; currByte < 0x10000; currByte += 512) {
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//fill sdBuffer
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myFile.read(sdBuffer, 512);
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for (int c = 0; c < 512; c++) {
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if ((readBank_SNES(currBank, currByte + c)) != sdBuffer[c]) {
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writeErrors++;
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}
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}
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}
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}
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}
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else {
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for (long currByte = 0x0; currByte < lastByte; currByte += 512) {
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//fill sdBuffer
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myFile.read(sdBuffer, 512);
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for (int c = 0; c < 512; c++) {
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if ((readBank_SNES(0x40, currByte + c)) != sdBuffer[c]) {
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writeErrors++;
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}
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}
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}
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}
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// Reset SA1
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// Set pins to input
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dataIn();
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// Close the file:
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myFile.close();
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if (writeErrors == 0) {
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println_Msg(F("Verified OK"));
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}
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else {
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print_Msg(F("Error: "));
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print_Msg(writeErrors);
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println_Msg(F(" bytes "));
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print_Error(F("did not verify."), false);
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}
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display_Update();
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wait();
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// Set reset pin to output (PH0)
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DDRH |= (1 << 0);
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// Switch RST(PH0) to LOW
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PORTH &= ~(1 << 0);
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display_Clear();
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print_Msg("Resetting...");
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display_Update();
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delay(3000); // wait 3 secs
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asm volatile (" jmp 0");
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}
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// Close the file:
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myFile.close();
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@ -1215,22 +1463,77 @@ boolean eraseSRAM (byte b) {
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// Set control pins
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controlOut_SNES();
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int sramBanks = 0;
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if (romType == LO) {
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// Sram size
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long lastByte = (long(sramSize) * 128);
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for (long currByte = 0; currByte < lastByte; currByte++) {
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writeBank_SNES(0x70, currByte, b);
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if ((romChips == 19) || (romChips == 20) || (romChips == 21) || (romChips == 26)) { // SuperFX
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if (lastByte > 0x10000) { // Large SuperFX SRAM (no known carts)
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sramBanks = lastByte / 0x10000;
|
||||
for (int currBank = 0x70; currBank < sramBanks + 0x70; currBank++) {
|
||||
for (long currByte = 0x0000; currByte < 0x10000; currByte++) {
|
||||
writeBank_SNES(currBank, currByte, b);
|
||||
}
|
||||
}
|
||||
}
|
||||
else { // SuperFX SRAM
|
||||
for (long currByte = 0; currByte < lastByte; currByte++) {
|
||||
writeBank_SNES(0x70, currByte, b);
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (lastByte > 0x8000) { // Large SRAM Fix
|
||||
sramBanks = lastByte / 0x8000;
|
||||
for (int currBank = 0x70; currBank < sramBanks + 0x70; currBank++) {
|
||||
for (long currByte = 0x0000; currByte < 0x8000; currByte++) {
|
||||
writeBank_SNES(currBank, currByte, b);
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
for (long currByte = 0; currByte < lastByte; currByte++) {
|
||||
writeBank_SNES(0x70, currByte, b);
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (romType == HI) {
|
||||
// Writing SRAM on HiRom needs CS(PH3) to be high
|
||||
PORTH |= (1 << 3);
|
||||
// Sram size
|
||||
long lastByte = (long(sramSize) * 128) + 0x6000;
|
||||
for (long currByte = 0x6000; currByte < lastByte; currByte++) {
|
||||
writeBank_SNES(0x30, currByte, b);
|
||||
|
||||
if ((romChips == 245) || (romChips == 249)) { // SPC7110 SRAM
|
||||
// Configure SPC7110 SRAM Register
|
||||
// Set 0x4830 to 0x80
|
||||
writeBank_SNES(0, 0x4830, 0x80);
|
||||
// Sram size
|
||||
long lastByte = (long(sramSize) * 128) + 0x6000;
|
||||
// Write to sram bank
|
||||
for (long currByte = 0x6000; currByte < lastByte; currByte++) {
|
||||
writeBank_SNES(0x30, currByte, b);
|
||||
}
|
||||
// Reset SPC7110 SRAM Register
|
||||
dataOut();
|
||||
// Reset 0x4830 to 0x0
|
||||
writeBank_SNES(0, 0x4830, 0);
|
||||
dataIn();
|
||||
}
|
||||
else {
|
||||
// Writing SRAM on HiRom needs CS(PH3) to be high
|
||||
PORTH |= (1 << 3);
|
||||
// Sram size
|
||||
long lastByte = (long(sramSize) * 128);
|
||||
if (lastByte > 0x2000) { // Large SRAM Fix
|
||||
sramBanks = lastByte / 0x2000;
|
||||
for (int currBank = 0x30; currBank < sramBanks + 0x30; currBank++) {
|
||||
for (long currByte = 0x6000; currByte < 0x8000; currByte++) {
|
||||
writeBank_SNES(currBank, currByte, b);
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
lastByte += 0x6000;
|
||||
// Write to sram bank
|
||||
for (long currByte = 0x6000; currByte < lastByte; currByte++) {
|
||||
writeBank_SNES(0x30, currByte, b);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
// ExHiRom
|
||||
@ -1243,6 +1546,49 @@ boolean eraseSRAM (byte b) {
|
||||
writeBank_SNES(0xB0, currByte, b);
|
||||
}
|
||||
}
|
||||
// SA1
|
||||
else if (romType == SA) {
|
||||
long lastByte = (long(sramSize) * 128);
|
||||
// Enable CPU Clock
|
||||
clockgen.set_freq(357954500ULL, SI5351_CLK1);
|
||||
clockgen.output_enable(SI5351_CLK1, 1);
|
||||
|
||||
// Direct writes to BW-RAM (SRAM) in banks 0x40-0x43 don't work
|
||||
// Break BW-RAM (SRAM) into 0x2000 blocks
|
||||
// Use $2225 to map BW-RAM block to 0x6000-0x7FFF
|
||||
// Writes must be to entire address range 0x0000-0x7FFF
|
||||
byte lastBlock = 0;
|
||||
lastBlock = lastByte / 0x2000;
|
||||
|
||||
// Writing SRAM on SA1 needs CS(PH3) to be high
|
||||
PORTH |= (1 << 3);
|
||||
|
||||
for (byte currBlock = 0; currBlock < lastBlock; currBlock++) {
|
||||
// Set 0x2225 (SA-1 BMAP) to map SRAM Block to 0x6000-0x7FFF
|
||||
writeBank_SNES(0, 0x2225, currBlock);
|
||||
// Set 0x2227 to 0x80 SA-1 SWBE BW-RAM Write Enable
|
||||
writeBank_SNES(0, 0x2227, 0x80);
|
||||
for (long currByte = 0x0000; currByte < 0x8000; currByte += 512) {
|
||||
if (currByte < 0x6000) {
|
||||
for (int c = 0; c < 512; c++) {
|
||||
// Shift to bypass protected 1st 0x100 bytes
|
||||
writeBank_SNES(0, currByte + c, currBlock + lastBlock);
|
||||
}
|
||||
}
|
||||
else {
|
||||
myFile.read(sdBuffer, 512);
|
||||
for (int c = 0; c < 512; c++) {
|
||||
writeBank_SNES(0, currByte + c, b);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
// Set 0x2227 to 0x00 SA-1 SWBE BW-RAM Write Disable
|
||||
writeBank_SNES(0, 0x2227, 0x00);
|
||||
// Disable CPU clock
|
||||
clockgen.output_enable(SI5351_CLK1, 0);
|
||||
}
|
||||
|
||||
dataIn();
|
||||
|
||||
// Variable for errors
|
||||
@ -1251,26 +1597,101 @@ boolean eraseSRAM (byte b) {
|
||||
// Set control
|
||||
controlIn_SNES();
|
||||
|
||||
sramBanks = 0;
|
||||
if (romType == LO) {
|
||||
// Sram size
|
||||
long lastByte = (long(sramSize) * 128);
|
||||
for (long currByte = 0; currByte < lastByte; currByte += 512) {
|
||||
for (int c = 0; c < 512; c++) {
|
||||
if ((readBank_SNES(0x70, currByte + c)) != b) {
|
||||
writeErrors++;
|
||||
if ((romChips == 19) || (romChips == 20) || (romChips == 21) || (romChips == 26)) { // SuperFX
|
||||
if (lastByte > 0x10000) { // Large SuperFX SRAM (no known carts)
|
||||
sramBanks = lastByte / 0x10000;
|
||||
for (int currBank = 0x70; currBank < sramBanks + 0x70; currBank++) {
|
||||
for (long currByte = 0; currByte < 0x10000; currByte += 512) {
|
||||
for (int c = 0; c < 512; c++) {
|
||||
if ((readBank_SNES(currBank, currByte + c)) != b) {
|
||||
writeErrors++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else { // SuperFX SRAM
|
||||
for (long currByte = 0; currByte < lastByte; currByte += 512) {
|
||||
for (int c = 0; c < 512; c++) {
|
||||
if ((readBank_SNES(0x70, currByte + c)) != b) {
|
||||
writeErrors++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (lastByte > 0x8000) { // Large SRAM Fix
|
||||
sramBanks = lastByte / 0x8000;
|
||||
for (int currBank = 0x70; currBank < sramBanks + 0x70; currBank++) {
|
||||
for (long currByte = 0; currByte < 0x8000; currByte += 512) {
|
||||
for (int c = 0; c < 512; c++) {
|
||||
if ((readBank_SNES(currBank, currByte + c)) != b) {
|
||||
writeErrors++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
for (long currByte = 0; currByte < lastByte; currByte += 512) {
|
||||
for (int c = 0; c < 512; c++) {
|
||||
if ((readBank_SNES(0x70, currByte + c)) != b) {
|
||||
writeErrors++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (romType == HI) {
|
||||
// Dumping SRAM on HiRom needs CS(PH3) to be high
|
||||
PORTH |= (1 << 3);
|
||||
// Sram size
|
||||
long lastByte = (long(sramSize) * 128) + 0x6000;
|
||||
for (long currByte = 0x6000; currByte < lastByte; currByte += 512) {
|
||||
for (int c = 0; c < 512; c++) {
|
||||
if ((readBank_SNES(0x30, currByte + c)) != b) {
|
||||
writeErrors++;
|
||||
if ((romChips == 245) || (romChips == 249)) { // SPC7110 SRAM
|
||||
// Configure SPC7110 SRAM Register
|
||||
dataOut();
|
||||
// Set 0x4830 to 0x80
|
||||
writeBank_SNES(0, 0x4830, 0x80);
|
||||
dataIn();
|
||||
// Sram size
|
||||
long lastByte = (long(sramSize) * 128) + 0x6000;
|
||||
for (long currByte = 0x6000; currByte < lastByte; currByte += 512) {
|
||||
for (int c = 0; c < 512; c++) {
|
||||
if ((readBank_SNES(0x30, currByte + c)) != b) {
|
||||
writeErrors++;
|
||||
}
|
||||
}
|
||||
}
|
||||
dataOut();
|
||||
// Reset 0x4830 to 0x0
|
||||
writeBank_SNES(0, 0x4830, 0);
|
||||
dataIn();
|
||||
}
|
||||
else {
|
||||
// Dumping SRAM on HiRom needs CS(PH3) to be high
|
||||
PORTH |= (1 << 3);
|
||||
// Sram size
|
||||
long lastByte = (long(sramSize) * 128);
|
||||
if (lastByte > 0x2000) { // Large SRAM Fix
|
||||
sramBanks = lastByte / 0x2000;
|
||||
for (int currBank = 0x30; currBank < sramBanks + 0x30; currBank++) {
|
||||
for (long currByte = 0x6000; currByte < 0x8000; currByte += 512) {
|
||||
for (int c = 0; c < 512; c++) {
|
||||
if ((readBank_SNES(currBank, currByte + c)) != b) {
|
||||
writeErrors++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
lastByte += 0x6000;
|
||||
for (long currByte = 0x6000; currByte < lastByte; currByte += 512) {
|
||||
for (int c = 0; c < 512; c++) {
|
||||
if ((readBank_SNES(0x30, currByte + c)) != b) {
|
||||
writeErrors++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1288,6 +1709,33 @@ boolean eraseSRAM (byte b) {
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (romType == SA) {
|
||||
// Dumping SRAM on HiRom needs CS(PH3) to be high
|
||||
PORTH |= (1 << 3);
|
||||
// Sram size
|
||||
long lastByte = (long(sramSize) * 128);
|
||||
if (lastByte > 0x10000) {
|
||||
sramBanks = lastByte / 0x10000;
|
||||
for (int currBank = 0x40; currBank < sramBanks + 0x40; currBank++) {
|
||||
for (long currByte = 0x0; currByte < 0x10000; currByte += 512) {
|
||||
for (int c = 0; c < 512; c++) {
|
||||
if ((readBank_SNES(currBank, currByte + c)) != b) {
|
||||
writeErrors++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
for (long currByte = 0x0; currByte < lastByte; currByte += 512) {
|
||||
for (int c = 0; c < 512; c++) {
|
||||
if ((readBank_SNES(0x40, currByte + c)) != b) {
|
||||
writeErrors++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if (writeErrors == 0) {
|
||||
println_Msg(F("OK"));
|
||||
return 1;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user