mirror of
https://github.com/sanni/cartreader.git
synced 2024-11-30 00:14:15 +01:00
Update PCW.ino
- Added : size detection for Multi-pack cartridges - Modified : dump function for Multi-pack cartridges - Added : timing fixes needed for recent HW revisions
This commit is contained in:
PsyK0p4T
GitHub
parent
b11330d31b
commit
8fdd93f293
@ -92,7 +92,8 @@
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#define ADDR_WRITE DDRC = 0xFF // [OUTPUT]
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#define DETECTION_SIZE 64
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boolean multipack = 0; // Multi-Pack Cart
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uint32_t rom_size;
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boolean multipack;
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byte bank0;
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byte bank1;
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@ -127,9 +128,6 @@ void setup_PCW() {
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// Set Unused Pins HIGH
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PORTJ |= (1 << 0); // TIME(PJ0)
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// Multi-Pack Cart Check
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check_multi_PCW();
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strcpy(romName, "PCW");
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mode = mode_PCW;
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@ -151,10 +149,11 @@ void pcwMenu() {
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case 0:
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// Read ROM
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sd.chdir("/");
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check_multi_PCW();
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if (multipack)
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readMultiROM_PCW();
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else
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readROM_PCW();
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readSingleROM_PCW();
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sd.chdir("/");
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break;
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@ -370,99 +369,53 @@ void write_ram_byte_1B_PCW(unsigned long address, unsigned char data) {
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NAND_1B_HIGH;
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}
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//==============================================================================
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// Overload Multi-Pack Bank Switch
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//
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// Known Multi-Pack Carts (Yellow Label Carts)
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// 0BD400 [PS] (2MB Version)
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// 0BD400 [PS] (4MB Version)
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// 0BF400 [PL]
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// 1BF400 [PZ]
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// 8BD400 [CR]
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// 8BF400 [LP]
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// 9BF400 [SLP] (Undumped)
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// Per Overload, identify multi-pack cart by reading 0x3FFA-0x3FFE
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// Multi-Pack carts are non-zero
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// 0x3FFA - Current Cartridge Bank
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// 0x3FFC - Value to Switch to Cartridge Bank 0
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// 0x3FFD - Value to Switch to Cartridge Bank 1
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// 0x3FFE - Last Value written to 0xFFFF
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// Bank Settings for 2MB
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// Write 0x28 to 0xFFFF to read 1st half of ROM
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// Write 0x2E to 0xFFFF to read 2nd half of ROM
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// Bank Settings for 4MB
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// Write 0x20 to 0xFFFF to read 1st half of ROM
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// Write 0x31 to 0xFFFF to read 2nd half of ROM
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// MULTI-PACK CART CHECK
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void check_multi_PCW() {
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read_setup_PCW();
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byte tempbyte = read_rom_byte_PCW(0x3FFC); // Bank 0 Switch
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if (tempbyte) {
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bank0 = tempbyte; // Store Bank 0 Switch
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tempbyte = read_rom_byte_PCW(0x3FFD); // Bank 1 Switch
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if (tempbyte) {
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bank1 = tempbyte; // Store Bank 1 Switch
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// Check for 00s
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tempbyte = read_rom_byte_PCW(0x3FFB); // Should be 00
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if (!tempbyte) {
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tempbyte = read_rom_byte_PCW(0x3FFF); // Should be 00
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if (!tempbyte)
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multipack = 1; // Flag Multi-Cart
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else {
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bank0 = 0;
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bank1 = 0;
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}
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}
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}
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}
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}
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void write_bank_byte_PCW(unsigned char data) {
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NAND_1A_LOW;
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NAND_1A_HIGH;
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NAND_1B_LOW;
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// Write to Address 0xFFFF
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PORTL = 0x00;
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PORTK = 0xFF; // A8-A15
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// Latch Address on AD0-AD7
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ADDR_WRITE;
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LE_HIGH; // Latch Enable
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PORTC = 0xFF; // A0-A7
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LE_LOW; // Address Latched
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// Write Data on AD0-AD7 - WE LOW ~728-736ns
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WE_LOW;
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PORTC = data;
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__asm__("nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t");
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__asm__("nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t");
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WE_HIGH;
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NAND_1B_HIGH;
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}
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void switchBank_PCW(int bank) {
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if (bank == 1) { // Upper Half
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write_bank_byte_PCW(bank1);
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} else { // Lower Half (default)
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write_bank_byte_PCW(bank0);
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}
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}
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//******************************************
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// READ ROM FUNCTIONS
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// SINGLE-PACK FUNCTIONS
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//******************************************
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void readROM_PCW() {
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uint32_t detect_rom_size_PCW(void) {
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uint8_t read_byte;
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uint8_t current_byte;
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uint8_t detect_1m, detect_2m;
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//Initialize variables
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detect_1m = 0;
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detect_2m = 0;
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//Confirm where mirror address starts from (1MB, 2MB or 4MB)
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for (current_byte = 0; current_byte < DETECTION_SIZE; current_byte++) {
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if ((current_byte != detect_1m) && (current_byte != detect_2m)) {
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//If none matched, size is 4MB
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break;
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}
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read_byte = read_rom_byte_PCW(current_byte);
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if (current_byte == detect_1m) {
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if (read_rom_byte_PCW(0x100000 + current_byte) == read_byte) {
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detect_1m++;
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}
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}
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if (current_byte == detect_2m) {
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if (read_rom_byte_PCW(0x200000 + current_byte) == read_byte) {
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detect_2m++;
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}
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}
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}
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//ROM size detection
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if (detect_1m == DETECTION_SIZE) {
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rom_size = 0x100000;
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} else if (detect_2m == DETECTION_SIZE) {
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rom_size = 0x200000;
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} else {
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rom_size = 0x400000;
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}
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return rom_size;
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}
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void readSingleROM_PCW() {
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// Setup read mode
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read_setup_PCW();
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@ -473,7 +426,6 @@ void readROM_PCW() {
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print_Msg(rom_size / 1024 / 1024);
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print_Msg("MB SINGLE-PACK");
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println_Msg(F(""));
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display_Update();
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// Create file
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strcpy(fileName, romName);
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@ -516,22 +468,112 @@ void readROM_PCW() {
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// Wait for user input
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println_Msg(F(""));
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// Prints string out of the common strings array either with or without newline
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print_STR(press_button_STR, 1);
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display_Update();
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wait();
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}
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//******************************************
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// MULTI-PACK FUNCTIONS
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//******************************************
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// Known Multi-Pack Carts (Yellow Label Carts)
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// 0BD400 [PS] (2MB Version)
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// 0BD400 [PS] (4MB Version)
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// 0BF400 [PL]
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// 1BF400 [PZ]
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// 8BD400 [CR]
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// 8BF400 [LP]
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// 9BF400 [SLP] (Undumped)
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// Per Overload, identify multi-pack cart by reading 0x3FFA-0x3FFE. Multi-Pack carts are non-zero.
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// 0x3FFA - Current Cartridge Bank
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// 0x3FFC - Value to Switch to Cartridge Bank 0
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// 0x3FFD - Value to Switch to Cartridge Bank 1
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// 0x3FFE - Last Value written to 0xFFFF
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// Bank Settings for 2MB
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// Write 0x28 to 0xFFFF to read 1st half of ROM
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// Write 0x2E to 0xFFFF to read 2nd half of ROM
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// Bank Settings for 4MB
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// Write 0x20 to 0xFFFF to read 1st half of ROM
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// Write 0x31 to 0xFFFF to read 2nd half of ROM
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void check_multi_PCW() {
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// init variables
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read_setup_PCW();
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multipack = 0;
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bank0 = 0;
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bank1 = 0;
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byte tempbyte = read_rom_byte_PCW(0x3FFC); // Check for a bank 0 switch value
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if (tempbyte) {
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bank0 = tempbyte; // Store bank 0 switch value
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tempbyte = read_rom_byte_PCW(0x3FFD); // Check for a bank 1 switch value
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if (tempbyte) {
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bank1 = tempbyte; // Store bank 1 switch value
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if (!read_rom_byte_PCW(0x3FFB) && !read_rom_byte_PCW(0x3FFF)) { // Check for 00s
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multipack = 1; // Flag as multi-pack
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display_Clear();
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if ((bank0 == 0x28) && (bank1 == 0x2E)) // 2MB multi-pack cart
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rom_size = 0x200000;
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else if ((bank0 == 0x20) && (bank1 == 0x31)) // 4MB multi-pack cart
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rom_size = 0x400000;
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else { // Warn for unknown bank switch values, size set to 4MB
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println_Msg(F("Warning: Unknown cart size"));
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rom_size = 0x400000;
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}
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}
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}
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}
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}
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void write_bank_byte_PCW(unsigned char data) {
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NAND_1A_LOW;
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NAND_1A_HIGH;
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NAND_1B_LOW;
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// Write to Address 0xFFFF
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PORTL = 0x00;
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PORTK = 0xFF; // A8-A15
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// Latch Address on AD0-AD7
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ADDR_WRITE;
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LE_HIGH; // Latch Enable
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PORTC = 0xFF; // A0-A7
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LE_LOW; // Address Latched
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// Write Data on AD0-AD7 - WE LOW ~728-736ns
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WE_LOW;
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PORTC = data;
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for (unsigned int x = 0; x < 40; x++)
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__asm__("nop\n\t");
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WE_HIGH;
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NAND_1B_HIGH;
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}
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void switchBank_PCW(int bank) {
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if (bank == 1) { // Upper Half
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write_bank_byte_PCW(bank1);
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} else { // Lower Half (default)
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write_bank_byte_PCW(bank0);
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}
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}
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void readMultiROM_PCW() {
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print_Msg(F("READING "));
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print_Msg(rom_size / 1024 / 1024);
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print_Msg("MB MULTI-PACK");
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println_Msg(F(""));
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// Create file
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strcpy(fileName, romName);
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strcat(fileName, ".pcw");
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EEPROM_readAnything(0, foldern);
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sprintf(folder, "PCW/ROM/%d", foldern);
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sd.mkdir(folder, true);
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sd.chdir(folder);
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display_Clear();
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print_STR(saving_to_STR, 0);
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print_Msg(folder);
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println_Msg(F("/..."));
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@ -544,41 +586,37 @@ void readMultiROM_PCW() {
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print_FatalError(sd_error_STR);
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}
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display_Clear();
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println_Msg(F("READING MULTI-PACK"));
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println_Msg(F(""));
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display_Update();
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// Init progress bar
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uint32_t progress = 0;
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draw_progressbar(0, 0x400000);
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draw_progressbar(0, rom_size);
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read_setup_PCW();
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// Lower Half
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read_setup_PCW();
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switchBank_PCW(0);
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for (unsigned long address = 0; address < 0x200000; address += 512) { // 2MB
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for (unsigned long address = 0; address < (rom_size / 2); address += 512) {
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for (unsigned int x = 0; x < 512; x++) {
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sdBuffer[x] = read_rom_byte_PCW(address + x);
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}
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myFile.write(sdBuffer, 512);
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progress += 512;
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draw_progressbar(progress, 0x400000);
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draw_progressbar(progress, rom_size);
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}
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read_setup_PCW();
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// Upper Half
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read_setup_PCW();
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switchBank_PCW(1);
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for (unsigned long address = 0x200000; address < 0x400000; address += 512) { // 2MB
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for (unsigned long address = 0x200000; address < (0x200000 + (rom_size / 2)); address += 512) {
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for (unsigned int x = 0; x < 512; x++) {
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sdBuffer[x] = read_rom_byte_PCW(address + x);
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}
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myFile.write(sdBuffer, 512);
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progress += 512;
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draw_progressbar(progress, 0x400000);
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draw_progressbar(progress, rom_size);
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}
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myFile.flush();
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myFile.close();
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// Reset Bank
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switchBank_PCW(0);
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@ -588,55 +626,11 @@ void readMultiROM_PCW() {
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// Wait for user input
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println_Msg(F(""));
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// Prints string out of the common strings array either with or without newline
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print_STR(press_button_STR, 1);
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display_Update();
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wait();
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}
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uint32_t detect_rom_size_PCW(void) {
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uint32_t rom_size;
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uint8_t read_byte;
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uint8_t current_byte;
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uint8_t detect_1m, detect_2m;
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//Initialize variables
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detect_1m = 0;
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detect_2m = 0;
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//Confirm where mirror address starts from (1MB, 2MB or 4MB)
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for (current_byte = 0; current_byte < DETECTION_SIZE; current_byte++) {
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if ((current_byte != detect_1m) && (current_byte != detect_2m)) {
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//If none matched, size is 4MB
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break;
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}
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read_byte = read_rom_byte_PCW(current_byte);
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if (current_byte == detect_1m) {
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if (read_rom_byte_PCW(0x100000 + current_byte) == read_byte) {
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detect_1m++;
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}
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}
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if (current_byte == detect_2m) {
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if (read_rom_byte_PCW(0x200000 + current_byte) == read_byte) {
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detect_2m++;
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}
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}
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}
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//ROM size detection
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if (detect_1m == DETECTION_SIZE) {
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rom_size = 0x100000;
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} else if (detect_2m == DETECTION_SIZE) {
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rom_size = 0x200000;
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} else {
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rom_size = 0x400000;
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}
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return rom_size;
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}
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//******************************************
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// SRAM FUNCTIONS
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//******************************************
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