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Merge pull request #41 from ramapcsx2/various

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various: work on SNES SA-1 init / reset; LED: skip red in attract mod…
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sanni 2019-09-05 15:46:05 +02:00 committed by GitHub
commit a03d78405c
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2 changed files with 42 additions and 20 deletions
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6
Cart_Reader/Cart_Reader.ino
View File

@ -39,6 +39,8 @@
Gens-gs - Megadrive checksum
**********************************************************************************/
#include <SdFat.h>
char ver[5] = "3.6";
/******************************************
@ -71,7 +73,6 @@ char ver[5] = "3.6";
#include <avr/wdt.h>
// SD Card
#include <SdFat.h>
#define sdSpeed SPI_FULL_SPEED
// SD Card (Pin 50 = MISO, Pin 51 = MOSI, Pin 52 = SCK, Pin 53 = SS)
#define chipSelectPin 53
@ -1158,6 +1159,9 @@ unsigned char questionBox_OLED(const __FlashStringHelper* question, char answers
if ((millis() - idleTime) % 4000 == 0) {
if (currentColor < 7) {
currentColor++;
if (currentColor == 1) {
currentColor = 2; // skip red as that signifies an error to the user
}
}
else {
currentColor = 0;

54
Cart_Reader/SNES.ino
View File

@ -216,6 +216,11 @@ void snesMenu() {
DDRH |= (1 << 0);
// Switch RST(PH0) to LOW
PORTH &= ~(1 << 0);
// Note: It is probably not intended to reset CIC or clocks here
// But if that's false, uncomment this:
// stopSnesClocks_resetCic_resetCart();
display_Clear();
print_Msg(F("Resetting..."));
display_Update();
@ -224,6 +229,7 @@ void snesMenu() {
break;
case 5:
stopSnesClocks_resetCic_resetCart();
resetArduino();
break;
}
@ -270,11 +276,22 @@ void confMenu() {
case 4:
// Reset
stopSnesClocks_resetCic_resetCart();
resetArduino();
break;
}
}
void stopSnesClocks_resetCic_resetCart() {
DDRG |= (1 << 1); // Set cicrstPin(PG1) to Output
PORTG |= (1 << 1); // pull high = reset CIC
DDRH |= (1 << 0); // Set RST(PH0) pin to Output
PORTH &= ~(1 << 0); // Switch RST(PH0) to LOW
clockgen.output_enable(SI5351_CLK1, 0); // CPU clock
clockgen.output_enable(SI5351_CLK2, 0); // CIC clock
clockgen.output_enable(SI5351_CLK0, 0); // master clock
}
/******************************************
Setup
*****************************************/
@ -286,16 +303,6 @@ void setup_Snes() {
// Set cichstPin(PG0) to Input
DDRG &= ~(1 << 0);
// Adafruit Clock Generator
clockgen.init(SI5351_CRYSTAL_LOAD_8PF, 0, 0);
clockgen.set_pll(SI5351_PLL_FIXED, SI5351_PLLA);
clockgen.set_pll(SI5351_PLL_FIXED, SI5351_PLLB);
clockgen.set_freq(2147727200ULL, SI5351_CLK0);
clockgen.set_freq(307200000ULL, SI5351_CLK2);
clockgen.output_enable(SI5351_CLK0, 1);
clockgen.output_enable(SI5351_CLK1, 0);
clockgen.output_enable(SI5351_CLK2, 1);
// Set Address Pins to Output
//A0-A7
DDRF = 0xFF;
@ -327,7 +334,7 @@ void setup_Snes() {
// Activate Internal Pullup Resistors
//PORTH |= (1 << 4);
// Set expand(PG5) to Imput
// Set expand(PG5) to Input
DDRG &= ~(1 << 5);
// Activate Internal Pullup Resistors
//PORTG |= (1 << 5);
@ -348,11 +355,25 @@ void setup_Snes() {
DDRJ |= (1 << 0);
//PORTJ &= ~(1 << 0);
// Adafruit Clock Generator
clockgen.init(SI5351_CRYSTAL_LOAD_8PF, 0, 0);
clockgen.set_pll(SI5351_PLL_FIXED, SI5351_PLLA);
clockgen.set_pll(SI5351_PLL_FIXED, SI5351_PLLB);
clockgen.set_freq(2147727200ULL, SI5351_CLK0);
clockgen.set_freq(357954500ULL, SI5351_CLK1);
clockgen.set_freq(307200000ULL, SI5351_CLK2);
// start outputting master clock, CIC clock
clockgen.output_enable(SI5351_CLK1, 0); // no CPU clock yet; seems to affect SA-1 success a lot
clockgen.output_enable(SI5351_CLK2, 1); // CIC clock (should go before master clock)
clockgen.output_enable(SI5351_CLK0, 1); // master clock
delay(8);
// Start CIC by outputting a low signal to cicrstPin(PG1)
PORTG &= ~(1 << 1);
// Wait for CIC reset
delay(1000);
delay(320);
// Print all the info
getCartInfo_SNES();
@ -1310,7 +1331,6 @@ void writeSRAM (boolean browseFile) {
else if (romType == SA) {
long lastByte = (long(sramSize) * 128);
// Enable CPU Clock
clockgen.set_freq(357954500ULL, SI5351_CLK1);
clockgen.output_enable(SI5351_CLK1, 1);
// Direct writes to BW-RAM (SRAM) in banks 0x40-0x43 don't work
@ -1689,10 +1709,9 @@ unsigned long verifySRAM() {
}
display_Update();
wait();
// Set reset pin to output (PH0)
DDRH |= (1 << 0);
// Switch RST(PH0) to LOW
PORTH &= ~(1 << 0);
stopSnesClocks_resetCic_resetCart();
display_Clear();
print_Msg(F("Resetting..."));
display_Update();
@ -1808,7 +1827,6 @@ boolean eraseSRAM (byte b) {
else if (romType == SA) {
long lastByte = (long(sramSize) * 128);
// Enable CPU Clock
clockgen.set_freq(357954500ULL, SI5351_CLK1);
clockgen.output_enable(SI5351_CLK1, 1);
// Direct writes to BW-RAM (SRAM) in banks 0x40-0x43 don't work