mirror of
https://github.com/sanni/cartreader.git
synced 2025-03-12 22:36:36 +01:00
Update NES.ino
- fixed mapper 52 - added mappers 49, 50, 55, 61 - added (ugly) workaround for Quattro carts until submappers are supported
This commit is contained in:
nsx0r
GitHub
parent
6194c20cb0
commit
a62e440c4d
@ -87,19 +87,19 @@ static const struct mapper_NES PROGMEM mapsize[] = {
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{ 46, 1, 6, 0, 8, 0, 0 }, // GameStation/RumbleStation
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{ 47, 4, 5, 6, 7, 0, 0 }, // Nintendo NES-QJ (2-in-1)
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{ 48, 3, 4, 6, 6, 0, 0 }, // Taito TC0690/TC0190+PAL16R4
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// 49 - 820401/T-217 (Super HIK 4-in-1 MMC3 multicart) [TODO]
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// 50 - N-32 (761214) [TODO]
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{ 49, 0, 5, 0, 7, 0, 0 }, // 820401/T-217 (Super HIK 4-in-1 MMC3 multicart)
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{ 50, 3, 3, 0, 0, 0, 0 }, // N-32 (761214)
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// 51 - 820718C [TODO]
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{ 52, 0, 5, 0, 7, 0, 0 }, // Realtec 8213
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// 53 - Supervision 16-in-1 [TODO]
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// 54 - not used
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// 55 - NCN-35A/BTL-MARIO1-MALEE2 [TODO]
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{ 55, 1, 1, 0, 0, 0, 0 }, // NCN-35A/BTL-MARIO1-MALEE2 [56KiB]
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{ 56, 0, 7, 0, 6, 0, 0 }, // Kaiser KS202 (SMB3)
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{ 57, 0, 3, 0, 5, 0, 0 }, // GK 6-in-1
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{ 58, 1, 6, 1, 6, 0, 0 }, // GK-192, duplicate of mapper 213
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{ 59, 0, 3, 0, 4, 0, 0 }, // BS-01/VT1512A (BMC-T3H53 + BMC-D1038)
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{ 60, 2, 2, 3, 3, 0, 0 }, // Reset-based NROM-128 (4-in-1 multicarts)
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// 61 - NTDEC GS-2017/0324 [TODO]
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{ 61, 0, 5, 0, 5, 0, 0 }, // NTDEC GS-2017/0324
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{ 62, 7, 7, 8, 8, 0, 0 }, // N-190B/K-1016/K-1017P (Super 700-in-1)
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{ 63, 8, 8, 0, 0, 0, 0 }, // NTDEC 2291 (Powerful multicart) / CH-011 / 82AB
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{ 64, 2, 3, 4, 5, 0, 0 }, // Tengen 800032 (RAMBO-1)
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@ -673,10 +673,11 @@ void printDataLine_NES(void* entry) {
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printNESSettings();
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}
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uint32_t oldcrc32 = 0xFFFFFFFF;
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uint32_t oldcrc32MMC3 = 0xFFFFFFFF;
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void getMapping() {
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FsFile database;
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uint32_t oldcrc32 = 0xFFFFFFFF;
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uint32_t oldcrc32MMC3 = 0xFFFFFFFF;
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char crcStr[9];
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display_Clear();
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@ -1911,7 +1912,7 @@ void readPRG(bool readrom) {
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write_prg_byte(0x8000, 0x80); // Clear Register
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write_mmc1_byte(0x8000, 0x0C); // Switch 16K Bank ($8000-$BFFF) + Fixed Last Bank ($C000-$FFFF)
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if (prgsize > 4) // 512K
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write_mmc1_byte(0xA000, 0x00); // Reset 512K Flag for Lower 256K
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write_mmc1_byte(0xA000, 0); // Reset 512K Flag for Lower 256K
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if (i > 15) // Switch Upper 256K
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write_mmc1_byte(0xA000, 0x10); // Set 512K Flag
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write_mmc1_byte(0xE000, i);
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@ -1943,6 +1944,8 @@ void readPRG(bool readrom) {
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case 12:
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case 37:
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case 47:
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case 49:
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case 52:
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case 64:
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case 76:
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case 88:
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@ -1966,10 +1969,10 @@ void readPRG(bool readrom) {
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banks = int_pow(2, prgsize) * 2;
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write_prg_byte(0xA001, 0x80); // Block Register - PRG RAM Chip Enable, Writable
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if (mapper == 126) {
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write_prg_byte(0x6003, 0x00); // set MMC3 banking mode
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write_prg_byte(0x6003, 0); // set MMC3 banking mode
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}
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if ((mapper == 115) || (mapper == 134) || (mapper == 248)) {
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write_prg_byte(0x6000, 0x00); // set MMC3 banking mode
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write_prg_byte(0x6000, 0); // set MMC3 banking mode
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}
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if (mapper == 176) {
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write_prg_byte(0x5FF3, 0); // extended MMC3 mode: disabled
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@ -1988,6 +1991,12 @@ void readPRG(bool readrom) {
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if (mapper == 47) {
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write_prg_byte(0x6000 + (i >> 4), 0);
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}
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if (mapper == 49) {
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write_prg_byte(0x6000, ((i & 0x30) << 2) | 1);
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}
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if (mapper == 52) {
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write_prg_byte(0x6000, (i & 0x70) >> 4);
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}
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if ((mapper == 115) || (mapper == 248)) {
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write_prg_byte(0x6000, (i & 0x10) << 2); // A18
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}
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@ -2003,12 +2012,12 @@ void readPRG(bool readrom) {
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if (mapper == 268) {
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write_prg_byte(0x5000, ((i & 0x70) >> 4) | ((i & 0xC00) >> 6));
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write_prg_byte(0x5001, ((i & 0x80) >> 3) | ((i & 0x300) >> 6) | 0x60);
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write_prg_byte(0x5002, 0x00);
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write_prg_byte(0x5003, 0x00);
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write_prg_byte(0x5002, 0);
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write_prg_byte(0x5003, 0);
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write_prg_byte(0x6000, ((i & 0x70) >> 4) | ((i & 0xC00) >> 6));
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write_prg_byte(0x6001, ((i & 0x80) >> 3) | ((i & 0x300) >> 6) | 0x60);
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write_prg_byte(0x6002, 0x00);
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write_prg_byte(0x6003, 0x00);
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write_prg_byte(0x6002, 0);
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write_prg_byte(0x6003, 0);
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}
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if (mapper == 315) {
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write_prg_byte(0x6800, (i & 30) >> 3);
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@ -2132,7 +2141,7 @@ void readPRG(bool readrom) {
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banks = int_pow(2, prgsize) * 2;
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// set vrc4 swap setting for TMNT2
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if (mapper == 25)
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write_prg_byte(0x9005, 0x00);
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write_prg_byte(0x9005, 0);
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for (size_t i = 0; i < banks; i += 2) {
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write_prg_byte(0x8000, i);
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write_prg_byte(0xA000, i + 1);
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@ -2169,7 +2178,7 @@ void readPRG(bool readrom) {
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write_prg_byte(0x8000, 0);
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write_prg_byte(0x5000, 0x01);
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write_prg_byte(0x8000, 0);
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write_prg_byte(0x5000, 0x00);
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write_prg_byte(0x5000, 0);
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write_prg_byte(0x8000, 0);
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for (size_t i = 0; i < banks; i++) {
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write_prg_byte(0x5000, 0x81);
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@ -2285,7 +2294,7 @@ void readPRG(bool readrom) {
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banks = ((int_pow(2, prgsize) * 2)) - 2; // Set Number of Banks
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for (size_t i = 0; i < banks; i += 2) { // 128K/256K/512K/1024K
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// set outer bank registers
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write_prg_byte(0x6000, 0x00); // CHR-OR
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write_prg_byte(0x6000, 0); // CHR-OR
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write_prg_byte(0x6000, (i & 0xC0)); // PRG-OR
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write_prg_byte(0x6000, ((i >> 2) & 0xC0)); // CHR-AND,CHR-OR/PRG-OR
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write_prg_byte(0x6000, 0x80); // PRG-AND
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@ -2294,7 +2303,7 @@ void readPRG(bool readrom) {
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write_prg_byte(0x8001, i);
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dumpBankPRG(0x0, 0x2000, base);
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// set outer bank registers
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write_prg_byte(0x6000, 0x00); // CHR-OR
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write_prg_byte(0x6000, 0); // CHR-OR
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write_prg_byte(0x6000, ((i + 1) & 0xC0)); // PRG-OR
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write_prg_byte(0x6000, (((i + 1) >> 2) & 0xC0)); // CHR-AND,CHR-OR/PRG-OR
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write_prg_byte(0x6000, 0x80); // PRG-AND
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@ -2315,6 +2324,22 @@ void readPRG(bool readrom) {
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}
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break;
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case 50:
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banks = int_pow(2, prgsize) * 2;
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for (size_t i = 0; i < banks; i++) {
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write_prg_byte(0x4122, (i & 0x08) | ((i & 0x03) << 1) | ((i & 0x04) >> 2));
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dumpBankPRG(0xC000, 0xE000, base);
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}
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break;
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case 55:
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dumpBankPRG(0x0, 0x8000, base);
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base = 0x6000;
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for (size_t i = 0; i < 8; i++) {
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dumpBankPRG(0x0, 0x0800, base);
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}
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break;
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case 56:
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banks = int_pow(2, prgsize) * 2;
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for (size_t i = 0; i < banks; i++) {
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@ -2337,7 +2362,7 @@ void readPRG(bool readrom) {
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case 213:
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banks = int_pow(2, prgsize);
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for (size_t i = 0; i < banks; i += 2) {
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write_prg_byte(0x8000 + (i & 0x07), 0x00);
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write_prg_byte(0x8000 + (i & 0x07), 0);
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dumpBankPRG(0x0, 0x8000, base);
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}
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break;
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@ -2359,19 +2384,19 @@ void readPRG(bool readrom) {
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}
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break;
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case 62:
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banks = int_pow(2, prgsize) / 2;
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case 61:
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banks = int_pow(2, prgsize);
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for (size_t i = 0; i < banks; i++) {
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write_prg_byte(0x8000 + (i * 512) + ((i & 32) << 1), 0x00);
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dumpBankPRG(0x0, 0x8000, base);
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write_prg_byte(0x8010 | ((i & 0x01) << 5) | ((i >> 1) & 0x0F), 0);
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dumpBankPRG(0x0, 0x4000, base);
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}
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break;
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case 66: // 64K/128K
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case 62:
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banks = int_pow(2, prgsize) / 2;
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for (size_t i = 0; i < banks; i++) { // 64K/128K
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write_prg_byte(0x8000, i << 4); // bits 4-5
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dumpBankPRG(0x0, 0x8000, base); // 32K Banks ($8000-$FFFF)
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for (size_t i = 0; i < banks; i++) {
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write_prg_byte(0x8000 + (i * 512) + ((i & 32) << 1), 0);
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dumpBankPRG(0x0, 0x8000, base);
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}
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break;
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@ -2383,6 +2408,14 @@ void readPRG(bool readrom) {
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}
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break;
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case 66: // 64K/128K
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banks = int_pow(2, prgsize) / 2;
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for (size_t i = 0; i < banks; i++) { // 64K/128K
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write_prg_byte(0x8000, i << 4); // bits 4-5
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dumpBankPRG(0x0, 0x8000, base); // 32K Banks ($8000-$FFFF)
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}
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break;
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case 67: // 128K
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banks = int_pow(2, prgsize);
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for (size_t i = 0; i < banks; i++) { // 128K
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@ -2540,7 +2573,7 @@ void readPRG(bool readrom) {
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break;
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case 105: // 256K
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write_mmc1_byte(0xA000, 0x00); // Clear PRG Init/IRQ (Bit 4)
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write_mmc1_byte(0xA000, 0); // Clear PRG Init/IRQ (Bit 4)
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write_mmc1_byte(0xA000, 0x10); // Set PRG Init/IRQ (Bit 4) to enable bank swapping
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for (size_t i = 0; i < 4; i++) { // PRG CHIP 1 128K
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write_mmc1_byte(0xA000, i << 1);
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@ -2788,13 +2821,23 @@ void readPRG(bool readrom) {
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break;
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case 232:
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banks = int_pow(2, prgsize) / 4;
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for (size_t outerbank = 0; outerbank < 4; outerbank++) {
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write_prg_byte(0x8000, outerbank << 3);
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for (size_t i = 0; i < banks; i++) {
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write_prg_byte(0xC000, i);
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if (oldcrc32 == 0x2B50A29C || oldcrc32 == 0x9DF7D376 || oldcrc32 == 0x596EC6E6 || oldcrc32 == 0xD003AFCA || oldcrc32 == 0x5004C6CF || oldcrc32 == 0x59D7D89D || oldcrc32 == 0x017D903E || oldcrc32 == 0xC1E6A786 || oldcrc32 == 0xD43AC4BE || oldcrc32 == 0x3E54E71D || oldcrc32 == 0x3D8497EA || oldcrc32MMC3 == 0x2B50A29C || oldcrc32MMC3 == 0x9DF7D376 || oldcrc32MMC3 == 0x596EC6E6 || oldcrc32MMC3 == 0xD003AFCA || oldcrc32MMC3 == 0x5004C6CF || oldcrc32MMC3 == 0x59D7D89D || oldcrc32MMC3 == 0x017D903E || oldcrc32MMC3 == 0xC1E6A786 || oldcrc32MMC3 == 0xD43AC4BE || oldcrc32MMC3 == 0x3E54E71D || oldcrc32MMC3 == 0x3D8497EA) {
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println_Msg(F("DUMPING QUATTRO CART"));
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display_Update();
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for (size_t i = 0; i < 16; i++) {
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write_prg_byte(0x8000, ((i & 0x04) << 2) | (i & 0x08));
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write_prg_byte(0xC000, i & 0x03);
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dumpBankPRG(0x0, 0x4000, base);
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}
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} else {
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banks = int_pow(2, prgsize) / 4;
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for (size_t outerbank = 0; outerbank < 4; outerbank++) {
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write_prg_byte(0x8000, outerbank << 3);
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for (size_t i = 0; i < banks; i++) {
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write_prg_byte(0xC000, i);
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dumpBankPRG(0x0, 0x4000, base);
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}
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}
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}
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break;
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@ -2956,6 +2999,7 @@ void readCHR(bool readrom) {
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switch (mapper) {
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case 0: // 8K
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case 43:
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case 55:
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dumpBankCHR(0x0, 0x2000);
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break;
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@ -2996,6 +3040,7 @@ void readCHR(bool readrom) {
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case 12:
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case 37:
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case 47:
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case 49:
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case 52:
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case 64:
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case 76:
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@ -3015,10 +3060,10 @@ void readCHR(bool readrom) {
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banks = int_pow(2, chrsize) * 4;
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write_prg_byte(0xA001, 0x80);
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if (mapper == 126) {
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write_prg_byte(0x6003, 0x00); // set MMC3 banking mode
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write_prg_byte(0x6003, 0); // set MMC3 banking mode
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}
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if ((mapper == 115) || (mapper == 134) || (mapper == 248)) {
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write_prg_byte(0x6000, 0x00); // set MMC3 banking mode
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write_prg_byte(0x6000, 0); // set MMC3 banking mode
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}
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if (mapper == 176) {
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write_prg_byte(0x5FF3, 0); // extended MMC3 mode: disabled
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@ -3040,6 +3085,9 @@ void readCHR(bool readrom) {
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if (mapper == 47) {
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write_prg_byte(0x6800 + ((i & 0x180) >> 7), 0);
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}
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if (mapper == 49) {
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write_prg_byte(0x6800, ((i & 0x180) >> 1) | 1);
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}
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if (mapper == 52) {
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write_prg_byte(0x6000, (i & 0x180) >> 3 | (i & 0x200) >> 7);
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}
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@ -3233,7 +3281,7 @@ void readCHR(bool readrom) {
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case 26: // 128K/256K
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banks = int_pow(2, chrsize) * 4;
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write_prg_byte(0xB003, 0x00);
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write_prg_byte(0xB003, 0);
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for (size_t i = 0; i < banks; i += 4) {
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write_prg_byte(0xD000, i + 0); // CHR Bank 0
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write_prg_byte(0xD002, i + 1); // CHR Bank 1
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@ -3310,8 +3358,8 @@ void readCHR(bool readrom) {
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case 41:
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banks = int_pow(2, chrsize) / 2;
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for (size_t i = 0; i < banks; i++) {
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write_prg_byte(0x6004 + ((i & 0x0C) << 1), 0x00);
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write_prg_byte(0x6004 + ((i & 0x0C) << 1), 0x00);
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write_prg_byte(0x6004 + ((i & 0x0C) << 1), 0);
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write_prg_byte(0x6004 + ((i & 0x0C) << 1), 0);
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write_prg_byte(0xFFF0 + (i & 0x03), i & 0x03);
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write_prg_byte(0xFFF0 + (i & 0x03), i & 0x03);
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dumpBankCHR(0x0, 0x2000);
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@ -3331,8 +3379,8 @@ void readCHR(bool readrom) {
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write_prg_byte(0xA001, 0x80); // Unlock Write Protection - not used by some carts
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for (size_t i = 0; i < banks; i++) {
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// set outer bank registers
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write_prg_byte(0x6000, 0x00); // CHR-OR
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write_prg_byte(0x6000, 0x00); // PRG-OR
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write_prg_byte(0x6000, 0); // CHR-OR
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write_prg_byte(0x6000, 0); // PRG-OR
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write_prg_byte(0x6000, (((i / 256) << 4) | 0x0F)); // CHR-AND,CHR-OR/PRG-OR
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write_prg_byte(0x6000, 0x80); // PRG-AND
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// set inner bank registers
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@ -3342,8 +3390,8 @@ void readCHR(bool readrom) {
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dumpCHR_M2(address); // Read CHR with M2 Pulse
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}
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// set outer bank registers
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write_prg_byte(0x6000, 0x00); // CHR-OR
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write_prg_byte(0x6000, 0x00); // PRG-OR
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write_prg_byte(0x6000, 0); // CHR-OR
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write_prg_byte(0x6000, 0); // PRG-OR
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write_prg_byte(0x6000, (((i / 256) << 4) | 0x0F)); // CHR-AND,CHR-OR/PRG-OR
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write_prg_byte(0x6000, 0x80); // PRG-AND
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// set inner bank registers
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@ -3385,7 +3433,7 @@ void readCHR(bool readrom) {
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case 213:
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banks = int_pow(2, chrsize) / 2;
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for (size_t i = 0; i < banks; i++) {
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write_prg_byte(0x8000 + ((i & 0x07) << 3), 0x00);
|
||||
write_prg_byte(0x8000 + ((i & 0x07) << 3), 0);
|
||||
dumpBankCHR(0x0, 0x2000);
|
||||
}
|
||||
break;
|
||||
@ -3406,6 +3454,14 @@ void readCHR(bool readrom) {
|
||||
}
|
||||
break;
|
||||
|
||||
case 61:
|
||||
banks = int_pow(2, chrsize) / 2;
|
||||
for (size_t i = 0; i < banks; i++) {
|
||||
write_prg_byte(0x8000 | (i << 8), 0);
|
||||
dumpBankCHR(0x0, 0x2000);
|
||||
}
|
||||
break;
|
||||
|
||||
case 62:
|
||||
banks = int_pow(2, chrsize) / 2;
|
||||
for (size_t i = 0; i < banks; i++) {
|
||||
@ -3494,7 +3550,7 @@ void readCHR(bool readrom) {
|
||||
case 207: // 128K [CART SOMETIMES NEEDS POWERCYCLE]
|
||||
case 552:
|
||||
banks = int_pow(2, chrsize) * 2;
|
||||
write_prg_byte(0x7EF6, 0x00); // CHR mode [2x 2KiB banks at $0000-$0FFF]
|
||||
write_prg_byte(0x7EF6, 0); // CHR mode [2x 2KiB banks at $0000-$0FFF]
|
||||
for (size_t i = 0; i < banks; i += 2) {
|
||||
write_prg_byte(0x7EF0, i << 1);
|
||||
write_prg_byte(0x7EF1, (i + 1) << 1);
|
||||
@ -3768,18 +3824,6 @@ void readCHR(bool readrom) {
|
||||
dumpBankCHR(0x1000, 0x1400);
|
||||
}
|
||||
break;
|
||||
|
||||
case 332:
|
||||
banks = int_pow(2, chrsize) / 2;
|
||||
for (int i = 0; i < banks; i++) {
|
||||
write_prg_byte(0x6001, 0x30 | (i & 0x07)); // NROM mode, A15-A13
|
||||
write_prg_byte(0x6001, 0x30 | (i & 0x07)); // NROM mode, A15-A13
|
||||
write_prg_byte(0x6000, (i & 0x08) << 3); // A16
|
||||
write_prg_byte(0x6000, (i & 0x08) << 3); // A16
|
||||
delay(100);
|
||||
dumpBankCHR(0x0, 0x2000);
|
||||
}
|
||||
break;
|
||||
}
|
||||
if (!readrom) {
|
||||
myFile.flush();
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user