mirror of
https://github.com/sanni/cartreader.git
synced 2024-11-14 08:55:06 +01:00
commit
b5101b892d
@ -25,6 +25,12 @@
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#include "options.h"
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#include "options.h"
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#ifdef enable_WS
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#ifdef enable_WS
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#ifdef ws_adapter_v2
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#define WS_CLK_BIT 5 // USE PE5 as CLK
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#else
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#define WS_CLK_BIT 3 // USE PE3 as CLK
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#endif
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/******************************************
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/******************************************
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Menu
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Menu
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*****************************************/
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*****************************************/
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@ -61,8 +67,8 @@ void setup_WS()
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PORTH |= ((1 << 0) | (1 << 3) | (1 << 4) | (1 << 5) | (1 << 6));
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PORTH |= ((1 << 0) | (1 << 3) | (1 << 4) | (1 << 5) | (1 << 6));
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// CLK outputs LOW
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// CLK outputs LOW
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DDRE |= (1 << 3);
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DDRE |= (1 << WS_CLK_BIT);
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PORTE &= ~(1 << 3);
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PORTE &= ~(1 << WS_CLK_BIT);
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// IO? as input with internal pull-up enabled
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// IO? as input with internal pull-up enabled
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DDRE &= ~(1 << 4);
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DDRE &= ~(1 << 4);
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@ -218,6 +224,8 @@ uint8_t getCartInfo_WS()
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// games missing 'COLOR' flag
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// games missing 'COLOR' flag
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case 0x26db: // SQRC01
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case 0x26db: // SQRC01
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case 0xbfdf: // SUMC07
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case 0xbfdf: // SUMC07
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case 0x50ca: // BANC09
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case 0x9238: // BANC0E
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{
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{
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sdBuffer[7] |= 0x01;
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sdBuffer[7] |= 0x01;
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break;
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break;
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@ -297,6 +305,12 @@ uint8_t getCartInfo_WS()
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}
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}
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}
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}
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}
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}
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else if (sdBuffer[6] == 0x2a && sdBuffer[8] == 0x01 && sdBuffer[9] == 0x01)
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{
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// Mobile WonderGate v1.1, checksum is filled with 0x0000
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wsGameChecksum = 0x1da0;
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}
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break;
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break;
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}
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}
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}
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}
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@ -429,6 +443,7 @@ void getDeveloperName(uint8_t id, char *buf, size_t length)
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case 0x26: devName = PSTR("KDK"); break;
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case 0x26: devName = PSTR("KDK"); break;
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case 0x27: devName = PSTR("SHL"); break;
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case 0x27: devName = PSTR("SHL"); break;
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case 0x28: devName = PSTR("SQR"); break;
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case 0x28: devName = PSTR("SQR"); break;
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case 0x2a: devName = PSTR("SCC"); break;
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case 0x2b: devName = PSTR("TMC"); break;
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case 0x2b: devName = PSTR("TMC"); break;
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case 0x2d: devName = PSTR("NMC"); break;
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case 0x2d: devName = PSTR("NMC"); break;
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case 0x2e: devName = PSTR("SES"); break;
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case 0x2e: devName = PSTR("SES"); break;
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@ -479,6 +494,9 @@ void readROM_WS(char *outPathBuf, size_t bufferSize)
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// get correct starting rom bank
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// get correct starting rom bank
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uint16_t bank = (256 - (cartSize >> 16));
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uint16_t bank = (256 - (cartSize >> 16));
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uint32_t progress = 0;
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draw_progressbar(0, cartSize);
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// start reading rom
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// start reading rom
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for (; bank <= 0xff; bank++)
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for (; bank <= 0xff; bank++)
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@ -502,7 +520,10 @@ void readROM_WS(char *outPathBuf, size_t bufferSize)
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* ((uint16_t*)(sdBuffer + w)) = readWord_WS(0x20000 + addr + w);
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* ((uint16_t*)(sdBuffer + w)) = readWord_WS(0x20000 + addr + w);
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myFile.write(sdBuffer, 512);
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myFile.write(sdBuffer, 512);
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progress += 512;
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}
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}
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draw_progressbar(progress, cartSize);
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}
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}
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// turn off LEDs (only for BANC33)
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// turn off LEDs (only for BANC33)
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@ -1214,10 +1235,10 @@ void generateEepromInstruction_WS(uint8_t *instruction, uint8_t opcode, uint16_t
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boolean unlockMMC2003_WS()
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boolean unlockMMC2003_WS()
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{
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{
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// initialize all control pin state
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// initialize all control pin state
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// RST(PH0) and CLK(PE3) to LOW
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// RST(PH0) and CLK(PE3or5) to LOW
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// CART(PH3) MMC(PH4) WE(PH5) OE(PH6) to HIGH
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// CART(PH3) MMC(PH4) WE(PH5) OE(PH6) to HIGH
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PORTH &= ~(1 << 0);
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PORTH &= ~(1 << 0);
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PORTE &= ~(1 << 3);
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PORTE &= ~(1 << WS_CLK_BIT);
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PORTH |= ((1 << 3) | (1 << 4) | (1 << 5) | (1 << 6));
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PORTH |= ((1 << 3) | (1 << 4) | (1 << 5) | (1 << 6));
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// switch RST(PH0) to HIGH
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// switch RST(PH0) to HIGH
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@ -1256,7 +1277,7 @@ boolean unlockMMC2003_WS()
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return false;
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return false;
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}
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}
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// doing a L->H on CLK(PE3) pin
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// doing a L->H on CLK pin
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void pulseCLK_WS(uint8_t count)
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void pulseCLK_WS(uint8_t count)
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{
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{
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register uint8_t tic;
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register uint8_t tic;
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@ -1267,12 +1288,12 @@ void pulseCLK_WS(uint8_t count)
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"cpi %[count], 0\n\t"
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"cpi %[count], 0\n\t"
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"breq L3_%=\n\t"
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"breq L3_%=\n\t"
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"dec %[count]\n\t"
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"dec %[count]\n\t"
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"cbi %[porte], 3\n\t"
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"cbi %[porte], %[ws_clk_bit]\n\t"
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"ldi %[tic], 6\n\t"
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"ldi %[tic], 6\n\t"
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"L1_%=:\n\t"
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"L1_%=:\n\t"
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"dec %[tic]\n\t"
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"dec %[tic]\n\t"
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"brne L1_%=\n\t"
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"brne L1_%=\n\t"
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"sbi %[porte], 3\n\t"
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"sbi %[porte], %[ws_clk_bit]\n\t"
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"ldi %[tic], 5\n\t"
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"ldi %[tic], 5\n\t"
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"L2_%=:\n\t"
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"L2_%=:\n\t"
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"dec %[tic]\n\t"
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"dec %[tic]\n\t"
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@ -1280,7 +1301,7 @@ void pulseCLK_WS(uint8_t count)
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"rjmp L0_%=\n\t"
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"rjmp L0_%=\n\t"
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"L3_%=:\n\t"
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"L3_%=:\n\t"
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: [tic] "=a" (tic)
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: [tic] "=a" (tic)
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: [count] "a" (count), [porte] "I" (_SFR_IO_ADDR(PORTE))
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: [count] "a" (count), [porte] "I" (_SFR_IO_ADDR(PORTE)), [ws_clk_bit] "I" (WS_CLK_BIT)
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);
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);
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}
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}
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@ -24,6 +24,7 @@
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#define enable_rotary
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#define enable_rotary
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#define clockgen_installed
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#define clockgen_installed
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#define fastcrc
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#define fastcrc
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#define ws_adapter_v2
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#endif
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#endif
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#if (defined(HW2) || defined(HW3))
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#if (defined(HW2) || defined(HW3))
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