mirror of
https://github.com/sanni/cartreader.git
synced 2024-11-10 23:15:08 +01:00
Fix reading/writing 4MB HiROM
HiROM starts at bank 192 and has 64 banks so byte variable currBank overflows.
This commit is contained in:
parent
a3feb32e15
commit
cc17c70e30
@ -109,7 +109,7 @@ char ver[5] = "11.1";
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#define enable_PCE
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// Benesse Pocket Challenge W
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//#define enable_PCW
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#define enable_PCW
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// Sega Master System
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#define enable_SMS
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@ -127,10 +127,10 @@ char ver[5] = "11.1";
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#define enable_VBOY
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// WonderSwan
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//#define enable_WS
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#define enable_WS
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// Watara Supervision
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//#define enable_WSV
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#define enable_WSV
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//******************************************
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// HW CONFIGS
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@ -298,9 +298,9 @@ bool i2c_found;
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#include "FreqCount.h"
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#endif
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void _print_FatalError(void) __attribute__ ((noreturn));
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void print_FatalError(const __FlashStringHelper* errorMessage) __attribute__ ((noreturn));
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void print_FatalError(byte errorMessage) __attribute__ ((noreturn));
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void _print_FatalError(void) __attribute__((noreturn));
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void print_FatalError(const __FlashStringHelper* errorMessage) __attribute__((noreturn));
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void print_FatalError(byte errorMessage) __attribute__((noreturn));
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/******************************************
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Common Strings
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@ -495,7 +495,7 @@ byte sdBuffer[512];
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// soft reset Arduino: jumps to 0
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// using the watchdog timer would be more elegant but some Mega2560 bootloaders are buggy with it
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void (*resetArduino)(void) __attribute__ ((noreturn)) = 0;
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void (*resetArduino)(void) __attribute__((noreturn)) = 0;
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// Progressbar
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void draw_progressbar(uint32_t processedsize, uint32_t totalsize);
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@ -1074,7 +1074,7 @@ void mainMenu() {
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break;
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default:
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print_MissingModule(); // does not return
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print_MissingModule(); // does not return
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}
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}
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@ -1168,7 +1168,7 @@ void mainMenu() {
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break;
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default:
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print_MissingModule(); // does not return
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print_MissingModule(); // does not return
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}
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}
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@ -1207,7 +1207,7 @@ void addonMenu() {
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break;
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default:
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print_MissingModule(); // does not return
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print_MissingModule(); // does not return
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}
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}
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@ -1263,7 +1263,7 @@ void consoleMenu() {
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break;
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default:
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print_MissingModule(); // does not return
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print_MissingModule(); // does not return
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}
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}
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@ -1321,7 +1321,7 @@ void handheldMenu() {
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break;
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default:
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print_MissingModule(); // does not return
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print_MissingModule(); // does not return
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}
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}
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#endif
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@ -1983,7 +1983,7 @@ void print_FatalError(const __FlashStringHelper* errorMessage) {
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_print_FatalError();
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}
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void print_FatalError(byte errorMessage){
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void print_FatalError(byte errorMessage) {
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print_Error(errorMessage);
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_print_FatalError();
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}
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@ -3319,4 +3319,4 @@ void loop() {
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//******************************************
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// End of File
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//******************************************
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//******************************************
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@ -565,12 +565,12 @@ void writeByte_GBA(unsigned long myAddress, byte myData) {
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*****************************************/
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// Compute the checksum of rom header
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// "header" must contain at least the rom's first 188 bytes
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byte checksumHeader_GBA(const byte *header) {
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byte result = 0x00;
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for (byte n = 0xA0; n < 0xBD; n++) {
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result -= header[n];
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}
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return result - 0x19;
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byte checksumHeader_GBA(const byte* header) {
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byte result = 0x00;
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for (byte n = 0xA0; n < 0xBD; n++) {
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result -= header[n];
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}
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return result - 0x19;
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}
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// Read info out of rom header
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@ -586,7 +586,7 @@ void writeWord_N64(word myWord) {
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*****************************************/
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static word addrCRC(word address) {
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const char n64_address_crc_table[] = { 0x15, 0x1F, 0x0B, 0x16, 0x19, 0x07, 0x0E, 0x1C, 0x0D, 0x1A, 0x01 };
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const char *cur_xor = n64_address_crc_table;
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const char* cur_xor = n64_address_crc_table;
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byte crc = 0;
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for (word mask = 0x0020; mask; mask <<= 1, cur_xor++) {
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if (address & mask) {
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@ -618,23 +618,23 @@ static uint8_t dataCRC(uint8_t* data) {
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// (3 instructions) making it the same size as the equivalent 3-cycles NOP
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// delay. For shorter delays or non-multiple-of-3-cycle delays, add your own
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// NOPs.
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#define N64_DELAY_LOOP(cycle_count) do { \
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byte i; \
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__asm__ __volatile__ ("\n" \
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"\tldi %[i], %[loop_count]\n" \
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".delay_loop_%=:\n" \
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"\tdec %[i]\n" \
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"\tbrne .delay_loop_%=\n" \
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: [i] "=r" (i) \
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: [loop_count] "i" (cycle_count / 3) \
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: "cc" \
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); \
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} while(0)
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#define N64_DELAY_LOOP(cycle_count) \
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do { \
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byte i; \
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__asm__ __volatile__("\n" \
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"\tldi %[i], %[loop_count]\n" \
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".delay_loop_%=:\n" \
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"\tdec %[i]\n" \
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"\tbrne .delay_loop_%=\n" \
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: [i] "=r"(i) \
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: [loop_count] "i"(cycle_count / 3) \
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: "cc"); \
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} while (0)
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/******************************************
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N64 Controller Protocol Functions
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*****************************************/
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void sendJoyBus(const byte *buffer, char length) {
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void sendJoyBus(const byte* buffer, char length) {
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// Implemented in assembly as there is very little wiggle room, timing-wise.
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// Overall structure:
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// outer_loop:
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@ -678,130 +678,129 @@ void sendJoyBus(const byte *buffer, char length) {
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const byte line_low = DDRH | 0x10;
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const byte line_high = line_low & 0xef;
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__asm__ __volatile__("\n"
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".outer_loop_%=:\n"
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// mask = 0x80
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"\tldi %[mask], 0x80\n" // 1
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// load byte to send from memory
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"\tld %[cur_byte], Z+\n" // 2
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".inner_loop_%=:\n"
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// Falling edge
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"\tsts %[out_byte], %[line_low]\n" // 2
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// Test cur_byte & mask, without clobbering either
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"\tmov %[scratch], %[cur_byte]\n" // 1
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"\tand %[scratch], %[mask]\n" // 1
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"\tbreq .bit_is_0_%=\n" // bit is 1: 1, bit is 0: 2
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".outer_loop_%=:\n"
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// mask = 0x80
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"\tldi %[mask], 0x80\n" // 1
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// load byte to send from memory
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"\tld %[cur_byte], Z+\n" // 2
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".inner_loop_%=:\n"
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// Falling edge
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"\tsts %[out_byte], %[line_low]\n" // 2
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// Test cur_byte & mask, without clobbering either
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"\tmov %[scratch], %[cur_byte]\n" // 1
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"\tand %[scratch], %[mask]\n" // 1
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"\tbreq .bit_is_0_%=\n" // bit is 1: 1, bit is 0: 2
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// bit is a 1
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// Stay low for 1us (16 cycles).
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// Time before: 3 cycles (mov, and, breq-false).
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// Time after: sts (2 cycles).
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// So 11 to go, so 3 3-cycles iterations and 2 nop.
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"\tldi %[scratch], 3\n" // 1
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".delay_1_low_%=:\n"
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"\tdec %[scratch]\n" // 1
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"\tbrne .delay_1_low_%=\n" // exit: 1, loop: 2
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"\tnop\n" // 1
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"\tnop\n" // 1
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// Rising edge
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"\tsts %[out_byte], %[line_high]\n" // 2
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// Wait for 2us (32 cycles) to sync with the bot_is_0 codepath.
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// Time before: 0 cycles.
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// Time after: 2 cycles (rjmp).
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// So 30 to go, so 10 3-cycles iterations and 0 nop.
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"\tldi %[scratch], 10\n" // 1
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".delay_1_high_%=:\n"
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"\tdec %[scratch]\n" // 1
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"\tbrne .delay_1_high_%=\n" // exit: 1, loop: 2
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"\trjmp .inner_common_path_%=\n" // 2
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// bit is a 1
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// Stay low for 1us (16 cycles).
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// Time before: 3 cycles (mov, and, breq-false).
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// Time after: sts (2 cycles).
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// So 11 to go, so 3 3-cycles iterations and 2 nop.
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"\tldi %[scratch], 3\n" // 1
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".delay_1_low_%=:\n"
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"\tdec %[scratch]\n" // 1
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"\tbrne .delay_1_low_%=\n" // exit: 1, loop: 2
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"\tnop\n" // 1
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"\tnop\n" // 1
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// Rising edge
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"\tsts %[out_byte], %[line_high]\n" // 2
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// Wait for 2us (32 cycles) to sync with the bot_is_0 codepath.
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// Time before: 0 cycles.
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// Time after: 2 cycles (rjmp).
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// So 30 to go, so 10 3-cycles iterations and 0 nop.
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"\tldi %[scratch], 10\n" // 1
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".delay_1_high_%=:\n"
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"\tdec %[scratch]\n" // 1
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"\tbrne .delay_1_high_%=\n" // exit: 1, loop: 2
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"\trjmp .inner_common_path_%=\n" // 2
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".bit_is_0_%=:\n"
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// bit is a 0
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// Stay high for 3us (48 cycles).
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// Time before: 4 cycles (mov, and, breq-true).
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// Time after: 2 cycles (sts).
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// So 42 to go, so 14 3-cycles iterations, and 0 nop.
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"\tldi %[scratch], 14\n" // 1
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".delay_0_low_%=:\n"
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"\tdec %[scratch]\n" // 1
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"\tbrne .delay_0_low_%=\n" // exit: 1, loop: 2
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// Rising edge
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"\tsts %[out_byte], %[line_high]\n" // 2
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".bit_is_0_%=:\n"
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// bit is a 0
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// Stay high for 3us (48 cycles).
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// Time before: 4 cycles (mov, and, breq-true).
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// Time after: 2 cycles (sts).
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// So 42 to go, so 14 3-cycles iterations, and 0 nop.
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"\tldi %[scratch], 14\n" // 1
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".delay_0_low_%=:\n"
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"\tdec %[scratch]\n" // 1
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"\tbrne .delay_0_low_%=\n" // exit: 1, loop: 2
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// Rising edge
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"\tsts %[out_byte], %[line_high]\n" // 2
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// codepath common to both possible values
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".inner_common_path_%=:\n"
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"\tnop\n" // 1
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"\tlsr %[mask]\n" // 1
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"\tbreq .outer_loop_trailer_%=\n" // mask!=0: 1, mask==0: 2
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// Stay high for 1us (16 cycles).
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// Time before: 3 cycles (nop, lsr, breq-false).
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// Time after: 4 cycles (rjmp, sts)
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// So 9 to go, so 3 3-cycles iterations and 0 nop.
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"\tldi %[scratch], 3\n" // 1
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".delay_common_high_%=:\n"
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"\tdec %[scratch]\n" // 1
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"\tbrne .delay_common_high_%=\n" // exit: 1, loop: 2
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"\trjmp .inner_loop_%=\n" // 2
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// codepath common to both possible values
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".inner_common_path_%=:\n"
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"\tnop\n" // 1
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"\tlsr %[mask]\n" // 1
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"\tbreq .outer_loop_trailer_%=\n" // mask!=0: 1, mask==0: 2
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// Stay high for 1us (16 cycles).
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// Time before: 3 cycles (nop, lsr, breq-false).
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// Time after: 4 cycles (rjmp, sts)
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// So 9 to go, so 3 3-cycles iterations and 0 nop.
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"\tldi %[scratch], 3\n" // 1
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".delay_common_high_%=:\n"
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"\tdec %[scratch]\n" // 1
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"\tbrne .delay_common_high_%=\n" // exit: 1, loop: 2
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"\trjmp .inner_loop_%=\n" // 2
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".outer_loop_trailer_%=:\n"
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"\tdec %[length]\n" // 1
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"\tbreq .stop_bit_%=\n" // length!=0: 1, length==0: 2
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// Stay high for 1us (16 cycles).
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// Time before: 6 cycles (lsr, nop, breq-true, dec, breq-false).
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// Time after: 7 cycles (rjmp, ldi, ld, sts).
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// So 3 to go, so 3 nop (for simplicity).
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"\tnop\n" // 1
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"\tnop\n" // 1
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"\tnop\n" // 1
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"\trjmp .outer_loop_%=\n" // 2
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// Done sending data, send a stop bit.
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".stop_bit_%=:\n"
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// Stay high for 1us (16 cycles).
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// Time before: 7 cycles (lsr, nop, breq-true, dec, breq-true).
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// Time after: 2 cycles (sts).
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// So 7 to go, so 2 3-cycles iterations and 1 nop.
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"\tldi %[scratch], 2\n" // 1
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".delay_stop_high_%=:\n"
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"\tdec %[scratch]\n" // 1
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"\tbrne .delay_stop_high_%=\n" // exit: 1, loop: 2
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"\tnop\n"
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"\tsts %[out_byte], %[line_low]\n" // 2
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// Stay low for 1us (16 cycles).
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// Time before: 0 cycles.
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// Time after: 2 cycles (sts).
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// So 14 to go, so 4 3-cycles iterations and 2 nop.
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"\tldi %[scratch], 5\n" // 1
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".delay_stop_low_%=:\n"
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"\tdec %[scratch]\n" // 1
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"\tbrne .delay_stop_low_%=\n" // exit: 1, loop: 2
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"\tnop\n"
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"\tnop\n"
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"\tsts %[out_byte], %[line_high]\n" // 2
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// Notes on arguments:
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// - mask and scratch are used wth "ldi", which can only work on registers
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// 16 to 31, so tag these with "a" rather than the generic "r"
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// - mark all output-only arguments as early-clobber ("&"), as input
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// registers are used throughout all iterations and both sets must be
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// strictly distinct
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// - tag buffer with "z", to use the "ld r?, Z+" instruction (load from
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// 16bits RAM address and postincrement, in 2 cycles).
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// XXX: any pointer register pair would do, but mapping to Z explicitly
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// because I cannot find a way to get one of "X", "Y" or "Z" to appear
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// when expanding "%[buffer]", causing the assembler to reject the
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// instruction. Pick Z as it is the only call-used such register,
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// avoiding the need to preserve any value a caller may have set it to.
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: [buffer] "+z" (buffer),
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[length] "+r" (length),
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[cur_byte] "=&r" (cur_byte),
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[mask] "=&a" (mask),
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[scratch] "=&a" (scratch)
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: [line_low] "r" (line_low),
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[line_high] "r" (line_high),
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[out_byte] "i" (&DDRH)
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: "cc", "memory"
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);
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".outer_loop_trailer_%=:\n"
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"\tdec %[length]\n" // 1
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"\tbreq .stop_bit_%=\n" // length!=0: 1, length==0: 2
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// Stay high for 1us (16 cycles).
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// Time before: 6 cycles (lsr, nop, breq-true, dec, breq-false).
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// Time after: 7 cycles (rjmp, ldi, ld, sts).
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// So 3 to go, so 3 nop (for simplicity).
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"\tnop\n" // 1
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"\tnop\n" // 1
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"\tnop\n" // 1
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"\trjmp .outer_loop_%=\n" // 2
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// Done sending data, send a stop bit.
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".stop_bit_%=:\n"
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// Stay high for 1us (16 cycles).
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// Time before: 7 cycles (lsr, nop, breq-true, dec, breq-true).
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// Time after: 2 cycles (sts).
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// So 7 to go, so 2 3-cycles iterations and 1 nop.
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"\tldi %[scratch], 2\n" // 1
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".delay_stop_high_%=:\n"
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"\tdec %[scratch]\n" // 1
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"\tbrne .delay_stop_high_%=\n" // exit: 1, loop: 2
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"\tnop\n"
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"\tsts %[out_byte], %[line_low]\n" // 2
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// Stay low for 1us (16 cycles).
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// Time before: 0 cycles.
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// Time after: 2 cycles (sts).
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// So 14 to go, so 4 3-cycles iterations and 2 nop.
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"\tldi %[scratch], 5\n" // 1
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".delay_stop_low_%=:\n"
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"\tdec %[scratch]\n" // 1
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"\tbrne .delay_stop_low_%=\n" // exit: 1, loop: 2
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"\tnop\n"
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"\tnop\n"
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"\tsts %[out_byte], %[line_high]\n" // 2
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// Notes on arguments:
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// - mask and scratch are used wth "ldi", which can only work on registers
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// 16 to 31, so tag these with "a" rather than the generic "r"
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// - mark all output-only arguments as early-clobber ("&"), as input
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// registers are used throughout all iterations and both sets must be
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// strictly distinct
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// - tag buffer with "z", to use the "ld r?, Z+" instruction (load from
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// 16bits RAM address and postincrement, in 2 cycles).
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// XXX: any pointer register pair would do, but mapping to Z explicitly
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// because I cannot find a way to get one of "X", "Y" or "Z" to appear
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// when expanding "%[buffer]", causing the assembler to reject the
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// instruction. Pick Z as it is the only call-used such register,
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// avoiding the need to preserve any value a caller may have set it to.
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: [buffer] "+z"(buffer),
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[length] "+r"(length),
|
||||
[cur_byte] "=&r"(cur_byte),
|
||||
[mask] "=&a"(mask),
|
||||
[scratch] "=&a"(scratch)
|
||||
: [line_low] "r"(line_low),
|
||||
[line_high] "r"(line_high),
|
||||
[out_byte] "i"(&DDRH)
|
||||
: "cc", "memory");
|
||||
}
|
||||
|
||||
word recvJoyBus(byte *output, byte byte_count) {
|
||||
word recvJoyBus(byte* output, byte byte_count) {
|
||||
// listen for expected byte_count bytes of data back from the controller
|
||||
// return the number of bytes not (fully) received if the delay for a signal
|
||||
// edge takes too long.
|
||||
@ -829,84 +828,83 @@ word recvJoyBus(byte *output, byte byte_count) {
|
||||
|
||||
byte mask, cur_byte, timeout, scratch;
|
||||
__asm__ __volatile__("\n"
|
||||
"\tldi %[mask], 0x80\n"
|
||||
"\tclr %[cur_byte]\n"
|
||||
".read_loop_%=:\n"
|
||||
// Wait for input to be low. Time out if it takes more than ~27us (~7 bits
|
||||
// worth of time) for it to go low.
|
||||
// Takes 5 cycles to exit on input-low iteration (lds, sbrs-false, rjmp).
|
||||
// Takes 7 cycles to loop on input-high iteration (lds, sbrs-true, dec,
|
||||
// brne-true).
|
||||
"\tldi %[timeout], 0x3f\n" // 1
|
||||
".read_wait_falling_edge_%=:\n"
|
||||
"\tlds %[scratch], %[in_byte]\n" // 2
|
||||
"\tsbrs %[scratch], %[in_bit]\n" // low: 1, high: 2
|
||||
"\trjmp .read_input_low_%=\n" // 2
|
||||
"\tdec %[timeout]\n" // 1
|
||||
"\tbrne .read_wait_falling_edge_%=\n" // timeout==0: 1, timeout!=0: 2
|
||||
"\trjmp .read_end_%=\n" // 2
|
||||
"\tldi %[mask], 0x80\n"
|
||||
"\tclr %[cur_byte]\n"
|
||||
".read_loop_%=:\n"
|
||||
// Wait for input to be low. Time out if it takes more than ~27us (~7 bits
|
||||
// worth of time) for it to go low.
|
||||
// Takes 5 cycles to exit on input-low iteration (lds, sbrs-false, rjmp).
|
||||
// Takes 7 cycles to loop on input-high iteration (lds, sbrs-true, dec,
|
||||
// brne-true).
|
||||
"\tldi %[timeout], 0x3f\n" // 1
|
||||
".read_wait_falling_edge_%=:\n"
|
||||
"\tlds %[scratch], %[in_byte]\n" // 2
|
||||
"\tsbrs %[scratch], %[in_bit]\n" // low: 1, high: 2
|
||||
"\trjmp .read_input_low_%=\n" // 2
|
||||
"\tdec %[timeout]\n" // 1
|
||||
"\tbrne .read_wait_falling_edge_%=\n" // timeout==0: 1, timeout!=0: 2
|
||||
"\trjmp .read_end_%=\n" // 2
|
||||
|
||||
".read_input_low_%=:\n"
|
||||
// Wait for 1500 us (24 cycles) before reading input.
|
||||
// As it takes from 5 to 7 cycles for the prevous loop to exit,
|
||||
// this means this loop exits from 1812.5us to 1937.5us after the falling
|
||||
// edge, so at least 812.5us after a 1-bit rising edge, and at least
|
||||
// 1062.5us before a 0-bit rising edge.
|
||||
// This also leaves us with up to 2062.5us (33 cycles) to update cur_byte,
|
||||
// possibly moving on to the next byte, waiting for a high input, and
|
||||
// waiting for the next falling edge.
|
||||
// Time taken until waiting for input high for non-last byte:
|
||||
// - shift to current byte:
|
||||
// - 1: 4 cycles (lds, sbrc-false, or)
|
||||
// - 0: 4 cycles (lds, sbrc-true)
|
||||
// - byte done: 8 cycles (lsr, brne-false, st, dec, brne-false, ldi, clr)
|
||||
// - byte not done: 3 cycles (lsr, brne-true)
|
||||
// Total: 7 to 12 cycles, so there are at least 21 cycles left until the
|
||||
// next bit.
|
||||
"\tldi %[timeout], 8\n" // 1
|
||||
".read_wait_low_%=:\n"
|
||||
"\tdec %[timeout]\n" // 1
|
||||
"\tbrne .read_wait_low_%=\n" // timeout=0: 1, timeout!=0: 2
|
||||
".read_input_low_%=:\n"
|
||||
// Wait for 1500 us (24 cycles) before reading input.
|
||||
// As it takes from 5 to 7 cycles for the prevous loop to exit,
|
||||
// this means this loop exits from 1812.5us to 1937.5us after the falling
|
||||
// edge, so at least 812.5us after a 1-bit rising edge, and at least
|
||||
// 1062.5us before a 0-bit rising edge.
|
||||
// This also leaves us with up to 2062.5us (33 cycles) to update cur_byte,
|
||||
// possibly moving on to the next byte, waiting for a high input, and
|
||||
// waiting for the next falling edge.
|
||||
// Time taken until waiting for input high for non-last byte:
|
||||
// - shift to current byte:
|
||||
// - 1: 4 cycles (lds, sbrc-false, or)
|
||||
// - 0: 4 cycles (lds, sbrc-true)
|
||||
// - byte done: 8 cycles (lsr, brne-false, st, dec, brne-false, ldi, clr)
|
||||
// - byte not done: 3 cycles (lsr, brne-true)
|
||||
// Total: 7 to 12 cycles, so there are at least 21 cycles left until the
|
||||
// next bit.
|
||||
"\tldi %[timeout], 8\n" // 1
|
||||
".read_wait_low_%=:\n"
|
||||
"\tdec %[timeout]\n" // 1
|
||||
"\tbrne .read_wait_low_%=\n" // timeout=0: 1, timeout!=0: 2
|
||||
|
||||
// Sample input
|
||||
"\tlds %[scratch], %[in_byte]\n" // 2
|
||||
// Add to cur_byte
|
||||
"\tsbrc %[scratch], %[in_bit]\n" // high: 1, low: 2
|
||||
"\tor %[cur_byte], %[mask]\n" // 1
|
||||
// Shift mask
|
||||
"\tlsr %[mask]\n"
|
||||
"\tbrne .read_wait_input_high_init_%=\n" // mask==0: 1, mask!=0: 2
|
||||
// A wole byte was read, store in output
|
||||
"\tst Z+, %[cur_byte]\n" // 2
|
||||
// Decrement byte count
|
||||
"\tdec %[byte_count]\n" // 1
|
||||
// Are we done reading ?
|
||||
"\tbreq .read_end_%=\n" // byte_count!=0: 1, byte_count==0: 2
|
||||
// No, prepare for reading another
|
||||
"\tldi %[mask], 0x80\n"
|
||||
"\tclr %[cur_byte]\n"
|
||||
// Sample input
|
||||
"\tlds %[scratch], %[in_byte]\n" // 2
|
||||
// Add to cur_byte
|
||||
"\tsbrc %[scratch], %[in_bit]\n" // high: 1, low: 2
|
||||
"\tor %[cur_byte], %[mask]\n" // 1
|
||||
// Shift mask
|
||||
"\tlsr %[mask]\n"
|
||||
"\tbrne .read_wait_input_high_init_%=\n" // mask==0: 1, mask!=0: 2
|
||||
// A wole byte was read, store in output
|
||||
"\tst Z+, %[cur_byte]\n" // 2
|
||||
// Decrement byte count
|
||||
"\tdec %[byte_count]\n" // 1
|
||||
// Are we done reading ?
|
||||
"\tbreq .read_end_%=\n" // byte_count!=0: 1, byte_count==0: 2
|
||||
// No, prepare for reading another
|
||||
"\tldi %[mask], 0x80\n"
|
||||
"\tclr %[cur_byte]\n"
|
||||
|
||||
// Wait for rising edge
|
||||
".read_wait_input_high_init_%=:"
|
||||
"\tldi %[timeout], 0x3f\n" // 1
|
||||
".read_wait_input_high_%=:\n"
|
||||
"\tlds %[scratch], %[in_byte]\n" // 2
|
||||
"\tsbrc %[scratch], %[in_bit]\n" // high: 1, low: 2
|
||||
"\trjmp .read_loop_%=\n" // 2
|
||||
"\tdec %[timeout]\n" // 1
|
||||
"\tbrne .read_wait_input_high_%=\n" // timeout==0: 1, timeout!=0: 2
|
||||
"\trjmp .read_end_%=\n" // 2
|
||||
".read_end_%=:\n"
|
||||
: [output] "+z" (output),
|
||||
[byte_count] "+r" (byte_count),
|
||||
[mask] "=&a" (mask),
|
||||
[cur_byte] "=&r" (cur_byte),
|
||||
[timeout] "=&a" (timeout),
|
||||
[scratch] "=&a" (scratch)
|
||||
: [in_byte] "i" (&PINH),
|
||||
[in_bit] "i" (4)
|
||||
: "cc", "memory"
|
||||
);
|
||||
// Wait for rising edge
|
||||
".read_wait_input_high_init_%=:"
|
||||
"\tldi %[timeout], 0x3f\n" // 1
|
||||
".read_wait_input_high_%=:\n"
|
||||
"\tlds %[scratch], %[in_byte]\n" // 2
|
||||
"\tsbrc %[scratch], %[in_bit]\n" // high: 1, low: 2
|
||||
"\trjmp .read_loop_%=\n" // 2
|
||||
"\tdec %[timeout]\n" // 1
|
||||
"\tbrne .read_wait_input_high_%=\n" // timeout==0: 1, timeout!=0: 2
|
||||
"\trjmp .read_end_%=\n" // 2
|
||||
".read_end_%=:\n"
|
||||
: [output] "+z"(output),
|
||||
[byte_count] "+r"(byte_count),
|
||||
[mask] "=&a"(mask),
|
||||
[cur_byte] "=&r"(cur_byte),
|
||||
[timeout] "=&a"(timeout),
|
||||
[scratch] "=&a"(scratch)
|
||||
: [in_byte] "i"(&PINH),
|
||||
[in_bit] "i"(4)
|
||||
: "cc", "memory");
|
||||
return byte_count;
|
||||
}
|
||||
|
||||
@ -1528,11 +1526,11 @@ void checkController() {
|
||||
}
|
||||
|
||||
// read 32bytes from controller pak and calculate CRC
|
||||
byte readBlock(byte *output, word myAddress) {
|
||||
byte readBlock(byte* output, word myAddress) {
|
||||
byte response_crc;
|
||||
// Calculate the address CRC
|
||||
word myAddressCRC = addrCRC(myAddress);
|
||||
const byte command[] = { 0x02, (byte) (myAddressCRC >> 8), (byte) (myAddressCRC & 0xff) };
|
||||
const byte command[] = { 0x02, (byte)(myAddressCRC >> 8), (byte)(myAddressCRC & 0xff) };
|
||||
word error;
|
||||
|
||||
// don't want interrupts getting in the way
|
||||
@ -1798,8 +1796,8 @@ void writeMPK() {
|
||||
myFile.read(command + 3, sizeof(command) - 3);
|
||||
|
||||
word address_with_crc = addrCRC(address);
|
||||
command[1] = (byte) (address_with_crc >> 8);
|
||||
command[2] = (byte) (address_with_crc & 0xff);
|
||||
command[1] = (byte)(address_with_crc >> 8);
|
||||
command[2] = (byte)(address_with_crc & 0xff);
|
||||
|
||||
// don't want interrupts getting in the way
|
||||
noInterrupts();
|
||||
@ -2191,7 +2189,7 @@ void writeEeprom() {
|
||||
// Blink led
|
||||
blinkLED();
|
||||
if (page)
|
||||
delay(50); // Wait 50ms between pages when writing
|
||||
delay(50); // Wait 50ms between pages when writing
|
||||
|
||||
noInterrupts();
|
||||
sendJoyBus(command, sizeof(command));
|
||||
@ -2211,7 +2209,7 @@ void writeEeprom() {
|
||||
}
|
||||
}
|
||||
|
||||
void readEepromPageList(byte *output, byte page_number, byte page_count) {
|
||||
void readEepromPageList(byte* output, byte page_number, byte page_count) {
|
||||
byte command[] = { 0x04, page_number };
|
||||
|
||||
// Disable interrupts for more uniform clock pulses
|
||||
@ -2226,7 +2224,7 @@ void readEepromPageList(byte *output, byte page_number, byte page_count) {
|
||||
interrupts();
|
||||
|
||||
if (page_count)
|
||||
delayMicroseconds(600); // wait 600us between pages when reading
|
||||
delayMicroseconds(600); // wait 600us between pages when reading
|
||||
|
||||
command[1]++;
|
||||
output += 8;
|
||||
|
@ -1068,7 +1068,7 @@ void CreateROMFolderInSD() {
|
||||
sd.chdir(folder);
|
||||
}
|
||||
|
||||
FsFile createNewFile(const char *prefix, const char *extension) {
|
||||
FsFile createNewFile(const char* prefix, const char* extension) {
|
||||
char filename[FILENAME_LENGTH];
|
||||
snprintf_P(filename, sizeof(filename), _file_name_no_number_fmt, prefix, extension);
|
||||
for (byte i = 0; i < 100; i++) {
|
||||
|
@ -893,7 +893,7 @@ void readROM_SFM() {
|
||||
|
||||
//clear the screen
|
||||
display_Clear();
|
||||
println_Msg(F("Creating folder: "));
|
||||
print_Msg(F("Creating folder "));
|
||||
println_Msg(folder);
|
||||
display_Update();
|
||||
|
||||
@ -927,7 +927,7 @@ void readROM_SFM() {
|
||||
println_Msg(F("Dumping HiRom..."));
|
||||
display_Update();
|
||||
|
||||
for (byte currBank = 192; currBank < (numBanks + 192); currBank++) {
|
||||
for (word currBank = 192; currBank < (numBanks + 192); currBank++) {
|
||||
for (long currByte = 0; currByte < 65536; currByte += 512) {
|
||||
for (int c = 0; c < 512; c++) {
|
||||
sdBuffer[c] = readBank_SFM(currBank, currByte + c);
|
||||
@ -1009,8 +1009,7 @@ void idFlash_SFM(int startBank) {
|
||||
void writeFlash_SFM(int startBank, uint32_t pos) {
|
||||
display_Clear();
|
||||
print_Msg(F("Writing Bank 0x"));
|
||||
print_Msg(startBank, HEX);
|
||||
print_Msg(F("..."));
|
||||
println_Msg(startBank, HEX);
|
||||
display_Update();
|
||||
|
||||
// Open file on sd card
|
||||
@ -1026,8 +1025,13 @@ void writeFlash_SFM(int startBank, uint32_t pos) {
|
||||
dataOut();
|
||||
|
||||
if (romType) {
|
||||
//Initialize progress bar
|
||||
uint32_t processedProgressBar = 0;
|
||||
uint32_t totalProgressBar = numBanks * 0x10000;
|
||||
draw_progressbar(0, totalProgressBar);
|
||||
|
||||
// Write hirom
|
||||
for (byte currBank = startBank; currBank < startBank + numBanks; currBank++) {
|
||||
for (word currBank = startBank; currBank < startBank + numBanks; currBank++) {
|
||||
// Fill SDBuffer with 1 page at a time then write it repeat until all bytes are written
|
||||
for (unsigned long currByte = 0; currByte < 0x10000; currByte += 128) {
|
||||
myFile.read(sdBuffer, 128);
|
||||
@ -1049,8 +1053,16 @@ void writeFlash_SFM(int startBank, uint32_t pos) {
|
||||
// Wait until write is finished
|
||||
busyCheck_SFM(startBank);
|
||||
}
|
||||
// update progress bar
|
||||
processedProgressBar += 0x10000;
|
||||
draw_progressbar(processedProgressBar, totalProgressBar);
|
||||
}
|
||||
} else {
|
||||
//Initialize progress bar
|
||||
uint32_t processedProgressBar = 0;
|
||||
uint32_t totalProgressBar = numBanks * 0x8000;
|
||||
draw_progressbar(0, totalProgressBar);
|
||||
|
||||
// Write lorom
|
||||
for (byte currBank = 0; currBank < numBanks; currBank++) {
|
||||
for (unsigned long currByte = 0x8000; currByte < 0x10000; currByte += 128) {
|
||||
@ -1072,6 +1084,9 @@ void writeFlash_SFM(int startBank, uint32_t pos) {
|
||||
// Wait until write is finished
|
||||
busyCheck_SFM(startBank);
|
||||
}
|
||||
// update progress bar
|
||||
processedProgressBar += 0x8000;
|
||||
draw_progressbar(processedProgressBar, totalProgressBar);
|
||||
}
|
||||
}
|
||||
// Close the file:
|
||||
@ -1155,7 +1170,7 @@ byte blankcheck_SFM(int startBank) {
|
||||
|
||||
byte blank = 1;
|
||||
if (romType) {
|
||||
for (byte currBank = startBank; currBank < startBank + numBanks; currBank++) {
|
||||
for (word currBank = startBank; currBank < startBank + numBanks; currBank++) {
|
||||
for (unsigned long currByte = 0; currByte < 0x10000; currByte++) {
|
||||
if (readBank_SFM(currBank, currByte) != 0xFF) {
|
||||
currBank = startBank + numBanks;
|
||||
@ -1192,7 +1207,7 @@ unsigned long verifyFlash_SFM(int startBank, uint32_t pos) {
|
||||
controlIn_SFM();
|
||||
|
||||
if (romType) {
|
||||
for (byte currBank = startBank; currBank < startBank + numBanks; currBank++) {
|
||||
for (word currBank = startBank; currBank < startBank + numBanks; currBank++) {
|
||||
for (unsigned long currByte = 0; currByte < 0x10000; currByte += 512) {
|
||||
// Fill SDBuffer
|
||||
myFile.read(sdBuffer, 512);
|
||||
@ -1244,7 +1259,7 @@ void readFlash_SFM() {
|
||||
print_FatalError(create_file_STR);
|
||||
}
|
||||
if (romType) {
|
||||
for (byte currBank = 0xC0; currBank < 0xC0 + numBanks; currBank++) {
|
||||
for (word currBank = 0xC0; currBank < 0xC0 + numBanks; currBank++) {
|
||||
for (unsigned long currByte = 0; currByte < 0x10000; currByte += 512) {
|
||||
for (int c = 0; c < 512; c++) {
|
||||
sdBuffer[c] = readBank_SFM(currBank, currByte + c);
|
||||
|
@ -602,7 +602,7 @@ void readLoRomBanks(unsigned int start, unsigned int total, FsFile* file) {
|
||||
uint32_t totalProgressBar = (uint32_t)(total - start) * 1024;
|
||||
draw_progressbar(0, totalProgressBar);
|
||||
|
||||
for (byte currBank = start; currBank < total; currBank++) {
|
||||
for (word currBank = start; currBank < total; currBank++) {
|
||||
PORTL = currBank;
|
||||
|
||||
// Blink led
|
||||
@ -653,7 +653,7 @@ void readHiRomBanks(unsigned int start, unsigned int total, FsFile* file) {
|
||||
uint32_t totalProgressBar = (uint32_t)(total - start) * 1024;
|
||||
draw_progressbar(0, totalProgressBar);
|
||||
|
||||
for (byte currBank = start; currBank < total; currBank++) {
|
||||
for (word currBank = start; currBank < total; currBank++) {
|
||||
PORTL = currBank;
|
||||
|
||||
// Blink led
|
||||
|
Loading…
Reference in New Issue
Block a user