mirror of
https://github.com/sanni/cartreader.git
synced 2024-09-21 07:39:44 +02:00
2cf7f5dbe7
The `setVoltage()` function should be called even when `ENABLE_VSELECT` is disabled because `ENABLE_3V3FIX` also uses it. There is no resource cost to do this as when both options are disabled the compiler will optimize this function out. This just "future proofs" the code so if that function ever does more it doesn't need updated everywhere. This applies to `setup_FlashVoltage()` as well. The changes to OSCR.cpp are just for code formatting and additional comments to clarify this.
744 lines
18 KiB
C++
744 lines
18 KiB
C++
//******************************************
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// BENESSE POCKET CHALLENGE W MODULE
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//******************************************
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#ifdef enable_PCW
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// Benesse Pocket Challenge W
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// Cartridge Pinout
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// 38P 1.27mm pitch connector
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//
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// CART CART
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// TOP EDGE
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// +---------+
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// | 1 |-- VCC
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// | 2 |-- GND
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// | 3 |-- AD0 (A0 IN/D0 OUT)
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// | 4 |-- AD1 (A1 IN/D1 OUT)
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// | 5 |-- AD2 (A2 IN/D2 OUT)
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// | 6 |-- AD3 (A3 IN/D3 OUT)
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// | 7 |-- AD4 (A4 IN/D4 OUT)
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// | 8 |-- AD5 (A5 IN/D5 OUT)
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// | 9 |-- AD6 (A6 IN/D6 OUT)
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// | 10 |-- AD7 (A7 IN/D7 OUT)
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// | 11 |-- A08
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// | 12 |-- A09
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// | 13 |-- A10
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// | 14 |-- A11
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// | 15 |-- A12
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// | 16 |-- A13
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// | 17 |-- A14
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// | 18 |-- A15
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// | 19 |-- A16
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// | 20 |-- A17
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// | 21 |-- A18
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// | 22 |-- A19
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// | 23 |-- A20
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// | 24 |-- A21
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// | 25 |-- NC [CPU-INT2/T15(P47)]
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// | 26 |-- 1B (7W00F) -> HIGH -+
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// | 27 |-- 1A (7W00F) -> HIGH -+-> OE (ROM) = LOW
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// | 28 |-- OE (LH5164A)
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// | 29 |-- WE (LH5164A)
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// | 30 |-- LE (HC573) [LATCH ENABLE FOR AD0-AD7]
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// | 31 |-- NC [CPU-TO5(P43)]
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// | 32 |-- NC [CPU-RESET]
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// | 33 |-- VCC
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// | 34 |-- GND
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// | 35 |-- NC
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// | 36 |-- NC [CPU-VCC]
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// | 37 |-- NC [CONSOLE-GND]
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// | 38 |-- NC
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// +---------+
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// CONTROL PINS:
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// LE - (PH0) - PCW PIN 30 - SNES RST
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// 1A - (PH3) - PCW PIN 27 - SNES /CS
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// 1B - (PH4) - PCW PIN 26 - SNES /IRQ
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// WE - (PH5) - PCW PIN 29 - SNES /WR
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// OE - (PH6) - PCW PIN 28 - SNES /RD
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// NOT CONNECTED:
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// CLK(PH1) - N/C
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// ADDRESS PINS:
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// ADDR/DATA [AD0-AD7] - PORTC
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// ADDR A8-A15 - PORTK
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// ADDR A16-A21 - PORTL
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//******************************************
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// DEFINES
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//******************************************
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// CONTROL PINS - LE/1A/1B/WE/OE
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#define LE_HIGH PORTH |= (1 << 0)
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#define LE_LOW PORTH &= ~(1 << 0)
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#define NAND_1A_HIGH PORTH |= (1 << 3)
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#define NAND_1A_LOW PORTH &= ~(1 << 3)
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#define NAND_1B_HIGH PORTH |= (1 << 4)
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#define NAND_1B_LOW PORTH &= ~(1 << 4) // Built-in RAM + I/O
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#define WE_HIGH PORTH |= (1 << 5)
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#define WE_LOW PORTH &= ~(1 << 5)
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#define OE_HIGH PORTH |= (1 << 6)
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#define OE_LOW PORTH &= ~(1 << 6)
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#define MODE_READ DDRC = 0 // [INPUT]
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#define MODE_WRITE DDRC = 0xFF //[OUTPUT]
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#define DATA_READ \
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{ \
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DDRC = 0; \
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PORTC = 0xFF; \
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} // [INPUT PULLUP]
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#define ADDR_WRITE DDRC = 0xFF // [OUTPUT]
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#define DETECTION_SIZE 64
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boolean multipack = 0; // Multi-Pack Cart
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byte bank0;
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byte bank1;
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//******************************************
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// SETUP
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//******************************************
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void setup_PCW() {
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// Request 5V
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setVoltage(VOLTS_SET_5V);
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// Set Address Pins to Output
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//A8-A15
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DDRK = 0xFF;
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//A16-A21
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DDRL = 0xFF;
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// Set Control Pins to Output
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// LE(PH0) --(PH1) 1A(PH3) 1B(PH4) WE(PH5) OE(PH6)
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DDRH |= (1 << 0) | (1 << 1) | (1 << 3) | (1 << 4) | (1 << 5) | (1 << 6);
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// Set TIME(PJ0) to Output (UNUSED)
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DDRJ |= (1 << 0);
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// Set Address/Data Pins AD0-AD7 (PC0-PC7) to Input
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MODE_READ; // DDRC = 0
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// Setting Control Pins to HIGH
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// LE(PH0) ---(PH1) 1A(PH3) 1B(PH4) WE(PH5) OE(PH6)
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PORTH |= (1 << 0) | (1 << 1) | (1 << 3) | (1 << 4) | (1 << 5) | (1 << 6);
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// Set Unused Pins HIGH
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PORTJ |= (1 << 0); // TIME(PJ0)
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// Multi-Pack Cart Check
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check_multi_PCW();
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strcpy(romName, "PCW");
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mode = mode_PCW;
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}
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//******************************************
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// MENU
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//******************************************
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static const char pcwmenuItem1[] PROGMEM = "Read ROM";
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static const char pcwmenuItem2[] PROGMEM = "Read SRAM";
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static const char pcwmenuItem3[] PROGMEM = "Write SRAM";
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static const char* const menuOptionsPCW[] PROGMEM = { pcwmenuItem1, pcwmenuItem2, pcwmenuItem3, string_reset2 };
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void pcwMenu() {
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convertPgm(menuOptionsPCW, 4);
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uint8_t mainMenu = question_box(F(" POCKET CHALLENGE W"), menuOptions, 4, 0);
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switch (mainMenu) {
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case 0:
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// Read ROM
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sd.chdir("/");
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if (multipack)
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readMultiROM_PCW();
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else
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readROM_PCW();
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sd.chdir("/");
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break;
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case 1:
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// Read SRAM
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sd.chdir("/");
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display_Clear();
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println_Msg(F("Reading SRAM..."));
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display_Update();
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readSRAM_PCW();
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sd.chdir("/");
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// Wait for user input
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// Prints string out of the common strings array either with or without newline
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print_STR(press_button_STR, 1);
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display_Update();
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wait();
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break;
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case 2:
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// Write SRAM
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sd.chdir("/");
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fileBrowser(F("Select SRM file"));
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display_Clear();
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writeSRAM_PCW();
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display_Clear();
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writeErrors = verifySRAM_PCW();
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if (writeErrors == 0) {
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println_Msg(F("SRAM verified OK"));
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display_Update();
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} else {
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print_STR(error_STR, 0);
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print_Msg(writeErrors);
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print_STR(_bytes_STR, 1);
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print_Error(did_not_verify_STR);
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}
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break;
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case 3:
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// Reset
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resetArduino();
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break;
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}
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}
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//******************************************
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// LOW LEVEL FUNCTIONS
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//******************************************
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// Max ROM Size 0x400000 (Highest Address = 0x3FFFFF) - 3F FFFF
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// NAND 1A + 1B HIGH = LOW = ROM Output Enabled
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void read_setup_PCW() {
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NAND_1A_HIGH;
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NAND_1B_HIGH;
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OE_HIGH;
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WE_HIGH;
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LE_LOW;
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}
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// READ ROM BYTE WITH ADDITIONAL DELAY
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// NEEDED FOR PROBLEM CARTS TO SWITCH FROM ADDRESS TO DATA
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unsigned char read_rom_byte_PCW(unsigned long address) {
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PORTL = (address >> 16) & 0xFF;
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PORTK = (address >> 8) & 0xFF;
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// Latch Address on AD0-AD7
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ADDR_WRITE;
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LE_HIGH; // Latch Enable
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PORTC = address & 0xFF; // A0-A7
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LE_LOW; // Address Latched
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__asm__("nop\n\t"
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"nop\n\t");
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// Read Data on AD0-AD7
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OE_LOW;
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DATA_READ;
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delayMicroseconds(5); // 3+ Microseconds for Problem Carts
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unsigned char data = PINC;
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OE_HIGH;
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return data;
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}
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// SRAM Size 0x8000 (Highest Address = 0x7FFF)
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// NAND 1A LOW = SRAM Enabled [ROM DISABLED]
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unsigned char read_ram_byte_1A_PCW(unsigned long address) {
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NAND_1A_LOW;
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PORTL = (address >> 16) & 0xFF;
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PORTK = (address >> 8) & 0xFF;
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// Latch Address on AD0-AD7
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ADDR_WRITE;
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LE_HIGH; // Latch Enable
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PORTC = address & 0xFF; // A0-A7
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LE_LOW; // Address Latched
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__asm__("nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t");
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// Read Data on AD0-AD7
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OE_LOW;
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DATA_READ;
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__asm__("nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t");
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unsigned char data = PINC;
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OE_HIGH;
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NAND_1A_HIGH;
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__asm__("nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t");
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return data;
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}
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// Toshiba TMP90C845A
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// 0xFEC0-0xFFBF Built-in RAM (256 bytes)
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// 0xFFC0-0xFFF7 Built-in I/O (56 bytes)
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// 0xFF00-0xFFBF (192 byte area available in direct addressing mode)
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// 0xFF18-0xFF68 (Micro DMA parameters (if used))
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// TEST CODE TO READ THE CPU BUILT-IN RAM + I/O
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// NAND 1B LOW = Built-In RAM + I/O Enabled [ROM DISABLED]
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unsigned char read_ram_byte_1B_PCW(unsigned long address) {
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NAND_1B_LOW;
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PORTL = (address >> 16) & 0xFF;
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PORTK = (address >> 8) & 0xFF;
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// Latch Address on AD0-AD7
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ADDR_WRITE;
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LE_HIGH; // Latch Enable
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PORTC = address & 0xFF; // A0-A7
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LE_LOW; // Address Latched
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__asm__("nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t");
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// Read Data on AD0-AD7
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OE_LOW;
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DATA_READ;
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__asm__("nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t");
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unsigned char data = PINC;
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OE_HIGH;
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NAND_1B_HIGH;
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__asm__("nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t");
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return data;
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}
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// WRITE SRAM 32K
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void write_ram_byte_1A_PCW(unsigned long address, unsigned char data) {
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NAND_1A_LOW;
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PORTL = (address >> 16) & 0xFF;
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PORTK = (address >> 8) & 0xFF;
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// Latch Address on AD0-AD7
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ADDR_WRITE;
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LE_HIGH; // Latch Enable
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PORTC = address & 0xFF; // A0-A7
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LE_LOW; // Address Latched
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// Write Data on AD0-AD7 - WE LOW ~240-248ns
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WE_LOW;
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PORTC = data;
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__asm__("nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t");
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WE_HIGH;
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NAND_1A_HIGH;
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}
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// WRITE CPU BUILT-IN RAM + I/O AREA
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// MODIFIED TO MATCH WORKING BANK SWITCH ROUTINE
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void write_ram_byte_1B_PCW(unsigned long address, unsigned char data) {
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NAND_1A_LOW;
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NAND_1A_HIGH;
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NAND_1B_LOW;
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PORTL = (address >> 16) & 0xFF;
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PORTK = (address >> 8) & 0xFF;
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// Latch Address on AD0-AD7
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ADDR_WRITE;
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LE_HIGH; // Latch Enable
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PORTC = address & 0xFF; // A0-A7
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LE_LOW; // Address Latched
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// Write Data on AD0-AD7 - WE LOW ~740ns
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WE_LOW;
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PORTC = data;
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__asm__("nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t");
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__asm__("nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t");
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WE_HIGH;
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NAND_1B_HIGH;
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}
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//==============================================================================
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// Overload Multi-Pack Bank Switch
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//
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// Known Multi-Pack Carts (Yellow Label Carts)
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// 0BD400 [PS] (2MB Version)
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// 0BD400 [PS] (4MB Version)
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// 0BF400 [PL]
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// 1BF400 [PZ]
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// 8BD400 [CR]
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// 8BF400 [LP]
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// 9BF400 [SLP] (Undumped)
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// Per Overload, identify multi-pack cart by reading 0x3FFA-0x3FFE
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// Multi-Pack carts are non-zero
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// 0x3FFA - Current Cartridge Bank
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// 0x3FFC - Value to Switch to Cartridge Bank 0
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// 0x3FFD - Value to Switch to Cartridge Bank 1
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// 0x3FFE - Last Value written to 0xFFFF
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// Bank Settings for 2MB
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// Write 0x28 to 0xFFFF to read 1st half of ROM
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// Write 0x2E to 0xFFFF to read 2nd half of ROM
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// Bank Settings for 4MB
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// Write 0x20 to 0xFFFF to read 1st half of ROM
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// Write 0x31 to 0xFFFF to read 2nd half of ROM
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// MULTI-PACK CART CHECK
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void check_multi_PCW() {
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read_setup_PCW();
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byte tempbyte = read_rom_byte_PCW(0x3FFC); // Bank 0 Switch
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if (tempbyte) {
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bank0 = tempbyte; // Store Bank 0 Switch
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tempbyte = read_rom_byte_PCW(0x3FFD); // Bank 1 Switch
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if (tempbyte) {
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bank1 = tempbyte; // Store Bank 1 Switch
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// Check for 00s
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tempbyte = read_rom_byte_PCW(0x3FFB); // Should be 00
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if (!tempbyte) {
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tempbyte = read_rom_byte_PCW(0x3FFF); // Should be 00
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if (!tempbyte)
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multipack = 1; // Flag Multi-Cart
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else {
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bank0 = 0;
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bank1 = 0;
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}
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}
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}
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}
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}
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void write_bank_byte_PCW(unsigned char data) {
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NAND_1A_LOW;
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NAND_1A_HIGH;
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NAND_1B_LOW;
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// Write to Address 0xFFFF
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PORTL = 0x00;
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PORTK = 0xFF; // A8-A15
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// Latch Address on AD0-AD7
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ADDR_WRITE;
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LE_HIGH; // Latch Enable
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PORTC = 0xFF; // A0-A7
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LE_LOW; // Address Latched
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// Write Data on AD0-AD7 - WE LOW ~728-736ns
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WE_LOW;
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PORTC = data;
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__asm__("nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t");
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__asm__("nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t");
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WE_HIGH;
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NAND_1B_HIGH;
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}
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void switchBank_PCW(int bank) {
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if (bank == 1) { // Upper Half
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write_bank_byte_PCW(bank1);
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} else { // Lower Half (default)
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write_bank_byte_PCW(bank0);
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}
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}
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//******************************************
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// READ ROM FUNCTIONS
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//******************************************
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void readROM_PCW() {
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// Setup read mode
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read_setup_PCW();
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// Detect rom size
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uint32_t rom_size = detect_rom_size_PCW();
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display_Clear();
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print_Msg(F("READING "));
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print_Msg(rom_size / 1024 / 1024);
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print_Msg("MB SINGLE-PACK");
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println_Msg(F(""));
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display_Update();
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// Create file
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strcpy(fileName, romName);
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strcat(fileName, ".pcw");
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EEPROM_readAnything(0, foldern);
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sprintf(folder, "PCW/ROM/%d", foldern);
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sd.mkdir(folder, true);
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sd.chdir(folder);
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print_STR(saving_to_STR, 0);
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print_Msg(folder);
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println_Msg(F("/..."));
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display_Update();
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foldern = foldern + 1;
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EEPROM_writeAnything(0, foldern);
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if (!myFile.open(fileName, O_RDWR | O_CREAT)) {
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print_FatalError(sd_error_STR);
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}
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// Init progress bar
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uint32_t progress = 0;
|
|
draw_progressbar(0, rom_size);
|
|
|
|
for (unsigned long address = 0; address < rom_size; address += 512) { // 4MB
|
|
for (unsigned int x = 0; x < 512; x++) {
|
|
sdBuffer[x] = read_rom_byte_PCW(address + x);
|
|
}
|
|
myFile.write(sdBuffer, 512);
|
|
progress += 512;
|
|
draw_progressbar(progress, rom_size);
|
|
}
|
|
myFile.flush();
|
|
myFile.close();
|
|
|
|
// Compare CRC32 to database and rename ROM if found
|
|
// Arguments: database name, precalculated crc string or 0 to calculate, rename rom or not, starting offset
|
|
compareCRC("pcw.txt", 0, 1, 0);
|
|
|
|
// Wait for user input
|
|
println_Msg(F(""));
|
|
// Prints string out of the common strings array either with or without newline
|
|
print_STR(press_button_STR, 1);
|
|
display_Update();
|
|
wait();
|
|
}
|
|
|
|
void readMultiROM_PCW() {
|
|
strcpy(fileName, romName);
|
|
strcat(fileName, ".pcw");
|
|
|
|
EEPROM_readAnything(0, foldern);
|
|
sprintf(folder, "PCW/ROM/%d", foldern);
|
|
sd.mkdir(folder, true);
|
|
sd.chdir(folder);
|
|
|
|
display_Clear();
|
|
print_STR(saving_to_STR, 0);
|
|
print_Msg(folder);
|
|
println_Msg(F("/..."));
|
|
display_Update();
|
|
|
|
foldern = foldern + 1;
|
|
EEPROM_writeAnything(0, foldern);
|
|
|
|
if (!myFile.open(fileName, O_RDWR | O_CREAT)) {
|
|
print_FatalError(sd_error_STR);
|
|
}
|
|
|
|
display_Clear();
|
|
println_Msg(F("READING MULTI-PACK"));
|
|
println_Msg(F(""));
|
|
display_Update();
|
|
|
|
// Init progress bar
|
|
uint32_t progress = 0;
|
|
draw_progressbar(0, 0x400000);
|
|
|
|
read_setup_PCW();
|
|
// Lower Half
|
|
switchBank_PCW(0);
|
|
for (unsigned long address = 0; address < 0x200000; address += 512) { // 2MB
|
|
for (unsigned int x = 0; x < 512; x++) {
|
|
sdBuffer[x] = read_rom_byte_PCW(address + x);
|
|
}
|
|
myFile.write(sdBuffer, 512);
|
|
progress += 512;
|
|
draw_progressbar(progress, 0x400000);
|
|
}
|
|
|
|
read_setup_PCW();
|
|
// Upper Half
|
|
switchBank_PCW(1);
|
|
for (unsigned long address = 0x200000; address < 0x400000; address += 512) { // 2MB
|
|
for (unsigned int x = 0; x < 512; x++) {
|
|
sdBuffer[x] = read_rom_byte_PCW(address + x);
|
|
}
|
|
myFile.write(sdBuffer, 512);
|
|
progress += 512;
|
|
draw_progressbar(progress, 0x400000);
|
|
}
|
|
|
|
myFile.flush();
|
|
myFile.close();
|
|
// Reset Bank
|
|
switchBank_PCW(0);
|
|
|
|
// Compare CRC32 to database and rename ROM if found
|
|
// Arguments: database name, precalculated crc string or 0 to calculate, rename rom or not, starting offset
|
|
compareCRC("pcw.txt", 0, 1, 0);
|
|
|
|
// Wait for user input
|
|
println_Msg(F(""));
|
|
// Prints string out of the common strings array either with or without newline
|
|
print_STR(press_button_STR, 1);
|
|
display_Update();
|
|
wait();
|
|
}
|
|
|
|
uint32_t detect_rom_size_PCW(void) {
|
|
uint32_t rom_size;
|
|
uint8_t read_byte;
|
|
uint8_t current_byte;
|
|
uint8_t detect_1m, detect_2m;
|
|
|
|
//Initialize variables
|
|
detect_1m = 0;
|
|
detect_2m = 0;
|
|
|
|
//Confirm where mirror address starts from (1MB, 2MB or 4MB)
|
|
for (current_byte = 0; current_byte < DETECTION_SIZE; current_byte++) {
|
|
if ((current_byte != detect_1m) && (current_byte != detect_2m)) {
|
|
//If none matched, size is 4MB
|
|
break;
|
|
}
|
|
|
|
read_byte = read_rom_byte_PCW(current_byte);
|
|
|
|
if (current_byte == detect_1m) {
|
|
if (read_rom_byte_PCW(0x100000 + current_byte) == read_byte) {
|
|
detect_1m++;
|
|
}
|
|
}
|
|
if (current_byte == detect_2m) {
|
|
if (read_rom_byte_PCW(0x200000 + current_byte) == read_byte) {
|
|
detect_2m++;
|
|
}
|
|
}
|
|
}
|
|
|
|
//ROM size detection
|
|
if (detect_1m == DETECTION_SIZE) {
|
|
rom_size = 0x100000;
|
|
} else if (detect_2m == DETECTION_SIZE) {
|
|
rom_size = 0x200000;
|
|
} else {
|
|
rom_size = 0x400000;
|
|
}
|
|
|
|
return rom_size;
|
|
}
|
|
|
|
//******************************************
|
|
// SRAM FUNCTIONS
|
|
//******************************************
|
|
|
|
void readSRAM_PCW() { // readSRAM_1A()
|
|
strcpy(fileName, romName);
|
|
strcat(fileName, ".srm");
|
|
|
|
EEPROM_readAnything(0, foldern);
|
|
sprintf(folder, "PCW/SAVE/%d", foldern);
|
|
sd.mkdir(folder, true);
|
|
sd.chdir(folder);
|
|
|
|
foldern = foldern + 1;
|
|
EEPROM_writeAnything(0, foldern);
|
|
|
|
if (!myFile.open(fileName, O_RDWR | O_CREAT)) {
|
|
print_FatalError(sd_error_STR);
|
|
}
|
|
display_Clear();
|
|
read_setup_PCW();
|
|
for (unsigned long address = 0x0; address < 0x8000; address += 512) { // 32K
|
|
for (unsigned int x = 0; x < 512; x++) {
|
|
sdBuffer[x] = read_ram_byte_1A_PCW(address + x);
|
|
}
|
|
myFile.write(sdBuffer, 512);
|
|
}
|
|
myFile.flush();
|
|
myFile.close();
|
|
print_Msg(F("Saved to "));
|
|
print_Msg(folder);
|
|
println_Msg(F("/"));
|
|
display_Update();
|
|
// calcCRC(fileName, 0x8000, NULL, 0); // 32K
|
|
}
|
|
|
|
// SRAM
|
|
void writeSRAM_PCW() {
|
|
sprintf(filePath, "%s/%s", filePath, fileName);
|
|
println_Msg(F("Writing..."));
|
|
println_Msg(filePath);
|
|
display_Update();
|
|
|
|
if (myFile.open(filePath, O_READ)) {
|
|
sd.chdir();
|
|
sprintf(filePath, "%s/%s", filePath, fileName);
|
|
display_Clear();
|
|
println_Msg(F("Writing File: "));
|
|
println_Msg(filePath);
|
|
println_Msg(fileName);
|
|
display_Update();
|
|
//open file on sd card
|
|
if (myFile.open(filePath, O_READ)) {
|
|
read_setup_PCW();
|
|
for (unsigned int address = 0x0; address < 0x8000; address += 512) { // 32K
|
|
myFile.read(sdBuffer, 512);
|
|
for (unsigned int x = 0; x < 512; x++) {
|
|
write_ram_byte_1A_PCW(address + x, sdBuffer[x]);
|
|
}
|
|
}
|
|
myFile.close();
|
|
print_STR(done_STR, 1);
|
|
display_Update();
|
|
} else {
|
|
print_FatalError(sd_error_STR);
|
|
}
|
|
} else {
|
|
print_FatalError(sd_error_STR);
|
|
}
|
|
display_Clear();
|
|
}
|
|
|
|
unsigned long verifySRAM_PCW() {
|
|
writeErrors = 0;
|
|
|
|
if (myFile.open(filePath, O_READ)) {
|
|
read_setup_PCW();
|
|
for (unsigned int address = 0x0; address < 0x8000; address += 512) { // 32K
|
|
for (unsigned int x = 0; x < 512; x++) {
|
|
byte myByte = read_ram_byte_1A_PCW(address + x);
|
|
sdBuffer[x] = myByte;
|
|
}
|
|
for (int i = 0; i < 512; i++) {
|
|
if (myFile.read() != sdBuffer[i]) {
|
|
writeErrors++;
|
|
}
|
|
}
|
|
}
|
|
myFile.close();
|
|
} else {
|
|
print_FatalError(sd_error_STR);
|
|
}
|
|
|
|
return writeErrors;
|
|
}
|
|
|
|
// avoid warnings
|
|
#undef MODE_READ
|
|
#undef MODE_WRITE
|
|
|
|
#endif
|
|
//******************************************
|
|
// End of File
|
|
//******************************************
|