diff --git a/builds/genesis_plus_gx_libretro.dll b/builds/genesis_plus_gx_libretro.dll
index 54e70bf..558d395 100644
Binary files a/builds/genesis_plus_gx_libretro.dll and b/builds/genesis_plus_gx_libretro.dll differ
diff --git a/builds/genplus_cube.dol b/builds/genplus_cube.dol
index 181e798..3debcf7 100644
Binary files a/builds/genplus_cube.dol and b/builds/genplus_cube.dol differ
diff --git a/builds/genplus_wii.dol b/builds/genplus_wii.dol
index 13753ac..4a530fd 100644
Binary files a/builds/genplus_wii.dol and b/builds/genplus_wii.dol differ
diff --git a/core/io_ctrl.c b/core/io_ctrl.c
index 9d1a768..97a8964 100644
--- a/core/io_ctrl.c
+++ b/core/io_ctrl.c
@@ -4,8 +4,8 @@
  *
  *  Support for Master System (315-5216, 315-5237 & 315-5297), Game Gear & Mega Drive I/O chips
  *
- *  Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003  Charles Mac Donald (original code)
- *  Copyright (C) 2007-2014  Eke-Eke (Genesis Plus GX)
+ *  Copyright (C) 1998-2003  Charles Mac Donald (original code)
+ *  Copyright (C) 2007-2016  Eke-Eke (Genesis Plus GX)
  *
  *  Redistribution and use of this code or any derivative works are permitted
  *  provided that the following conditions are met:
@@ -437,13 +437,6 @@ void io_z80_write(unsigned int offset, unsigned int data, unsigned int cycles)
     /* Send TR/TH state to connected peripherals */
     port[0].data_w((data << 1) & 0x60, (~data << 5) & 0x60);
     port[1].data_w((data >> 1) & 0x60, (~data << 3) & 0x60);
-
-    /* Japanese model specific */
-    if (region_code == REGION_JAPAN_NTSC)
-    {
-      /* Reading TH & TR pins always return 0 when set as output */
-      data &= 0x0F;
-    }
     
     /* Check for TH low-to-high transitions on both ports */
     if ((!(io_reg[0x0F] & 0x80) && (data & 0x80)) ||
@@ -453,6 +446,13 @@ void io_z80_write(unsigned int offset, unsigned int data, unsigned int cycles)
       hvc_latch = hctab[cycles % MCYCLES_PER_LINE] | 0x10000;
     }
 
+    /* Japanese model specific */
+    if (region_code == REGION_JAPAN_NTSC)
+    {
+      /* Reading TH & TR pins always return 0 when set as output */
+      data &= 0x0F;
+    }
+
     /* Update I/O Control register */
     io_reg[0x0F] = data;
   }
diff --git a/core/io_ctrl.h b/core/io_ctrl.h
index ca3d6be..8cf7d34 100644
--- a/core/io_ctrl.h
+++ b/core/io_ctrl.h
@@ -4,8 +4,8 @@
  *
  *  Support for Master System (315-5216, 315-5237 & 315-5297), Game Gear & Mega Drive I/O chips
  *
- *  Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003  Charles Mac Donald (original code)
- *  Copyright (C) 2007-2014  Eke-Eke (Genesis Plus GX)
+ *  Copyright (C) 1998-2003  Charles Mac Donald (original code)
+ *  Copyright (C) 2007-2016  Eke-Eke (Genesis Plus GX)
  *
  *  Redistribution and use of this code or any derivative works are permitted
  *  provided that the following conditions are met:
diff --git a/core/memz80.c b/core/memz80.c
index 7f08d50..0692ce3 100644
--- a/core/memz80.c
+++ b/core/memz80.c
@@ -4,8 +4,8 @@
  *
  *  Support for SG-1000, Mark-III, Master System, Game Gear & Mega Drive ports access
  *
- *  Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003  Charles Mac Donald (original code)
- *  Copyright (C) 2007-2015  Eke-Eke (Genesis Plus GX)
+ *  Copyright (C) 1998-2003  Charles Mac Donald (original code)
+ *  Copyright (C) 2007-2016  Eke-Eke (Genesis Plus GX)
  *
  *  Redistribution and use of this code or any derivative works are permitted
  *  provided that the following conditions are met:
@@ -468,18 +468,43 @@ void z80_ms_port_w(unsigned int port, unsigned char data)
 
     default:
     {
-      /* write FM chip if enabled */
-      if (!(port & 4) && (config.ym2413 & 1))
+      /* check if YM2413 chip is enabled */
+      if (config.ym2413 & 1)
       {
-        fm_write(Z80.cycles, port, data);
-
-        /* 315-5297 I/O chip decodes bit 1 to enable/disable PSG output */
         if (region_code == REGION_JAPAN_NTSC)
         {
-          io_reg[6] = (data & 2) ? 0xFF : 0x00;
-          SN76489_Config(Z80.cycles, config.psg_preamp, config.psgBoostNoise, io_reg[6]);
+          /* 315-5297 I/O chip decodes full address range */
+          port &= 0xFF;
+
+          /* internal YM2413 chip */
+          if ((port == 0xF0) || (port == 0xF1))
+          {
+            fm_write(Z80.cycles, port, data);
+            return;
+          }
+
+          /* Audio control register (315-5297 I/O chip specific) */
+          if (port == 0xF2)
+          {
+            /*  D1 D0
+                -----
+                0  0 : enable only PSG output (power-on default)
+                0  1 : enable only FM output
+                1  0 : disable both PSG & FM output
+                1  1 : enable both PSG and FM output
+            */
+            SN76489_Config(Z80.cycles, config.psg_preamp, config.psgBoostNoise, ((data + 1) & 0x02) ? 0x00 : 0xFF);
+            fm_write(Z80.cycles, 0x02, data);
+            io_reg[6] = data;
+            return;
+          }
+        }
+        else if (!(port & 4))
+        {
+          /* external FM board */
+          fm_write(Z80.cycles, port, data);
+          return;
         }
-        return;
       }
 
       z80_unused_port_w(port & 0xFF, data);
@@ -520,32 +545,54 @@ unsigned char z80_ms_port_r(unsigned int port)
 
     default:
     {
-      uint8 data = 0xFF;
-
-      /* read FM chip if enabled */
-      if (!(port & 4) && (config.ym2413 & 1))
+      if (region_code == REGION_JAPAN_NTSC)
       {
-        data = YM2413Read();
-
         /* 315-5297 I/O chip decodes full address range */
-        if (region_code == REGION_JAPAN_NTSC)
+        port &= 0xFF;
+
+        if (port == 0xF2)
         {
-          return data;
+          /* D7-D5 : C-SYNC counter (not emulated)
+             D4-D2 : Always zero
+             D1 : Mute control bit 1
+             D0 : Mute control bit 0
+          */
+          return io_reg[0x06] & 0x03;
         }
-      }
 
-      /* read I/O ports if enabled */
-      if (!(io_reg[0x0E] & 0x04))
+        if ((port == 0xC0) || (port == 0xC1) || (port == 0xDC) || (port == 0xDD))
+        {
+          /* read I/O ports if enabled */
+          if (!(io_reg[0x0E] & 0x04))
+          {
+            return io_z80_read(port & 1);
+          }
+        }
+
+        return z80_unused_port_r(port);
+      }
+      else
       {
-        data &= io_z80_read(port & 1);
-      }
+        uint8 data = 0xFF;
 
-      return data;
+        /* read FM board if enabled */
+        if (!(port & 4) && (config.ym2413 & 1))
+        {
+          data = YM2413Read();
+        }
+
+        /* read I/O ports if enabled */
+        if (!(io_reg[0x0E] & 0x04))
+        {
+          data &= io_z80_read(port & 1);
+        }
+
+        return data;
+      }
     }
   }
 }
 
-
 /*--------------------------------------------------------------------------*/
 /* Mark III port handlers                                                   */
 /*--------------------------------------------------------------------------*/
diff --git a/core/memz80.h b/core/memz80.h
index 3cf6f79..fab3f93 100644
--- a/core/memz80.h
+++ b/core/memz80.h
@@ -4,8 +4,8 @@
  *
  *  Support for SG-1000, Mark-III, Master System, Game Gear & Mega Drive ports access
  *
- *  Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003  Charles Mac Donald (original code)
- *  Copyright (C) 2007-2015  Eke-Eke (Genesis Plus GX)
+ *  Copyright (C) 1998-2003  Charles Mac Donald (original code)
+ *  Copyright (C) 2007-2016  Eke-Eke (Genesis Plus GX)
  *
  *  Redistribution and use of this code or any derivative works are permitted
  *  provided that the following conditions are met: