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https://github.com/ekeeke/Genesis-Plus-GX.git
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updated z80 core to last version (fixed X/Y flags in CCF/SCF/BIT instructions)
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ekeeke31
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@ -1,7 +1,7 @@
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/*****************************************************************************
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*
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* z80.c
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* Portable Z80 emulator V3.8
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* Portable Z80 emulator V3.9
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*
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* Copyright Juergen Buchmueller, all rights reserved.
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*
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@ -17,19 +17,42 @@
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* terms of its usage and license at any time, including retroactively
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* - This entire notice must remain in the source code.
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*
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* Changes in 3.8 [Miodrag Milanovic]
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* TODO:
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* - If LD A,I or LD A,R is interrupted, P/V flag gets reset, even if IFF2
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* was set before this instruction
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* - Ideally, the tiny differences between Z80 types should be supported,
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* currently known differences:
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* - LD A,I/R P/V flag reset glitch is fixed on CMOS Z80
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* - OUT (C),0 outputs 0 on NMOS Z80, $FF on CMOS Z80
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* - SCF/CCF X/Y flags is ((flags | A) & 0x28) on SGS/SHARP/ZiLOG NMOS Z80,
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* (flags & A & 0x28) on NEC NMOS Z80, other models unknown.
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* However, people from the Speccy scene mention that SCF/CCF X/Y results
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* are inconsistant and may be influenced by I and R registers.
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* This Z80 emulator assumes a ZiLOG NMOS model.
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*
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* Additional changes [Eke-Eke]:
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* - Discarded multi-chip support (unused)
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* - Fixed cycle counting for FD and DD prefixed instructions
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* - Fixed behavior of chained FD and DD prefixes (R register should be only incremented by one
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* - Implemented cycle-accurate INI/IND (needed by SMS emulation)
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* Changes in 3.9:
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* - Fixed cycle counts for LD IYL/IXL/IYH/IXH,n [Marshmellow]
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* - Fixed X/Y flags in CCF/SCF/BIT, ZEXALL is happy now [hap]
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* - Simplified DAA, renamed MEMPTR (3.8) to WZ, added TODO [hap]
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* - Fixed IM2 interrupt cycles [eke]
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* Changes in 3.8 [Miodrag Milanovic]:
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* - Added MEMPTR register (according to informations provided
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* by Vladimir Kladov
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* - BIT n,(HL) now return valid values due to use of MEMPTR
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* - Fixed BIT 6,(XY+o) undocumented instructions
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* Changes in 3.7 [Aaron Giles]
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* Changes in 3.7 [Aaron Giles]:
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* - Changed NMI handling. NMIs are now latched in set_irq_state
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* but are not taken there. Instead they are taken at the start of the
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* execute loop.
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* - Changed IRQ handling. IRQ state is set in set_irq_state but not taken
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* except during the inner execute loop.
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* - Removed x86 assembly hacks and obsolete timing loop catchers.
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* Changes in 3.6
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* Changes in 3.6:
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* - Got rid of the code that would inexactly emulate a Z80, i.e. removed
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* all the #if Z80_EXACT #else branches.
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* - Removed leading underscores from local register name shortcuts as
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@ -37,23 +60,23 @@
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* - Renamed the registers inside the Z80 context to lower case to avoid
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* ambiguities (shortcuts would have had the same names as the fields
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* of the structure).
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* Changes in 3.5
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* Changes in 3.5:
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* - Implemented OTIR, INIR, etc. without look-up table for PF flag.
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* [Ramsoft, Sean Young]
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* Changes in 3.4
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* Changes in 3.4:
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* - Removed Z80-MSX specific code as it's not needed any more.
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* - Implemented DAA without look-up table [Ramsoft, Sean Young]
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* Changes in 3.3
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* Changes in 3.3:
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* - Fixed undocumented flags XF & YF in the non-asm versions of CP,
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* and all the 16 bit arithmetic instructions. [Sean Young]
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* Changes in 3.2
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* Changes in 3.2:
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* - Fixed undocumented flags XF & YF of RRCA, and CF and HF of
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* INI/IND/OUTI/OUTD/INIR/INDR/OTIR/OTDR [Sean Young]
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* Changes in 3.1
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* Changes in 3.1:
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* - removed the REPEAT_AT_ONCE execution of LDIR/CPIR etc. opcodes
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* for readabilities sake and because the implementation was buggy
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* (and I was not able to find the difference)
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* Changes in 3.0
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* Changes in 3.0:
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* - 'finished' switch to dynamically overrideable cycle count tables
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* Changes in 2.9:
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* - added methods to access and override the cycle count tables
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@ -928,26 +951,18 @@ INLINE UINT8 DEC(UINT8 value)
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* DAA
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***************************************************************/
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#define DAA { \
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UINT8 cf, nf, hf, lo, hi, diff; \
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cf = F & CF; \
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nf = F & NF; \
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hf = F & HF; \
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lo = A & 15; \
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hi = A / 16; \
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UINT8 a = A; \
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if (F & NF) { \
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if ((F&HF) | ((A&0xf)>9)) a-=6; \
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if ((F&CF) | (A>0x99)) a-=0x60; \
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} \
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else { \
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if ((F&HF) | ((A&0xf)>9)) a+=6; \
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if ((F&CF) | (A>0x99)) a+=0x60; \
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} \
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\
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if (cf) \
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diff = (lo <= 9 && !hf) ? 0x60 : 0x66; \
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else if (lo >= 10) \
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diff = hi <= 8 ? 0x06 : 0x66; \
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else if (hi >= 10) \
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diff = hf ? 0x66 : 0x60; \
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else \
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diff = hf ? 0x06 : 0x00; \
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if (nf) A -= diff; \
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else A += diff; \
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F = SZP[A] | (F & NF); \
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if (cf || (lo <= 9 ? hi >= 10 : hi >= 9)) F |= CF; \
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if (nf ? hf && lo <= 5 : lo >= 10) F |= HF; \
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F = (F&(CF|NF)) | (A>0x99) | ((A^a)&HF) | SZP[a]; \
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A = a; \
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}
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/***************************************************************
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@ -1165,7 +1180,7 @@ INLINE UINT8 SRL(UINT8 value)
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***************************************************************/
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#undef BIT
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#define BIT(bit,reg) \
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F = (F & CF) | HF | SZ_BIT[reg & (1<<bit)]
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F = (F & CF) | HF | (SZ_BIT[reg & (1<<bit)] & ~(YF|XF)) | (reg & (YF|XF)); \
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/***************************************************************
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* BIT bit,(HL)
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@ -1375,6 +1390,7 @@ INLINE UINT8 SET(UINT8 bit, UINT8 value)
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if( BC ) \
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{ \
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PC -= 2; \
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MEMPTR = PC + 1; \
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CC(ex,0xb8); \
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}
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@ -2957,7 +2973,7 @@ OP(op,33) { SP++;
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OP(op,34) { WM( HL, INC(RM(HL)) ); } /* INC (HL) */
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OP(op,35) { WM( HL, DEC(RM(HL)) ); } /* DEC (HL) */
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OP(op,36) { WM( HL, ARG() ); } /* LD (HL),n */
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OP(op,37) { F = (F & (SF|ZF|PF)) | CF | (A & (YF|XF)); } /* SCF */
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OP(op,37) { F = (F & (SF|ZF|YF|XF|PF)) | CF | (A & (YF|XF)); } /* SCF */
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OP(op,38) { JR_COND( F & CF, 0x38 ); } /* JR C,o */
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OP(op,39) { ADD16(hl, sp); } /* ADD HL,SP */
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@ -2966,7 +2982,7 @@ OP(op,3b) { SP--;
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OP(op,3c) { A = INC(A); } /* INC A */
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OP(op,3d) { A = DEC(A); } /* DEC A */
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OP(op,3e) { A = ARG(); } /* LD A,n */
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OP(op,3f) { F = ((F&(SF|ZF|PF|CF))|((F&CF)<<4)|(A&(YF|XF)))^CF; } /* CCF */
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OP(op,3f) { F = ((F&(SF|ZF|YF|XF|PF|CF))|((F&CF)<<4)|(A&(YF|XF)))^CF; } /* CCF */
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OP(op,40) { } /* LD B,B */
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OP(op,41) { B = C; } /* LD B,C */
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