diff --git a/HISTORY.txt b/HISTORY.txt
index 14fb6c4..b16e527 100644
--- a/HISTORY.txt
+++ b/HISTORY.txt
@@ -30,6 +30,7 @@ Genesis Plus GX 1.7.5 (xx/xx/xxxx) (Eke-Eke)
 * improved CDD status report accuracy (fixes track looping with Mode 1 patched games using MSU-MD driver)
 * improved Word-RAM byte access accuracy (verified on schematics)
 * improved GFX processing accuracy to halt it while Word RAM is allocated to Main CPU in 2M mode
+* improved GFX timing accuracy (fixes "Night Striker" crashing after completing a game)
 * disabled 68k and Z80 access to PRG-RAM when SUB-CPU is running (fixes "Dungeon Explorer")
 * disabled CD hardware reset on Soft-Reset (verified on real hardware)
 * fixed potential load issues with non-zero backup RAM cart
diff --git a/builds/genesis_plus_gx_libretro.dll b/builds/genesis_plus_gx_libretro.dll
index 7b36337..c04648d 100644
Binary files a/builds/genesis_plus_gx_libretro.dll and b/builds/genesis_plus_gx_libretro.dll differ
diff --git a/builds/genplus_cube.dol b/builds/genplus_cube.dol
index 464fe29..5a9a2de 100644
Binary files a/builds/genplus_cube.dol and b/builds/genplus_cube.dol differ
diff --git a/builds/genplus_wii.dol b/builds/genplus_wii.dol
index 2eb7e93..d479847 100644
Binary files a/builds/genplus_wii.dol and b/builds/genplus_wii.dol differ
diff --git a/core/cd_hw/gfx.c b/core/cd_hw/gfx.c
index 16023e2..ebb060e 100644
--- a/core/cd_hw/gfx.c
+++ b/core/cd_hw/gfx.c
@@ -638,8 +638,17 @@ void gfx_start(unsigned int base, int cycles)
   /* reset GFX chip cycle counter */
   gfx.cycles = cycles;
 
-  /* update GFX chip timings (see AC3:Thunderhawk / Thunderstrike) */
-  gfx.cyclesPerLine = 4 * 5 * scd.regs[0x62>>1].w; 
+  /* update GFX chip timings (see AC3:Thunderhawk / Thunderstrike, Night Striker) */
+  /* number of Word-RAM accesses per image buffer rendered line:                  */
+  /*  . 4 initial read accesses (Xposition, Yposition, Xoffset and Yoffset)       */
+  /*  . 2 read accesses per rendered pixels (stamp map + stamp pixel data)        */
+  /*  . 1 read-modify-write access per group of 4 rendered pixels                 */
+  /* each access (read or read-modify-write) takes 3 SUB-CPU cycles by default    */
+  /* each access can be delayed by 1 to 3 CPU cycles in case of refresh or SUB-CPU access occuring on the same Word-RAM bank (not emulated) */
+  /* reference: https://github.com/MiSTer-devel/MegaCD_MiSTer/blob/master/docs/mcd%20logs/graphics_operations_and_68k_wordram_access.jpg */
+  /* TODO: figure what happen exactly when pixel offset is different from 0 */
+  /*       for the moment, one additional read-modify-write access is assumed at the start if pixel offset is not aligned to 4 pixels */
+  gfx.cyclesPerLine = 4 * 3 * (4 + 2 * scd.regs[0x62>>1].w + ((scd.regs[0x62>>1].w + (scd.regs[0x60>>1].byte.l & 0x03) + 3) >> 2));
 
   /* start graphics operation */
   scd.regs[0x58>>1].byte.h = 0x80;