From 6804b15f5dcde1a1bac61f863c40aa44a87cf75c Mon Sep 17 00:00:00 2001 From: EkeEke Date: Thu, 22 Nov 2012 22:10:18 +0100 Subject: [PATCH] [SCD] fixed typos --- source/cd_hw/scd.c | 2 +- source/cd_hw/scd.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/source/cd_hw/scd.c b/source/cd_hw/scd.c index bbbc8fa..591babf 100644 --- a/source/cd_hw/scd.c +++ b/source/cd_hw/scd.c @@ -1198,7 +1198,7 @@ void scd_reset(int hard) /* RESET register always return 1 (register $06 is unused by both sides, it is used for SUB-CPU first register) */ scd.regs[0x06>>1].byte.l = 0x01; - /* Reset TIMER & STOPWATCH counters */ + /* Reset Timer & Stopwatch counters */ scd.timer = 0; scd.stopwatch = 0; diff --git a/source/cd_hw/scd.h b/source/cd_hw/scd.h index 29d26d2..29d9233 100644 --- a/source/cd_hw/scd.h +++ b/source/cd_hw/scd.h @@ -67,7 +67,7 @@ typedef struct uint8 bram[0x2000]; /* 8K Backup RAM */ reg16_t regs[0x100]; /* 256 x 16-bit ASIC registers */ uint32 cycles; /* Master clock counter */ - int32 stopwatch; /* Clockwatch counter */ + int32 stopwatch; /* Stopwatch counter */ int32 timer; /* Timer counter */ uint8 pending; /* Pending interrupts */ uint8 dmna; /* Pending DMNA write status */