diff --git a/source/genesis.c b/source/genesis.c
index e8c06ba..cb83e59 100644
--- a/source/genesis.c
+++ b/source/genesis.c
@@ -265,7 +265,7 @@ void gen_zbusreq_w(unsigned int data, unsigned int cycles)
     {
       /* resynchronize with 68k */ 
       z80_run(cycles);
-      
+
       /* enable 68k access to Z80 bus */
       _m68k_memory_map *base = &m68k_memory_map[0xa0];
       base->read8   = z80_read_byte;
@@ -273,7 +273,7 @@ void gen_zbusreq_w(unsigned int data, unsigned int cycles)
       base->write8  = z80_write_byte;
       base->write16 = z80_write_word;
     }
-	
+
     /* update Z80 bus status */
     zstate |= 2;
   }
@@ -282,15 +282,15 @@ void gen_zbusreq_w(unsigned int data, unsigned int cycles)
     /* check if Z80 is going to be restarted */
     if (zstate == 3)
     {
-       /* resynchronize with 68k */
-       mcycles_z80 = cycles;
-	   
-       /* disable 68k access to Z80 bus */
-       _m68k_memory_map *base = &m68k_memory_map[0xa0];
-       base->read8   = m68k_read_bus_8;
-       base->read16  = m68k_read_bus_16;
-       base->write8  = m68k_unused_8_w;
-       base->write16 = m68k_unused_16_w;
+      /* resynchronize with 68k */
+      mcycles_z80 = cycles;
+
+      /* disable 68k access to Z80 bus */
+      _m68k_memory_map *base = &m68k_memory_map[0xa0];
+      base->read8   = m68k_read_bus_8;
+      base->read16  = m68k_read_bus_16;
+      base->write8  = m68k_unused_8_w;
+      base->write16 = m68k_unused_16_w;
     }   
 
     /* update Z80 bus status */
@@ -306,7 +306,7 @@ void gen_zreset_w(unsigned int data, unsigned int cycles)
     if (zstate == 0)
     {
       /* resynchronize with 68k */
-	    mcycles_z80 = cycles;
+      mcycles_z80 = cycles;
  
       /* reset Z80 & YM2612 */
       z80_reset();
@@ -314,7 +314,7 @@ void gen_zreset_w(unsigned int data, unsigned int cycles)
     }
 	
     /* check if 68k access to Z80 bus is granted */
-	  else if (zstate == 2)
+    else if (zstate == 2)
     {
       /* enable 68k access to Z80 bus */
       _m68k_memory_map *base = &m68k_memory_map[0xa0];
@@ -322,6 +322,10 @@ void gen_zreset_w(unsigned int data, unsigned int cycles)
       base->read16  = z80_read_word;
       base->write8  = z80_write_byte;
       base->write16 = z80_write_word;
+
+      /* reset Z80 & YM2612 */
+      z80_reset();
+      fm_reset(cycles);
     }
 
     /* update Z80 bus status */
@@ -334,8 +338,8 @@ void gen_zreset_w(unsigned int data, unsigned int cycles)
     {
       /* resynchronize with 68k */
       z80_run(cycles);
-	  }
-	
+    }
+
     /* check if 68k had access to Z80 bus */
     else if (zstate == 3)
     {
@@ -346,7 +350,7 @@ void gen_zreset_w(unsigned int data, unsigned int cycles)
       base->write8  = m68k_unused_8_w;
       base->write16 = m68k_unused_16_w;
     }
-	
+
     /* stop YM2612 */
     fm_reset(cycles);
 
diff --git a/source/vdp.c b/source/vdp.c
index 5488535..a371c2f 100644
--- a/source/vdp.c
+++ b/source/vdp.c
@@ -117,7 +117,7 @@ static uint32 fifo_latency;   /* CPU access latency */
  CRAM or VSRAM for a 68K > VDP transfer, in which case it is in words.
 
 */
-static const uint32 dma_rates[16] = {
+static const uint8 dma_rates[16] = {
   8,   83,  9, 102, /* 68K to VRAM (1 word = 2 bytes) */
   16, 167, 18, 205, /* 68K to CRAM or VSRAM */
   15, 166, 17, 204, /* DMA fill */
@@ -140,10 +140,7 @@ static void dma_fill(unsigned int data);
 void vdp_init(void)
 {
   /* PAL/NTSC timings */
-  if (vdp_pal)
-    lines_per_frame = 313;
-  else
-    lines_per_frame = 262;
+  lines_per_frame = vdp_pal ? 313: 262;
 }
 
 void vdp_reset(void)
@@ -268,25 +265,22 @@ void vdp_restore(uint8 *vdp_regs)
 
 void vdp_update_dma()
 {
-  uint32 dma_cycles = 0;
+  int dma_cycles = 0;
 
   /* update DMA timings  */
-  uint32 index = dma_type;
-  if ((status & 8) || !(reg[1] & 0x40))
-    ++index;
-  if (reg[12] & 1)
-    index+=2;
+  unsigned int index = dma_type;
+  if ((status & 8) || !(reg[1] & 0x40)) index++;
+  if (reg[12] & 1) index += 2;
 
   /* DMA transfer rate (bytes per line) */
-  uint32 rate = dma_rates[index];
+  unsigned int rate = dma_rates[index];
 
   /* 68k cycles left */
-  int32 left_cycles = (mcycles_vdp + MCYCLES_PER_LINE) - mcycles_68k;
-  if (left_cycles < 0)
-    left_cycles = 0;
+  int left_cycles = (mcycles_vdp + MCYCLES_PER_LINE) - mcycles_68k;
+  if (left_cycles < 0) left_cycles = 0;
 
   /* DMA bytes left */
-  uint32 dma_bytes = (left_cycles * rate) / MCYCLES_PER_LINE;
+  int dma_bytes = (left_cycles * rate) / MCYCLES_PER_LINE;
 
 #ifdef LOGVDP
   error("[%d(%d)][%d(%d)] DMA type %d (%d access/line)-> %d access (%d remaining) (%x)\n", v_counter, mcycles_68k/MCYCLES_PER_LINE, mcycles_68k, mcycles_68k%MCYCLES_PER_LINE,dma_type/4, rate, dma_length, dma_bytes, m68k_get_reg (NULL, M68K_REG_PC));
@@ -344,7 +338,11 @@ void vdp_ctrl_w(unsigned int data)
       /* VDP register write */
       reg_w((data >> 8) & 0x1F,data & 0xFF);
     }
-    else pending = 1;
+    else
+    {
+      /* Set pending flag */
+      pending = 1;
+    }
 
     addr = addr_latch | (data & 0x3FFF);
     code = ((code & 0x3C) | ((data >> 14) & 0x03));