From b1ccc1aaba2705cb4f6c90107f0101c1e4da2451 Mon Sep 17 00:00:00 2001
From: ekeeke <ekeeke31@gmail.com>
Date: Sat, 23 Mar 2019 14:01:43 +0100
Subject: [PATCH] [Core/CD] improved CD hardware reset timing accuracy on
 software reset

---
 core/cd_hw/cdd.c |  7 ++-----
 core/cd_hw/scd.c | 15 +++++++++------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/core/cd_hw/cdd.c b/core/cd_hw/cdd.c
index e3e3025..859179e 100644
--- a/core/cd_hw/cdd.c
+++ b/core/cd_hw/cdd.c
@@ -198,15 +198,12 @@ void cdd_init(int samplerate)
 
 void cdd_reset(void)
 {
-  /* reset cycle counter */
-  cdd.cycles = 0;
-  
   /* reset drive access latency */
   cdd.latency = 0;
-  
+
   /* reset track index */
   cdd.index = 0;
-  
+
   /* reset logical block address */
   cdd.lba = 0;
 
diff --git a/core/cd_hw/scd.c b/core/cd_hw/scd.c
index 42192c2..74d1795 100644
--- a/core/cd_hw/scd.c
+++ b/core/cd_hw/scd.c
@@ -793,7 +793,7 @@ static void scd_write_byte(unsigned int address, unsigned int data)
 
     case 0x01: /* RESET status */
     {
-      /* RESET bit cleared ? */      
+      /* RESET bit cleared ? */
       if (!(data & 0x01))
       {
         /* reset CD hardware */
@@ -1071,7 +1071,7 @@ static void scd_write_word(unsigned int address, unsigned int data)
       /* only update LED status (register $00 is reserved for MAIN-CPU, use $06 instead) */
       scd.regs[0x06>>1].byte.h = data >> 8;
 
-      /* RESET bit cleared ? */      
+      /* RESET bit cleared ? */
       if (!(data & 0x01))
       {
         /* reset CD hardware */
@@ -1626,6 +1626,9 @@ void scd_reset(int hard)
     s68k.cycles = 0;
     s68k_pulse_reset();
     s68k_pulse_halt();
+
+    /* Reset frame cycle counter */
+    scd.cycles = 0;
   }
   else
   {
@@ -1649,10 +1652,7 @@ void scd_reset(int hard)
 
   /* Reset Timer & Stopwatch counters */
   scd.timer = 0;
-  scd.stopwatch = 0;
-
-  /* Reset frame cycle counter */
-  scd.cycles = 0;
+  scd.stopwatch = s68k.cycles;
 
   /* Clear pending interrupts */
   scd.pending = 0;
@@ -1661,6 +1661,9 @@ void scd_reset(int hard)
   memset(&m68k.poll, 0, sizeof(m68k.poll));
   memset(&s68k.poll, 0, sizeof(s68k.poll));
 
+  /* reset CDD cycle counter */
+  cdd.cycles = (scd.cycles - s68k.cycles) * 3;
+
   /* Reset CD hardware */
   cdd_reset();
   cdc_reset();