From f7fc3382fc1d925fc59afb9e35a97cd45ed4c1ec Mon Sep 17 00:00:00 2001
From: EkeEke <ekeeke31@gmail.com>
Date: Mon, 21 Oct 2013 00:14:44 +0200
Subject: [PATCH] [Core/MCD] added CDC & GFX register polling detection /
 synchronization

---
 core/cd_hw/cdc.c | 15 ++++++++++++++-
 core/cd_hw/gfx.c | 13 +++++++++++++
 core/cd_hw/scd.c | 14 ++++++++++++++
 3 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/core/cd_hw/cdc.c b/core/cd_hw/cdc.c
index c8c75e6..3425931 100644
--- a/core/cd_hw/cdc.c
+++ b/core/cd_hw/cdc.c
@@ -214,9 +214,22 @@ void cdc_dma_update(void)
       }
     }
 
-    /* clear DSR bit & set EDT bit (SCD register $04) */
+    /* clear DSR bit & set EDT bit (CD register $04) */
     scd.regs[0x04>>1].byte.h = (scd.regs[0x04>>1].byte.h & 0x07) | 0x80;
 
+    /* SUB-CPU idle on register $04 polling ? */
+    if (s68k.stopped & (1<<0x04))
+    {
+      /* sync SUB-CPU with CDC */
+      s68k.cycles = scd.cycles;
+
+      /* restart SUB-CPU */
+      s68k.stopped = 0;
+#ifdef LOG_SCD
+      error("s68k started from %d cycles\n", s68k.cycles);
+#endif
+    }
+
     /* disable DMA transfer */
     cdc.dma_w = 0;
   }
diff --git a/core/cd_hw/gfx.c b/core/cd_hw/gfx.c
index d1f0341..4b40c88 100644
--- a/core/cd_hw/gfx.c
+++ b/core/cd_hw/gfx.c
@@ -692,6 +692,19 @@ void gfx_update(int cycles)
       /* end of graphics operation */
       scd.regs[0x58>>1].byte.h = 0;
  
+      /* SUB-CPU idle on register $58 polling ? */
+      if (s68k.stopped & (1<<0x08))
+      {
+        /* sync SUB-CPU with GFX chip */
+        s68k.cycles = scd.cycles;
+
+        /* restart SUB-CPU */
+        s68k.stopped = 0;
+#ifdef LOG_SCD
+        error("s68k started from %d cycles\n", s68k.cycles);
+#endif
+      }
+
       /* level 1 interrupt enabled ? */
       if (scd.regs[0x32>>1].byte.l & 0x02)
       {
diff --git a/core/cd_hw/scd.c b/core/cd_hw/scd.c
index c36c0d4..e750374 100644
--- a/core/cd_hw/scd.c
+++ b/core/cd_hw/scd.c
@@ -287,6 +287,20 @@ static unsigned int scd_read_byte(unsigned int address)
     return scd.regs[0x0e>>1].byte.h;
   }
 
+  /* CDC transfer status */
+  if (address == 0xff8004)
+  {
+    s68k_poll_detect(1<<0x04);
+    return scd.regs[0x04>>1].byte.h;
+  }
+
+  /* GFX operation status */
+  if (address == 0xff8058)
+  {
+    s68k_poll_detect(1<<0x08);
+    return scd.regs[0x58>>1].byte.h;
+  }
+
   /* CDC register data (controlled by BIOS, byte access only ?) */
   if (address == 0xff8007)
   {