220 lines
5.3 KiB
Plaintext
220 lines
5.3 KiB
Plaintext
# these are identified as part of the PowerPC Embedded Architecture
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#dcba 0,r0 0x7c 00 05 ec
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:dcba RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=758 & BIT_0=0 & RA_OR_ZERO
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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dataCacheBlockAllocate(ea);
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}
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#dcbf 0,r0 0x7c 00 00 ac
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:dcbf RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=86 & BIT_0=0 & RA_OR_ZERO
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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dataCacheBlockFlush(ea);
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}
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#dcbi 0,r0 0x7c 00 03 ac
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:dcbi RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=470 & BIT_0=0 & RA_OR_ZERO
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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dataCacheBlockInvalidate(ea);
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}
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#dcbst 0,r0 0x7c 00 00 6c
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:dcbst RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=54 & BIT_0=0 & RA_OR_ZERO
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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dataCacheBlockStore(ea);
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}
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#dcbt 0,r0 0x7c 00 02 2c
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:dcbt RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=278 & BIT_0=0 & RA_OR_ZERO
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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dataCacheBlockTouch(ea);
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}
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#dcbtst 0,r0 0x7c 00 01 ec
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:dcbtst RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=246 & BIT_0=0 & RA_OR_ZERO
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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dataCacheBlockTouchForStore(ea);
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}
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#dcbz 0,r0 0x7c 00 07 ec
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:dcbz RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=1014 & BIT_0=0 & RA_OR_ZERO
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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dataCacheBlockClearToZero(ea);
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}
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@ifndef IS_ISA
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# this is equilent to "mbar 0"
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#eieio 0x7c 00 06 ac
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:eieio is $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=854 & BIT_0=0
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{
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enforceInOrderExecutionIO();
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}
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@endif
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#icbi r0,r0 0x7c 00 07 ac
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:icbi RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=982 & BIT_0=0 & RA_OR_ZERO
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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instructionCacheBlockInvalidate(ea);
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}
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#icbt 0,r0 0x7c 00 02 0c
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:icbt BITS_21_24,RA_OR_ZERO,B is OP=31 & BIT_25=0 & BITS_21_24 & RA_OR_ZERO & B & XOP_1_10=22 & BIT_0=0
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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instructionCacheBlockTouch(ea);
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}
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#isync 0x4c 00 01 2c
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:isync is $(NOTVLE) & OP=19 & BITS_21_25=0 & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=150 & BIT_0=0
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{
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instructionSynchronize();
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}
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#mfdcr r0,DCRN 0x7c 00 02 86
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:mfdcr D, DCRN is OP=31 & D & DCRN & XOP_1_10=323 & BIT_0=0
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{
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D = DCRN;
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}
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#mfmsr r0 0x7c 00 00 a6
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:mfmsr D is OP=31 & D & BITS_11_20=0 & XOP_1_10=83 & BIT_0=0
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{
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D = MSR;
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}
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#mfspr r0 0x7c 00 02 a6
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:mfspr D,SPRVAL is OP=31 & D & SPRVAL & XOP_1_10=339 & BIT_0=0
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{
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D = SPRVAL;
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}
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#mftb r0,TBLr 0x7c 0c 42 e6
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:mftb D,TBLr is $(NOTVLE) & OP=31 & D & TBR=392 & TBLr & XOP_1_10=371 & BIT_0=0
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{
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D = TBLr;
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}
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#mftb r0,TBUr 0x7c 0d 42 e6
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:mftb D,TBUr is $(NOTVLE) & OP=31 & D & TBR=424 & TBUr & XOP_1_10=371 & BIT_0=0
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{
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D = TBUr;
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}
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#mtdcr DCRN,r0 0x7c 00 03 86
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:mtdcr DCRN, D is OP=31 & D & DCRN & XOP_1_10=451 & BIT_0=0
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{
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DCRN = D;
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}
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#mtmsr r0,0 0x7c 00 01 24
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:mtmsr S,0 is OP=31 & S & BITS_17_20=0 & MSR_L=0 & BITS_11_15=0 & XOP_1_10=146 & BIT_0=0
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{
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bit58:$(REGISTER_SIZE) = (S >> 5) & 1; #bit 58
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bit49:$(REGISTER_SIZE) = (S >> 14)& 1; #bit 49
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bit59:$(REGISTER_SIZE) = (S >> 4) & 1; #bit 59
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@ifdef BIT_64
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tmp:8 = S & 0x00000000ffff6fcf; #0b00000000000000000000000000000000 1111 1111 1111 1111 0110 1111 1100 1111
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tmp = tmp & ((bit58 | bit49) << 5);
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tmp = tmp & ((bit59 | bit49) << 4);
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MSR = MSR & 0xffffffff00009030 | tmp;
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@else
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tmp:4 = S & 0xffff6fcf;
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tmp = tmp & ((bit58 | bit49) << 5);
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tmp = tmp & ((bit59 | bit49) << 4);
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MSR = MSR & 0x00009000 | tmp;
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@endif
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}
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#mtmsr r0,1 0x7c 01 01 24
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:mtmsr S,1 is OP=31 & S & BITS_17_20=0 & MSR_L=1 & BITS_11_15=0 & XOP_1_10=146 & BIT_0=0
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{
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@ifdef BIT_64
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mask:8 = 0x000000000000fffe;
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@else
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mask:4 = 0x0000fffe;
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@endif
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MSR = (MSR & ~mask) | (S & mask);
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}
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#mtspr spr000,r0 0x7c 00 02 a6
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:mtspr SPRVAL,S is OP=31 & SPRVAL & S & XOP_1_10=467 & BIT_0=0
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{
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SPRVAL = S;
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}
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:mtspr SPRVAL,S is OP=31 & BITS_11_20=0x100 & BITS_21_25=0 & SPRVAL & S & XOP_1_10=467 & BIT_0=0
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[ linkreg=1; globalset(inst_next,linkreg); ]
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{
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SPRVAL = S;
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}
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:mtspr SPRVAL,S is linkreg=1 & OP=31 & BITS_11_20=0x100 & BITS_21_25=0 & SPRVAL & S & XOP_1_10=467 & BIT_0=0
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[ linkreg=0; globalset(inst_start,linkreg); ]
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{
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SPRVAL = S;
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}
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:rfci is $(NOTVLE) & OP=19 & BITS_21_25=0 & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=51 & BIT_0=0
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{
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MSR = returnFromCriticalInterrupt(MSR, CSRR1);
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local ra = CSRR0;
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return[ra];
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}
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#rfi 0x4c 00 00 64
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:rfi is $(NOTVLE) & OP=19 & BITS_11_25=0 & XOP_1_10=50 & BIT_0=0
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{
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MSR = returnFromInterrupt(MSR, SRR1);
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local ra = SRR0;
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return[ra];
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}
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#tlbre 0x7c 00 07 64
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:tlbre is OP=31 & XOP_1_10=946
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{
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TLBRead();
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}
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#tlbsx r0,r0,r0 0x7c 00 07 24
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:tlbsx D,RA_OR_ZERO,B is OP=31 & D & B & XOP_1_10=914 & RA_OR_ZERO & Rc=0
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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D = TLBSearchIndexed(D,ea);
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}
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#tlbsx. r0,r0,r0 0x7c 00 07 25
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:tlbsx. D,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & D & B & XOP_1_10=914 & RA_OR_ZERO & Rc=1
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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D = TLBSearchIndexed(D,ea);
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cr0flags(D);
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}
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#tlbwe 0x7c 00 07 a4
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:tlbwe D,A,B_BITS is OP=31 & D & A & B_BITS & XOP_1_10=978
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{
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D = TLBWrite(D,A,B_BITS:1);
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}
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#wrtee r0 0x7c 00 01 06
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:wrtee S is OP=31 & S & XOP_1_10=131
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{
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WriteExternalEnable(S);
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}
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#wrteei 0 0x7c 00 01 46
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:wrteei BIT_15 is OP=31 & BIT_15 & XOP_1_10=163
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{
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WriteExternalEnableImmediate(BIT_15:1);
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}
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