mirror of
https://github.com/Wiimpathy/HatariWii.git
synced 2024-06-03 00:58:44 +02:00
597 lines
18 KiB
C
597 lines
18 KiB
C
/*
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* UAE - The Un*x Amiga Emulator
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*
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* memory management
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*
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* Copyright 1995 Bernd Schmidt
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*/
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#ifndef MEMORY_H
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#define MEMORY_H
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extern void memory_reset (void);
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#ifdef JIT
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extern int special_mem;
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extern uae_u8 *cache_alloc (int);
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extern void cache_free (uae_u8*);
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#endif
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#define S_READ 1
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#define S_WRITE 2
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bool init_shm (void);
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void free_shm (void);
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bool preinit_shm (void);
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extern bool canbang;
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extern bool jit_direct_compatible_memory;
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#define Z3BASE_UAE 0x10000000
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#define Z3BASE_REAL 0x40000000
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#ifdef ADDRESS_SPACE_24BIT
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#define MEMORY_BANKS 256
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#define MEMORY_RANGE_MASK ((1<<24)-1)
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#else
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#define MEMORY_BANKS 65536
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#define MEMORY_RANGE_MASK (~0)
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#endif
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typedef uae_u32 (REGPARAM3 *mem_get_func)(uaecptr) REGPARAM;
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typedef void (REGPARAM3 *mem_put_func)(uaecptr, uae_u32) REGPARAM;
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typedef uae_u8 *(REGPARAM3 *xlate_func)(uaecptr) REGPARAM;
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typedef int (REGPARAM3 *check_func)(uaecptr, uae_u32) REGPARAM;
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extern uae_u8 *address_space, *good_address_map;
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extern uae_u32 max_z3fastmem;
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extern uae_u32 wait_cpu_cycle_read (uaecptr addr, int mode);
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extern void wait_cpu_cycle_write (uaecptr addr, int mode, uae_u32 v);
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extern uae_u32 wait_cpu_cycle_read_ce020 (uaecptr addr, int mode);
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extern void wait_cpu_cycle_write_ce020 (uaecptr addr, int mode, uae_u32 v);
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#undef DIRECT_MEMFUNCS_SUCCESSFUL
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#include "maccess.h"
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#define chipmem_start_addr 0x00000000
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#define bogomem_start_addr 0x00C00000
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#define ROM_SIZE_512 524288
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#define ROM_SIZE_256 262144
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#define ROM_SIZE_128 131072
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extern bool ersatzkickfile;
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extern bool cloanto_rom, kickstart_rom;
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extern uae_u16 kickstart_version;
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extern int uae_boot_rom_type;
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extern int uae_boot_rom_size;
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extern uaecptr rtarea_base;
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extern uae_u8* baseaddr[];
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enum
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{
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ABFLAG_UNK = 0, ABFLAG_RAM = 1, ABFLAG_ROM = 2, ABFLAG_ROMIN = 4, ABFLAG_IO = 8,
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ABFLAG_NONE = 16, ABFLAG_SAFE = 32, ABFLAG_INDIRECT = 64, ABFLAG_NOALLOC = 128,
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ABFLAG_RTG = 256, ABFLAG_THREADSAFE = 512, ABFLAG_DIRECTMAP = 1024
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};
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typedef struct {
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/* These ones should be self-explanatory... */
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mem_get_func lget, wget, bget;
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mem_put_func lput, wput, bput;
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/* Use xlateaddr to translate an Amiga address to a uae_u8 * that can
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* be used to address memory without calling the wget/wput functions.
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* This doesn't work for all memory banks, so this function may call
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* abort(). */
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xlate_func xlateaddr;
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/* To prevent calls to abort(), use check before calling xlateaddr.
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* It checks not only that the memory bank can do xlateaddr, but also
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* that the pointer points to an area of at least the specified size.
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* This is used for example to translate bitplane pointers in custom.c */
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check_func check;
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/* For those banks that refer to real memory, we can save the whole trouble
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of going through function calls, and instead simply grab the memory
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ourselves. This holds the memory address where the start of memory is
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for this particular bank. */
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uae_u8 *baseaddr;
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const TCHAR *label;
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const TCHAR *name;
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/* for instruction opcode/operand fetches */
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mem_get_func lgeti, wgeti;
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int flags;
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struct addrbank_sub *sub_banks;
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uae_u32 mask;
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uae_u32 startmask;
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uae_u32 start;
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uae_u32 allocated;
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} addrbank;
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#define MEMORY_MIN_SUBBANK 1024
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struct addrbank_sub
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{
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addrbank *bank;
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uae_u32 offset;
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uae_u32 suboffset;
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uae_u32 mask;
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uae_u32 maskval;
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};
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#define CE_MEMBANK_FAST32 0
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#define CE_MEMBANK_CHIP16 1
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#define CE_MEMBANK_CHIP32 2
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#define CE_MEMBANK_CIA 3
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#define CE_MEMBANK_FAST16 4
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#ifdef WINUAE_FOR_HATARI
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#define CE_MEMBANK_NOT_CACHABLE 0
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#define CE_MEMBANK_CACHABLE (1)
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#define CE_MEMBANK_CACHABLE_BURST (1|2)
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#endif
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extern uae_u8 ce_banktype[65536], ce_cachable[65536];
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#ifdef JIT
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#define MEMORY_LGET(name, nojit) \
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static uae_u32 REGPARAM3 name ## _lget (uaecptr) REGPARAM; \
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static uae_u32 REGPARAM2 name ## _lget (uaecptr addr) \
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{ \
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uae_u8 *m; \
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if (nojit) special_mem |= S_READ; \
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addr -= name ## _bank.start & name ## _bank.mask; \
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addr &= name ## _bank.mask; \
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m = name ## _bank.baseaddr + addr; \
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return do_get_mem_long ((uae_u32 *)m); \
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}
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#define MEMORY_WGET(name, nojit) \
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static uae_u32 REGPARAM3 name ## _wget (uaecptr) REGPARAM; \
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static uae_u32 REGPARAM2 name ## _wget (uaecptr addr) \
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{ \
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uae_u8 *m; \
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if (nojit) special_mem |= S_READ; \
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addr -= name ## _bank.start & name ## _bank.mask; \
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addr &= name ## _bank.mask; \
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m = name ## _bank.baseaddr + addr; \
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return do_get_mem_word ((uae_u16 *)m); \
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}
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#define MEMORY_BGET(name, nojit) \
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static uae_u32 REGPARAM3 name ## _bget (uaecptr) REGPARAM; \
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static uae_u32 REGPARAM2 name ## _bget (uaecptr addr) \
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{ \
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if (nojit) special_mem |= S_READ; \
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addr -= name ## _bank.start & name ## _bank.mask; \
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addr &= name ## _bank.mask; \
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return name ## _bank.baseaddr[addr]; \
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}
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#define MEMORY_LPUT(name, nojit) \
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static void REGPARAM3 name ## _lput (uaecptr, uae_u32) REGPARAM; \
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static void REGPARAM2 name ## _lput (uaecptr addr, uae_u32 l) \
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{ \
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uae_u8 *m; \
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if (nojit) special_mem |= S_WRITE; \
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addr -= name ## _bank.start & name ## _bank.mask; \
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addr &= name ## _bank.mask; \
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m = name ## _bank.baseaddr + addr; \
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do_put_mem_long ((uae_u32 *)m, l); \
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}
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#define MEMORY_WPUT(name, nojit) \
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static void REGPARAM3 name ## _wput (uaecptr, uae_u32) REGPARAM; \
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static void REGPARAM2 name ## _wput (uaecptr addr, uae_u32 w) \
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{ \
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uae_u8 *m; \
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if (nojit) special_mem |= S_WRITE; \
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addr -= name ## _bank.start & name ## _bank.mask; \
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addr &= name ## _bank.mask; \
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m = name ## _bank.baseaddr + addr; \
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do_put_mem_word ((uae_u16 *)m, w); \
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}
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#define MEMORY_BPUT(name, nojit) \
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static void REGPARAM3 name ## _bput (uaecptr, uae_u32) REGPARAM; \
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static void REGPARAM2 name ## _bput (uaecptr addr, uae_u32 b) \
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{ \
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if (nojit) special_mem |= S_WRITE; \
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addr -= name ## _bank.start & name ## _bank.mask; \
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addr &= name ## _bank.mask; \
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name ## _bank.baseaddr[addr] = b; \
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}
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#define MEMORY_CHECK(name) \
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static int REGPARAM3 name ## _check (uaecptr addr, uae_u32 size) REGPARAM; \
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static int REGPARAM2 name ## _check (uaecptr addr, uae_u32 size) \
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{ \
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addr -= name ## _bank.start & name ## _bank.mask; \
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addr &= name ## _bank.mask; \
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return (addr + size) <= name ## _bank.allocated; \
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}
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#define MEMORY_XLATE(name) \
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static uae_u8 *REGPARAM3 name ## _xlate (uaecptr addr) REGPARAM; \
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static uae_u8 *REGPARAM2 name ## _xlate (uaecptr addr) \
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{ \
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addr -= name ## _bank.start & name ## _bank.mask; \
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addr &= name ## _bank.mask; \
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return name ## _bank.baseaddr + addr; \
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}
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#else
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#define MEMORY_LGET(name, nojit) \
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static uae_u32 REGPARAM3 name ## _lget (uaecptr) REGPARAM; \
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static uae_u32 REGPARAM2 name ## _lget (uaecptr addr) \
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{ \
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uae_u8 *m; \
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addr -= name ## _bank.start & name ## _bank.mask; \
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addr &= name ## _bank.mask; \
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m = name ## _bank.baseaddr + addr; \
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return do_get_mem_long ((uae_u32 *)m); \
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}
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#define MEMORY_WGET(name, nojit) \
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static uae_u32 REGPARAM3 name ## _wget (uaecptr) REGPARAM; \
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static uae_u32 REGPARAM2 name ## _wget (uaecptr addr) \
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{ \
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uae_u8 *m; \
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addr -= name ## _bank.start & name ## _bank.mask; \
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addr &= name ## _bank.mask; \
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m = name ## _bank.baseaddr + addr; \
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return do_get_mem_word ((uae_u16 *)m); \
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}
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#define MEMORY_BGET(name, nojit) \
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static uae_u32 REGPARAM3 name ## _bget (uaecptr) REGPARAM; \
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static uae_u32 REGPARAM2 name ## _bget (uaecptr addr) \
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{ \
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addr -= name ## _bank.start & name ## _bank.mask; \
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addr &= name ## _bank.mask; \
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return name ## _bank.baseaddr[addr]; \
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}
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#define MEMORY_LPUT(name, nojit) \
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static void REGPARAM3 name ## _lput (uaecptr, uae_u32) REGPARAM; \
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static void REGPARAM2 name ## _lput (uaecptr addr, uae_u32 l) \
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{ \
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uae_u8 *m; \
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addr -= name ## _bank.start & name ## _bank.mask; \
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addr &= name ## _bank.mask; \
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m = name ## _bank.baseaddr + addr; \
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do_put_mem_long ((uae_u32 *)m, l); \
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}
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#define MEMORY_WPUT(name, nojit) \
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static void REGPARAM3 name ## _wput (uaecptr, uae_u32) REGPARAM; \
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static void REGPARAM2 name ## _wput (uaecptr addr, uae_u32 w) \
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{ \
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uae_u8 *m; \
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addr -= name ## _bank.start & name ## _bank.mask; \
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addr &= name ## _bank.mask; \
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m = name ## _bank.baseaddr + addr; \
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do_put_mem_word ((uae_u16 *)m, w); \
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}
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#define MEMORY_BPUT(name, nojit) \
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static void REGPARAM3 name ## _bput (uaecptr, uae_u32) REGPARAM; \
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static void REGPARAM2 name ## _bput (uaecptr addr, uae_u32 b) \
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{ \
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addr -= name ## _bank.start & name ## _bank.mask; \
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addr &= name ## _bank.mask; \
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name ## _bank.baseaddr[addr] = b; \
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}
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#define MEMORY_CHECK(name) \
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static int REGPARAM3 name ## _check (uaecptr addr, uae_u32 size) REGPARAM; \
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static int REGPARAM2 name ## _check (uaecptr addr, uae_u32 size) \
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{ \
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addr -= name ## _bank.start & name ## _bank.mask; \
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addr &= name ## _bank.mask; \
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return (addr + size) <= name ## _bank.allocated; \
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}
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#define MEMORY_XLATE(name) \
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static uae_u8 *REGPARAM3 name ## _xlate (uaecptr addr) REGPARAM; \
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static uae_u8 *REGPARAM2 name ## _xlate (uaecptr addr) \
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{ \
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addr -= name ## _bank.start & name ## _bank.mask; \
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addr &= name ## _bank.mask; \
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return name ## _bank.baseaddr + addr; \
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}
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#endif
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#define DECLARE_MEMORY_FUNCTIONS(name) \
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static uae_u32 REGPARAM3 name ## _lget (uaecptr) REGPARAM; \
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static uae_u32 REGPARAM3 name ## _lgeti (uaecptr) REGPARAM; \
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static uae_u32 REGPARAM3 name ## _wget (uaecptr) REGPARAM; \
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static uae_u32 REGPARAM3 name ## _wgeti (uaecptr) REGPARAM; \
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static uae_u32 REGPARAM3 name ## _bget (uaecptr) REGPARAM; \
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static void REGPARAM3 name ## _lput (uaecptr, uae_u32) REGPARAM; \
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static void REGPARAM3 name ## _wput (uaecptr, uae_u32) REGPARAM; \
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static void REGPARAM3 name ## _bput (uaecptr, uae_u32) REGPARAM; \
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static int REGPARAM3 name ## _check (uaecptr addr, uae_u32 size) REGPARAM; \
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static uae_u8 *REGPARAM3 name ## _xlate (uaecptr addr) REGPARAM;
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#define MEMORY_FUNCTIONS(name) \
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MEMORY_LGET(name, 0); \
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MEMORY_WGET(name, 0); \
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MEMORY_BGET(name, 0); \
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MEMORY_LPUT(name, 0); \
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MEMORY_WPUT(name, 0); \
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MEMORY_BPUT(name, 0); \
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MEMORY_CHECK(name); \
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MEMORY_XLATE(name);
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#define MEMORY_FUNCTIONS_NOJIT(name) \
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MEMORY_LGET(name, 1); \
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MEMORY_WGET(name, 1); \
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MEMORY_BGET(name, 1); \
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MEMORY_LPUT(name, 1); \
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MEMORY_WPUT(name, 1); \
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MEMORY_BPUT(name, 1); \
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MEMORY_CHECK(name); \
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MEMORY_XLATE(name);
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extern addrbank chipmem_bank;
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extern addrbank chipmem_agnus_bank;
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extern addrbank chipmem_bank_ce2;
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extern addrbank kickmem_bank;
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extern addrbank custom_bank;
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extern addrbank filesys_bank;
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extern addrbank expamem_bank;
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extern addrbank expamem_null, expamem_none;
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extern addrbank fastmem_bank;
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extern addrbank fastmem_nojit_bank;
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extern addrbank fastmem2_bank;
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extern addrbank fastmem2_nojit_bank;
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extern addrbank bogomem_bank;
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extern addrbank custmem1_bank;
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extern addrbank custmem2_bank;
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extern uae_u32 last_custom_value1;
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/* Default memory access functions */
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extern void dummy_put (uaecptr addr, int size, uae_u32 val);
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extern uae_u32 dummy_get (uaecptr addr, int size, bool inst);
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extern int REGPARAM3 default_check(uaecptr addr, uae_u32 size) REGPARAM;
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extern uae_u8 *REGPARAM3 default_xlate(uaecptr addr) REGPARAM;
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/* 680x0 opcode fetches */
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extern uae_u32 REGPARAM3 dummy_lgeti (uaecptr addr) REGPARAM;
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extern uae_u32 REGPARAM3 dummy_wgeti (uaecptr addr) REGPARAM;
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/* sub bank support */
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extern uae_u32 REGPARAM3 sub_bank_lget (uaecptr) REGPARAM;
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extern uae_u32 REGPARAM3 sub_bank_wget(uaecptr) REGPARAM;
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extern uae_u32 REGPARAM3 sub_bank_bget(uaecptr) REGPARAM;
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extern void REGPARAM3 sub_bank_lput(uaecptr, uae_u32) REGPARAM;
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extern void REGPARAM3 sub_bank_wput(uaecptr, uae_u32) REGPARAM;
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extern void REGPARAM3 sub_bank_bput(uaecptr, uae_u32) REGPARAM;
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extern uae_u32 REGPARAM3 sub_bank_lgeti(uaecptr) REGPARAM;
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extern uae_u32 REGPARAM3 sub_bank_wgeti(uaecptr) REGPARAM;
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extern int REGPARAM3 sub_bank_check(uaecptr addr, uae_u32 size) REGPARAM;
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extern uae_u8 *REGPARAM3 sub_bank_xlate(uaecptr addr) REGPARAM;
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extern addrbank *get_sub_bank(uaecptr *addr);
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#define bankindex(addr) (((uaecptr)(addr)) >> 16)
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extern addrbank *mem_banks[MEMORY_BANKS];
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#ifdef JIT
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extern uae_u8 *baseaddr[MEMORY_BANKS];
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#endif
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#define get_mem_bank(addr) (*mem_banks[bankindex(addr)])
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extern addrbank *get_mem_bank_real(uaecptr);
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#ifdef JIT
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#define put_mem_bank(addr, b, realstart) do { \
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(mem_banks[bankindex(addr)] = (b)); \
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if ((b)->baseaddr) \
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baseaddr[bankindex(addr)] = (b)->baseaddr - (realstart); \
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else \
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baseaddr[bankindex(addr)] = (uae_u8*)(((uae_u8*)b)+1); \
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} while (0)
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#else
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#define put_mem_bank(addr, b, realstart) \
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(mem_banks[bankindex(addr)] = (b));
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#endif
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#ifdef WINUAE_FOR_HATARI
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extern bool memory_region_bus_error ( uaecptr addr );
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#endif
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extern void memory_init(uae_u32 nNewSTMemSize, uae_u32 nNewTTMemSize, uae_u32 nNewRomMemStart);
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extern void memory_uninit (void);
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extern void map_banks (addrbank *bank, int first, int count, int realsize);
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extern void map_banks_quick (addrbank *bank, int first, int count, int realsize);
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extern void map_banks_nojitdirect (addrbank *bank, int first, int count, int realsize);
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extern void map_banks_cond (addrbank *bank, int first, int count, int realsize);
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#ifdef WINUAE_FOR_HATARI
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extern void map_banks_ce (addrbank *bank, int first, int count, int realsize, int banktype, int cachable);
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#endif
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extern void memory_hardreset (void);
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extern void memory_clear (void);
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extern void free_fastmemory (int);
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#define longget(addr) (call_mem_get_func(get_mem_bank(addr).lget, addr))
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#define wordget(addr) (call_mem_get_func(get_mem_bank(addr).wget, addr))
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#define byteget(addr) (call_mem_get_func(get_mem_bank(addr).bget, addr))
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#define longgeti(addr) (call_mem_get_func(get_mem_bank(addr).lgeti, addr))
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#define wordgeti(addr) (call_mem_get_func(get_mem_bank(addr).wgeti, addr))
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#define longput(addr,l) (call_mem_put_func(get_mem_bank(addr).lput, addr, l))
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#define wordput(addr,w) (call_mem_put_func(get_mem_bank(addr).wput, addr, w))
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#define byteput(addr,b) (call_mem_put_func(get_mem_bank(addr).bput, addr, b))
|
|
|
|
STATIC_INLINE uae_u32 get_long (uaecptr addr)
|
|
{
|
|
return longget (addr);
|
|
}
|
|
STATIC_INLINE uae_u32 get_word (uaecptr addr)
|
|
{
|
|
return wordget (addr);
|
|
}
|
|
STATIC_INLINE uae_u32 get_byte (uaecptr addr)
|
|
{
|
|
return byteget (addr);
|
|
}
|
|
STATIC_INLINE uae_u32 get_longi(uaecptr addr)
|
|
{
|
|
return longgeti (addr);
|
|
}
|
|
STATIC_INLINE uae_u32 get_wordi(uaecptr addr)
|
|
{
|
|
return wordgeti (addr);
|
|
}
|
|
|
|
/*
|
|
* Read a host pointer from addr
|
|
*/
|
|
#if SIZEOF_VOID_P == 4
|
|
# define get_pointer(addr) ((void *)get_long (addr))
|
|
#else
|
|
# if SIZEOF_VOID_P == 8
|
|
STATIC_INLINE void *get_pointer (uaecptr addr)
|
|
{
|
|
const unsigned int n = SIZEOF_VOID_P / 4;
|
|
union {
|
|
void *ptr;
|
|
uae_u32 longs[SIZEOF_VOID_P / 4];
|
|
} p;
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < n; i++) {
|
|
#ifdef WORDS_BIGENDIAN
|
|
p.longs[i] = get_long (addr + i * 4);
|
|
#else
|
|
p.longs[n - 1 - i] = get_long (addr + i * 4);
|
|
#endif
|
|
}
|
|
return p.ptr;
|
|
}
|
|
# else
|
|
# error "Unknown or unsupported pointer size."
|
|
# endif
|
|
#endif
|
|
|
|
STATIC_INLINE void put_long (uaecptr addr, uae_u32 l)
|
|
{
|
|
longput(addr, l);
|
|
}
|
|
STATIC_INLINE void put_word (uaecptr addr, uae_u32 w)
|
|
{
|
|
wordput(addr, w);
|
|
}
|
|
STATIC_INLINE void put_byte (uaecptr addr, uae_u32 b)
|
|
{
|
|
byteput(addr, b);
|
|
}
|
|
|
|
extern void put_long_slow (uaecptr addr, uae_u32 v);
|
|
extern void put_word_slow (uaecptr addr, uae_u32 v);
|
|
extern void put_byte_slow (uaecptr addr, uae_u32 v);
|
|
extern uae_u32 get_long_slow (uaecptr addr);
|
|
extern uae_u32 get_word_slow (uaecptr addr);
|
|
extern uae_u32 get_byte_slow (uaecptr addr);
|
|
|
|
|
|
/*
|
|
* Store host pointer v at addr
|
|
*/
|
|
#if SIZEOF_VOID_P == 4
|
|
# define put_pointer(addr, p) (put_long ((addr), (uae_u32)(p)))
|
|
#else
|
|
# if SIZEOF_VOID_P == 8
|
|
STATIC_INLINE void put_pointer (uaecptr addr, void *v)
|
|
{
|
|
const unsigned int n = SIZEOF_VOID_P / 4;
|
|
union {
|
|
void *ptr;
|
|
uae_u32 longs[SIZEOF_VOID_P / 4];
|
|
} p;
|
|
unsigned int i;
|
|
|
|
p.ptr = v;
|
|
|
|
for (i = 0; i < n; i++) {
|
|
#ifdef WORDS_BIGENDIAN
|
|
put_long (addr + i * 4, p.longs[i]);
|
|
#else
|
|
put_long (addr + i * 4, p.longs[n - 1 - i]);
|
|
#endif
|
|
}
|
|
}
|
|
# endif
|
|
#endif
|
|
|
|
STATIC_INLINE uae_u8 *get_real_address (uaecptr addr)
|
|
{
|
|
return get_mem_bank (addr).xlateaddr(addr);
|
|
}
|
|
|
|
STATIC_INLINE int valid_address (uaecptr addr, uae_u32 size)
|
|
{
|
|
return get_mem_bank (addr).check(addr, size);
|
|
}
|
|
|
|
extern int addr_valid (const TCHAR*, uaecptr,uae_u32);
|
|
|
|
/* For faster access in custom chip emulation. */
|
|
extern void REGPARAM3 chipmem_lput (uaecptr, uae_u32) REGPARAM;
|
|
extern void REGPARAM3 chipmem_wput (uaecptr, uae_u32) REGPARAM;
|
|
extern void REGPARAM3 chipmem_bput (uaecptr, uae_u32) REGPARAM;
|
|
|
|
extern uae_u32 REGPARAM3 chipmem_agnus_wget (uaecptr) REGPARAM;
|
|
extern void REGPARAM3 chipmem_agnus_wput (uaecptr, uae_u32) REGPARAM;
|
|
|
|
/* 68020+ Chip RAM DMA contention emulation */
|
|
extern void REGPARAM3 chipmem_bput_c2 (uaecptr, uae_u32) REGPARAM;
|
|
|
|
extern uae_u32 (REGPARAM3 *chipmem_lget_indirect)(uaecptr) REGPARAM;
|
|
extern uae_u32 (REGPARAM3 *chipmem_wget_indirect)(uaecptr) REGPARAM;
|
|
extern uae_u32 (REGPARAM3 *chipmem_bget_indirect)(uaecptr) REGPARAM;
|
|
extern void (REGPARAM3 *chipmem_lput_indirect)(uaecptr, uae_u32) REGPARAM;
|
|
extern void (REGPARAM3 *chipmem_wput_indirect)(uaecptr, uae_u32) REGPARAM;
|
|
extern void (REGPARAM3 *chipmem_bput_indirect)(uaecptr, uae_u32) REGPARAM;
|
|
extern int (REGPARAM3 *chipmem_check_indirect)(uaecptr, uae_u32) REGPARAM;
|
|
extern uae_u8 *(REGPARAM3 *chipmem_xlate_indirect)(uaecptr) REGPARAM;
|
|
|
|
#ifdef NATMEM_OFFSET
|
|
|
|
typedef struct shmpiece_reg {
|
|
uae_u8 *native_address;
|
|
int id;
|
|
uae_u32 size;
|
|
const TCHAR *name;
|
|
struct shmpiece_reg *next;
|
|
struct shmpiece_reg *prev;
|
|
} shmpiece;
|
|
|
|
extern shmpiece *shm_start;
|
|
|
|
#endif
|
|
|
|
extern bool mapped_malloc (addrbank*);
|
|
extern void mapped_free (addrbank*);
|
|
extern void clearexec (void);
|
|
|
|
extern uaecptr strcpyha_safe (uaecptr dst, const uae_char *src);
|
|
extern uae_char *strcpyah_safe (uae_char *dst, uaecptr src, int maxsize);
|
|
extern void memcpyha_safe (uaecptr dst, const uae_u8 *src, int size);
|
|
extern void memcpyha (uaecptr dst, const uae_u8 *src, int size);
|
|
extern void memcpyah_safe (uae_u8 *dst, uaecptr src, int size);
|
|
extern void memcpyah (uae_u8 *dst, uaecptr src, int size);
|
|
|
|
|
|
#define UAE_MEMORY_REGIONS_MAX 64
|
|
#define UAE_MEMORY_REGION_NAME_LENGTH 64
|
|
|
|
#define UAE_MEMORY_REGION_RAM (1 << 0)
|
|
#define UAE_MEMORY_REGION_ALIAS (1 << 1)
|
|
#define UAE_MEMORY_REGION_MIRROR (1 << 2)
|
|
|
|
/* Get a list of memory regions in the Amiga address space */
|
|
|
|
typedef struct UaeMemoryRegion {
|
|
uaecptr start;
|
|
int size;
|
|
TCHAR name[UAE_MEMORY_REGION_NAME_LENGTH];
|
|
TCHAR rom_name[UAE_MEMORY_REGION_NAME_LENGTH];
|
|
uaecptr alias;
|
|
int flags;
|
|
uae_u8 *memory;
|
|
} UaeMemoryRegion;
|
|
|
|
typedef struct UaeMemoryMap {
|
|
UaeMemoryRegion regions[UAE_MEMORY_REGIONS_MAX];
|
|
int num_regions;
|
|
} UaeMemoryMap;
|
|
|
|
void uae_memory_map(UaeMemoryMap *map);
|
|
#endif /* MEMORY_H */
|