mirror of
https://github.com/Wiimpathy/HatariWii.git
synced 2025-11-04 07:16:00 +01:00
876 lines
21 KiB
C
876 lines
21 KiB
C
/*
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* UAE - The Un*x Amiga Emulator
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*
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* Read 68000 CPU specs from file "table68k"
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*
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* Copyright 1995,1996 Bernd Schmidt
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*/
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#include "sysconfig.h"
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#include "sysdeps.h"
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#include <ctype.h>
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#include <string.h>
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#include "readcpu.h"
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int nr_cpuop_funcs;
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struct mnemolookup lookuptab[] = {
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{ i_ILLG, _T("ILLEGAL") },
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{ i_OR, _T("OR") },
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{ i_CHK, _T("CHK") },
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{ i_CHK2, _T("CHK2") },
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{ i_AND, _T("AND") },
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{ i_EOR, _T("EOR") },
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{ i_ORSR, _T("ORSR") },
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{ i_ANDSR, _T("ANDSR") },
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{ i_EORSR, _T("EORSR") },
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{ i_SUB, _T("SUB") },
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{ i_SUBA, _T("SUBA") },
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{ i_SUBX, _T("SUBX") },
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{ i_SBCD, _T("SBCD") },
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{ i_ADD, _T("ADD") },
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{ i_ADDA, _T("ADDA") },
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{ i_ADDX, _T("ADDX") },
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{ i_ABCD, _T("ABCD") },
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{ i_NEG, _T("NEG") },
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{ i_NEGX, _T("NEGX") },
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{ i_NBCD, _T("NBCD") },
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{ i_CLR, _T("CLR") },
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{ i_NOT, _T("NOT") },
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{ i_TST, _T("TST") },
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{ i_BTST, _T("BTST") },
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{ i_BCHG, _T("BCHG") },
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{ i_BCLR, _T("BCLR") },
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{ i_BSET, _T("BSET") },
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{ i_CMP, _T("CMP") },
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{ i_CMPM, _T("CMPM") },
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{ i_CMPA, _T("CMPA") },
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{ i_MVPRM, _T("MVPRM") },
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{ i_MVPMR, _T("MVPMR") },
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{ i_MOVE, _T("MOVE") },
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{ i_MOVEA, _T("MOVEA") },
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{ i_MVSR2, _T("MVSR2") },
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{ i_MV2SR, _T("MV2SR") },
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{ i_SWAP, _T("SWAP") },
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{ i_EXG, _T("EXG") },
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{ i_EXT, _T("EXT") },
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{ i_MVMEL, _T("MVMEL"), _T("MOVEM") },
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{ i_MVMLE, _T("MVMLE"), _T("MOVEM") },
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{ i_TRAP, _T("TRAP") },
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{ i_MVR2USP, _T("MVR2USP") },
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{ i_MVUSP2R, _T("MVUSP2R") },
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{ i_NOP, _T("NOP") },
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{ i_RESET, _T("RESET") },
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{ i_RTE, _T("RTE") },
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{ i_RTD, _T("RTD") },
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{ i_LINK, _T("LINK") },
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{ i_UNLK, _T("UNLK") },
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{ i_RTS, _T("RTS") },
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{ i_STOP, _T("STOP") },
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{ i_TRAPV, _T("TRAPV") },
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{ i_RTR, _T("RTR") },
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{ i_JSR, _T("JSR") },
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{ i_JMP, _T("JMP") },
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{ i_BSR, _T("BSR") },
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{ i_Bcc, _T("Bcc") },
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{ i_LEA, _T("LEA") },
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{ i_PEA, _T("PEA") },
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{ i_DBcc, _T("DBcc") },
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{ i_Scc, _T("Scc") },
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{ i_DIVU, _T("DIVU") },
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{ i_DIVS, _T("DIVS") },
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{ i_MULU, _T("MULU") },
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{ i_MULS, _T("MULS") },
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{ i_ASR, _T("ASR") },
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{ i_ASL, _T("ASL") },
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{ i_LSR, _T("LSR") },
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{ i_LSL, _T("LSL") },
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{ i_ROL, _T("ROL") },
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{ i_ROR, _T("ROR") },
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{ i_ROXL, _T("ROXL") },
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{ i_ROXR, _T("ROXR") },
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{ i_ASRW, _T("ASRW") },
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{ i_ASLW, _T("ASLW") },
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{ i_LSRW, _T("LSRW") },
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{ i_LSLW, _T("LSLW") },
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{ i_ROLW, _T("ROLW") },
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{ i_RORW, _T("RORW") },
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{ i_ROXLW, _T("ROXLW") },
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{ i_ROXRW, _T("ROXRW") },
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{ i_MOVE2C, _T("MOVE2C"), _T("MOVEC") },
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{ i_MOVEC2, _T("MOVEC2"), _T("MOVEC") },
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{ i_CAS, _T("CAS") },
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{ i_CAS2, _T("CAS2") },
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{ i_MULL, _T("MULL") },
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{ i_DIVL, _T("DIVL") },
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{ i_BFTST, _T("BFTST") },
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{ i_BFEXTU, _T("BFEXTU") },
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{ i_BFCHG, _T("BFCHG") },
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{ i_BFEXTS, _T("BFEXTS") },
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{ i_BFCLR, _T("BFCLR") },
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{ i_BFFFO, _T("BFFFO") },
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{ i_BFSET, _T("BFSET") },
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{ i_BFINS, _T("BFINS") },
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{ i_PACK, _T("PACK") },
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{ i_UNPK, _T("UNPK") },
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{ i_TAS, _T("TAS") },
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{ i_BKPT, _T("BKPT") },
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{ i_CALLM, _T("CALLM") },
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{ i_RTM, _T("RTM") },
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{ i_TRAPcc, _T("TRAPcc") },
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{ i_MOVES, _T("MOVES") },
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{ i_FPP, _T("FPP") },
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{ i_FDBcc, _T("FDBcc") },
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{ i_FScc, _T("FScc") },
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{ i_FTRAPcc, _T("FTRAPcc") },
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{ i_FBcc, _T("FBcc") },
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{ i_FBcc, _T("FBcc") },
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{ i_FSAVE, _T("FSAVE") },
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{ i_FRESTORE, _T("FRESTORE") },
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{ i_CINVL, _T("CINVL") },
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{ i_CINVP, _T("CINVP") },
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{ i_CINVA, _T("CINVA") },
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{ i_CPUSHL, _T("CPUSHL") },
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{ i_CPUSHP, _T("CPUSHP") },
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{ i_CPUSHA, _T("CPUSHA") },
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{ i_MOVE16, _T("MOVE16") },
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{ i_MMUOP030, _T("MMUOP030") },
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{ i_PFLUSHN, _T("PFLUSHN") },
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{ i_PFLUSH, _T("PFLUSH") },
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{ i_PFLUSHAN, _T("PFLUSHAN") },
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{ i_PFLUSHA, _T("PFLUSHA") },
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{ i_PLPAR, _T("PLPAR") },
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{ i_PLPAW, _T("PLPAW") },
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{ i_PTESTR, _T("PTESTR") },
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{ i_PTESTW, _T("PTESTW") },
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{ i_LPSTOP, _T("LPSTOP") },
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{ i_ILLG, _T("") },
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};
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struct instr *table68k;
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static amodes mode_from_str (const TCHAR *str)
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{
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if (_tcsncmp (str, _T("Dreg"), 4) == 0) return Dreg;
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if (_tcsncmp (str, _T("Areg"), 4) == 0) return Areg;
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if (_tcsncmp (str, _T("Aind"), 4) == 0) return Aind;
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if (_tcsncmp (str, _T("Apdi"), 4) == 0) return Apdi;
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if (_tcsncmp (str, _T("Aipi"), 4) == 0) return Aipi;
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if (_tcsncmp (str, _T("Ad16"), 4) == 0) return Ad16;
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if (_tcsncmp (str, _T("Ad8r"), 4) == 0) return Ad8r;
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if (_tcsncmp (str, _T("absw"), 4) == 0) return absw;
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if (_tcsncmp (str, _T("absl"), 4) == 0) return absl;
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if (_tcsncmp (str, _T("PC16"), 4) == 0) return PC16;
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if (_tcsncmp (str, _T("PC8r"), 4) == 0) return PC8r;
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if (_tcsncmp (str, _T("Immd"), 4) == 0) return imm;
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abort ();
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return 0;
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}
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STATIC_INLINE amodes mode_from_mr (int mode, int reg)
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{
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switch (mode) {
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case 0: return Dreg;
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case 1: return Areg;
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case 2: return Aind;
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case 3: return Aipi;
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case 4: return Apdi;
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case 5: return Ad16;
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case 6: return Ad8r;
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case 7:
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switch (reg) {
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case 0: return absw;
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case 1: return absl;
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case 2: return PC16;
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case 3: return PC8r;
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case 4: return imm;
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case 5:
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case 6:
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case 7: return am_illg;
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}
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}
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abort ();
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return 0;
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}
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static void build_insn (int insn)
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{
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int find = -1;
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int variants;
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int isjmp = 0;
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struct instr_def id;
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const TCHAR *opcstr;
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int i;
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int flaglive = 0, flagdead = 0;
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id = defs68k[insn];
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/* Note: We treat anything with unknown flags as a jump. That
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is overkill, but "the programmer" was lazy quite often, and
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*this* programmer can't be bothered to work out what can and
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can't trap. Usually, this will be overwritten with the gencomp
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based information, anyway. */
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for (i = 0; i < 5; i++) {
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switch (id.flaginfo[i].flagset){
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case fa_unset: break;
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case fa_isjmp: isjmp = 1; break;
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case fa_isbranch: isjmp = 1; break;
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case fa_zero: flagdead |= 1 << i; break;
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case fa_one: flagdead |= 1 << i; break;
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case fa_dontcare: flagdead |= 1 << i; break;
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case fa_unknown: isjmp = 1; flagdead = -1; goto out1;
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case fa_set: flagdead |= 1 << i; break;
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}
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}
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out1:
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for (i = 0; i < 5; i++) {
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switch (id.flaginfo[i].flaguse) {
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case fu_unused: break;
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case fu_isjmp: isjmp = 1; flaglive |= 1 << i; break;
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case fu_maybecc: isjmp = 1; flaglive |= 1 << i; break;
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case fu_unknown: isjmp = 1; flaglive |= 1 << i; break;
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case fu_used: flaglive |= 1 << i; break;
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}
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}
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opcstr = id.opcstr;
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for (variants = 0; variants < (1 << id.n_variable); variants++) {
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int bitcnt[lastbit];
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int bitval[lastbit];
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int bitpos[lastbit];
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int i;
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uae_u16 opc = id.bits;
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uae_u16 msk, vmsk;
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int pos = 0;
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int mnp = 0;
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int bitno = 0;
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int unsized = 1;
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TCHAR mnemonic[10];
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int mnemo;
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wordsizes sz = sz_long;
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int srcgather = 0, dstgather = 0;
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int usesrc = 0, usedst = 0;
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int srctype = 0;
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int srcpos = -1, dstpos = -1;
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amodes srcmode = am_unknown, destmode = am_unknown;
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int srcreg = -1, destreg = -1;
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for (i = 0; i < lastbit; i++)
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bitcnt[i] = bitval[i] = 0;
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vmsk = 1 << id.n_variable;
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for (i = 0, msk = 0x8000; i < 16; i++, msk >>= 1) {
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if (!(msk & id.mask)) {
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int currbit = id.bitpos[bitno++];
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int bit_set;
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vmsk >>= 1;
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bit_set = variants & vmsk ? 1 : 0;
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if (bit_set)
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opc |= msk;
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bitpos[currbit] = 15 - i;
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bitcnt[currbit]++;
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bitval[currbit] <<= 1;
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bitval[currbit] |= bit_set;
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}
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}
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if (bitval[bitj] == 0) bitval[bitj] = 8;
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/* first check whether this one does not match after all */
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if (bitval[bitz] == 3 || bitval[bitC] == 1)
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continue;
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if (bitcnt[bitI] && (bitval[bitI] == 0x00 || bitval[bitI] == 0xff))
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continue;
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/* bitI and bitC get copied to biti and bitc */
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if (bitcnt[bitI]) {
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bitval[biti] = bitval[bitI]; bitpos[biti] = bitpos[bitI];
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}
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if (bitcnt[bitC])
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bitval[bitc] = bitval[bitC];
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pos = 0;
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while (opcstr[pos] && !_istspace(opcstr[pos])) {
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if (opcstr[pos] == '.') {
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pos++;
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unsized = 0;
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switch (opcstr[pos]) {
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case 'B': sz = sz_byte; break;
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case 'W': sz = sz_word; break;
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case 'L': sz = sz_long; break;
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case 'z':
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switch (bitval[bitz]) {
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case 0: sz = sz_byte; break;
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case 1: sz = sz_word; break;
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case 2: sz = sz_long; break;
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default: abort();
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}
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break;
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default: abort();
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}
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} else {
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mnemonic[mnp] = opcstr[pos];
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if (mnemonic[mnp] == 'f') {
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find = -1;
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switch (bitval[bitf]) {
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case 0: mnemonic[mnp] = 'R'; break;
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case 1: mnemonic[mnp] = 'L'; break;
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default: abort();
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}
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}
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mnp++;
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}
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pos++;
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}
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mnemonic[mnp] = 0;
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/* now, we have read the mnemonic and the size */
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while (opcstr[pos] && _istspace(opcstr[pos]))
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pos++;
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/* A goto a day keeps the D******a away. */
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if (opcstr[pos] == 0)
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goto endofline;
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/* parse the source address */
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usesrc = 1;
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switch (opcstr[pos++]) {
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case 'D':
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srcmode = Dreg;
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switch (opcstr[pos++]) {
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case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break;
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case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break;
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default: abort();
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}
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break;
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case 'A':
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srcmode = Areg;
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switch (opcstr[pos++]) {
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case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break;
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case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break;
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default: abort();
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}
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switch (opcstr[pos]) {
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case 'p': srcmode = Apdi; pos++; break;
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case 'P': srcmode = Aipi; pos++; break;
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case 'a': srcmode = Aind; pos++; break;
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}
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break;
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case 'L':
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srcmode = absl;
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break;
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case '#':
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switch (opcstr[pos++]) {
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case 'z': srcmode = imm; break;
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case '0': srcmode = imm0; break;
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case '1': srcmode = imm1; break;
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case '2': srcmode = imm2; break;
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case 'i': srcmode = immi; srcreg = (uae_s32)(uae_s8)bitval[biti];
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if (CPU_EMU_SIZE < 4) {
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/* Used for branch instructions */
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srctype = 1;
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srcgather = 1;
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srcpos = bitpos[biti];
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}
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break;
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case 'j': srcmode = immi; srcreg = bitval[bitj];
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if (CPU_EMU_SIZE < 3) {
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/* 1..8 for ADDQ/SUBQ and rotshi insns */
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srcgather = 1;
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srctype = 3;
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srcpos = bitpos[bitj];
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}
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break;
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case 'J': srcmode = immi; srcreg = bitval[bitJ];
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if (CPU_EMU_SIZE < 5) {
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/* 0..15 */
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srcgather = 1;
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srctype = 2;
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srcpos = bitpos[bitJ];
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}
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break;
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case 'k': srcmode = immi; srcreg = bitval[bitk];
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if (CPU_EMU_SIZE < 3) {
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srcgather = 1;
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srctype = 4;
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srcpos = bitpos[bitk];
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}
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break;
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case 'K': srcmode = immi; srcreg = bitval[bitK];
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if (CPU_EMU_SIZE < 5) {
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/* 0..15 */
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srcgather = 1;
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srctype = 5;
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srcpos = bitpos[bitK];
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}
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break;
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case 'p': srcmode = immi; srcreg = bitval[bitK];
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if (CPU_EMU_SIZE < 5) {
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/* 0..3 */
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srcgather = 1;
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srctype = 7;
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srcpos = bitpos[bitp];
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}
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break;
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default: abort();
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}
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break;
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case 'd':
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srcreg = bitval[bitD];
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srcmode = mode_from_mr(bitval[bitd],bitval[bitD]);
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if (srcmode == am_illg)
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continue;
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if (CPU_EMU_SIZE < 2 &&
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(srcmode == Areg || srcmode == Dreg || srcmode == Aind
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|| srcmode == Ad16 || srcmode == Ad8r || srcmode == Aipi
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|| srcmode == Apdi))
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{
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srcgather = 1; srcpos = bitpos[bitD];
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}
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if (opcstr[pos] == '[') {
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pos++;
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if (opcstr[pos] == '!') {
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/* exclusion */
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do {
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pos++;
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if (mode_from_str(opcstr+pos) == srcmode)
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goto nomatch;
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pos += 4;
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} while (opcstr[pos] == ',');
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pos++;
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} else {
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if (opcstr[pos+4] == '-') {
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/* replacement */
|
|
if (mode_from_str(opcstr+pos) == srcmode)
|
|
srcmode = mode_from_str(opcstr+pos+5);
|
|
else
|
|
goto nomatch;
|
|
pos += 10;
|
|
} else {
|
|
/* normal */
|
|
while(mode_from_str(opcstr+pos) != srcmode) {
|
|
pos += 4;
|
|
if (opcstr[pos] == ']')
|
|
goto nomatch;
|
|
pos++;
|
|
}
|
|
while(opcstr[pos] != ']') pos++;
|
|
pos++;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
/* Some addressing modes are invalid as destination */
|
|
if (srcmode == imm || srcmode == PC16 || srcmode == PC8r)
|
|
goto nomatch;
|
|
break;
|
|
case 's':
|
|
srcreg = bitval[bitS];
|
|
srcmode = mode_from_mr(bitval[bits],bitval[bitS]);
|
|
|
|
if (srcmode == am_illg)
|
|
continue;
|
|
if (CPU_EMU_SIZE < 2 &&
|
|
(srcmode == Areg || srcmode == Dreg || srcmode == Aind
|
|
|| srcmode == Ad16 || srcmode == Ad8r || srcmode == Aipi
|
|
|| srcmode == Apdi))
|
|
{
|
|
srcgather = 1; srcpos = bitpos[bitS];
|
|
}
|
|
if (opcstr[pos] == '[') {
|
|
pos++;
|
|
if (opcstr[pos] == '!') {
|
|
/* exclusion */
|
|
do {
|
|
pos++;
|
|
if (mode_from_str(opcstr+pos) == srcmode)
|
|
goto nomatch;
|
|
pos += 4;
|
|
} while (opcstr[pos] == ',');
|
|
pos++;
|
|
} else {
|
|
if (opcstr[pos+4] == '-') {
|
|
/* replacement */
|
|
if (mode_from_str(opcstr+pos) == srcmode)
|
|
srcmode = mode_from_str(opcstr+pos+5);
|
|
else
|
|
goto nomatch;
|
|
pos += 10;
|
|
} else {
|
|
/* normal */
|
|
while(mode_from_str(opcstr+pos) != srcmode) {
|
|
pos += 4;
|
|
if (opcstr[pos] == ']')
|
|
goto nomatch;
|
|
pos++;
|
|
}
|
|
while(opcstr[pos] != ']') pos++;
|
|
pos++;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
default: abort();
|
|
}
|
|
/* safety check - might have changed */
|
|
if (srcmode != Areg && srcmode != Dreg && srcmode != Aind
|
|
&& srcmode != Ad16 && srcmode != Ad8r && srcmode != Aipi
|
|
&& srcmode != Apdi && srcmode != immi)
|
|
{
|
|
srcgather = 0;
|
|
}
|
|
if (srcmode == Areg && sz == sz_byte)
|
|
goto nomatch;
|
|
|
|
if (opcstr[pos] != ',')
|
|
goto endofline;
|
|
pos++;
|
|
|
|
/* parse the destination address */
|
|
usedst = 1;
|
|
switch (opcstr[pos++]) {
|
|
case 'D':
|
|
destmode = Dreg;
|
|
switch (opcstr[pos++]) {
|
|
case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break;
|
|
case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break;
|
|
default: abort();
|
|
}
|
|
if (dstpos < 0 || dstpos >= 32)
|
|
abort ();
|
|
break;
|
|
case 'A':
|
|
destmode = Areg;
|
|
switch (opcstr[pos++]) {
|
|
case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break;
|
|
case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break;
|
|
case 'x': destreg = 0; dstgather = 0; dstpos = 0; break;
|
|
default: abort();
|
|
}
|
|
if (dstpos < 0 || dstpos >= 32)
|
|
abort ();
|
|
switch (opcstr[pos]) {
|
|
case 'p': destmode = Apdi; pos++; break;
|
|
case 'P': destmode = Aipi; pos++; break;
|
|
}
|
|
break;
|
|
case 'L':
|
|
destmode = absl;
|
|
break;
|
|
case '#':
|
|
switch (opcstr[pos++]) {
|
|
case 'z': destmode = imm; break;
|
|
case '0': destmode = imm0; break;
|
|
case '1': destmode = imm1; break;
|
|
case '2': destmode = imm2; break;
|
|
case 'i': destmode = immi; destreg = (uae_s32)(uae_s8)bitval[biti]; break;
|
|
case 'j': destmode = immi; destreg = bitval[bitj]; break;
|
|
case 'J': destmode = immi; destreg = bitval[bitJ]; break;
|
|
case 'k': destmode = immi; destreg = bitval[bitk]; break;
|
|
case 'K': destmode = immi; destreg = bitval[bitK]; break;
|
|
default: abort();
|
|
}
|
|
break;
|
|
case 'd':
|
|
destreg = bitval[bitD];
|
|
destmode = mode_from_mr(bitval[bitd],bitval[bitD]);
|
|
if (destmode == am_illg)
|
|
continue;
|
|
if (CPU_EMU_SIZE < 1 &&
|
|
(destmode == Areg || destmode == Dreg || destmode == Aind
|
|
|| destmode == Ad16 || destmode == Ad8r || destmode == Aipi
|
|
|| destmode == Apdi))
|
|
{
|
|
dstgather = 1; dstpos = bitpos[bitD];
|
|
}
|
|
|
|
if (opcstr[pos] == '[') {
|
|
pos++;
|
|
if (opcstr[pos] == '!') {
|
|
/* exclusion */
|
|
do {
|
|
pos++;
|
|
if (mode_from_str(opcstr+pos) == destmode)
|
|
goto nomatch;
|
|
pos += 4;
|
|
} while (opcstr[pos] == ',');
|
|
pos++;
|
|
} else {
|
|
if (opcstr[pos+4] == '-') {
|
|
/* replacement */
|
|
if (mode_from_str(opcstr+pos) == destmode)
|
|
destmode = mode_from_str(opcstr+pos+5);
|
|
else
|
|
goto nomatch;
|
|
pos += 10;
|
|
} else {
|
|
/* normal */
|
|
while(mode_from_str(opcstr+pos) != destmode) {
|
|
pos += 4;
|
|
if (opcstr[pos] == ']')
|
|
goto nomatch;
|
|
pos++;
|
|
}
|
|
while(opcstr[pos] != ']') pos++;
|
|
pos++;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
/* Some addressing modes are invalid as destination */
|
|
if (destmode == imm || destmode == PC16 || destmode == PC8r)
|
|
goto nomatch;
|
|
break;
|
|
case 's':
|
|
destreg = bitval[bitS];
|
|
destmode = mode_from_mr(bitval[bits],bitval[bitS]);
|
|
|
|
if (destmode == am_illg)
|
|
continue;
|
|
if (CPU_EMU_SIZE < 1 &&
|
|
(destmode == Areg || destmode == Dreg || destmode == Aind
|
|
|| destmode == Ad16 || destmode == Ad8r || destmode == Aipi
|
|
|| destmode == Apdi))
|
|
{
|
|
dstgather = 1; dstpos = bitpos[bitS];
|
|
}
|
|
|
|
if (opcstr[pos] == '[') {
|
|
pos++;
|
|
if (opcstr[pos] == '!') {
|
|
/* exclusion */
|
|
do {
|
|
pos++;
|
|
if (mode_from_str(opcstr+pos) == destmode)
|
|
goto nomatch;
|
|
pos += 4;
|
|
} while (opcstr[pos] == ',');
|
|
pos++;
|
|
} else {
|
|
if (opcstr[pos+4] == '-') {
|
|
/* replacement */
|
|
if (mode_from_str(opcstr+pos) == destmode)
|
|
destmode = mode_from_str(opcstr+pos+5);
|
|
else
|
|
goto nomatch;
|
|
pos += 10;
|
|
} else {
|
|
/* normal */
|
|
while(mode_from_str(opcstr+pos) != destmode) {
|
|
pos += 4;
|
|
if (opcstr[pos] == ']')
|
|
goto nomatch;
|
|
pos++;
|
|
}
|
|
while(opcstr[pos] != ']') pos++;
|
|
pos++;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
default: abort();
|
|
}
|
|
/* safety check - might have changed */
|
|
if (destmode != Areg && destmode != Dreg && destmode != Aind
|
|
&& destmode != Ad16 && destmode != Ad8r && destmode != Aipi
|
|
&& destmode != Apdi)
|
|
{
|
|
dstgather = 0;
|
|
}
|
|
|
|
if (destmode == Areg && sz == sz_byte)
|
|
goto nomatch;
|
|
#if 0
|
|
if (sz == sz_byte && (destmode == Aipi || destmode == Apdi)) {
|
|
dstgather = 0;
|
|
}
|
|
#endif
|
|
endofline:
|
|
/* now, we have a match */
|
|
if (table68k[opc].mnemo != i_ILLG)
|
|
;//write_log (_T("Double match: %x: %s\n"), opc, opcstr);
|
|
if (find == -1) {
|
|
for (find = 0;; find++) {
|
|
if (_tcscmp (mnemonic, lookuptab[find].name) == 0) {
|
|
table68k[opc].mnemo = lookuptab[find].mnemo;
|
|
break;
|
|
}
|
|
if (_tcslen (lookuptab[find].name) == 0)
|
|
abort();
|
|
}
|
|
}
|
|
else {
|
|
table68k[opc].mnemo = lookuptab[find].mnemo;
|
|
}
|
|
table68k[opc].cc = bitval[bitc];
|
|
mnemo = table68k[opc].mnemo;
|
|
if (mnemo == i_BTST
|
|
|| mnemo == i_BSET
|
|
|| mnemo == i_BCLR
|
|
|| mnemo == i_BCHG)
|
|
{
|
|
sz = destmode == Dreg ? sz_long : sz_byte;
|
|
unsized = 0;
|
|
}
|
|
if (mnemo == i_JSR || mnemo == i_JMP) {
|
|
unsized = 1;
|
|
}
|
|
|
|
table68k[opc].size = sz;
|
|
table68k[opc].unsized = unsized;
|
|
table68k[opc].sduse = id.sduse;
|
|
table68k[opc].sreg = srcreg;
|
|
table68k[opc].dreg = destreg;
|
|
table68k[opc].smode = srcmode;
|
|
table68k[opc].dmode = destmode;
|
|
table68k[opc].spos = srcgather ? srcpos : -1;
|
|
table68k[opc].dpos = dstgather ? dstpos : -1;
|
|
table68k[opc].suse = usesrc;
|
|
table68k[opc].duse = usedst;
|
|
table68k[opc].stype = srctype;
|
|
table68k[opc].plev = id.plevel;
|
|
table68k[opc].clev = id.cpulevel;
|
|
table68k[opc].unimpclev = id.unimpcpulevel;
|
|
table68k[opc].head = id.head;
|
|
table68k[opc].tail = id.tail;
|
|
table68k[opc].clocks = id.clocks;
|
|
table68k[opc].fetchmode = id.fetchmode;
|
|
|
|
#if 0
|
|
for (i = 0; i < 5; i++) {
|
|
table68k[opc].flaginfo[i].flagset = id.flaginfo[i].flagset;
|
|
table68k[opc].flaginfo[i].flaguse = id.flaginfo[i].flaguse;
|
|
}
|
|
#endif
|
|
table68k[opc].flagdead = flagdead;
|
|
table68k[opc].flaglive = flaglive;
|
|
table68k[opc].isjmp = isjmp;
|
|
nomatch:
|
|
/* FOO! */;
|
|
}
|
|
}
|
|
|
|
|
|
void read_table68k (void)
|
|
{
|
|
int i;
|
|
|
|
free (table68k);
|
|
table68k = xmalloc (struct instr, 65536);
|
|
for (i = 0; i < 65536; i++) {
|
|
table68k[i].mnemo = i_ILLG;
|
|
table68k[i].handler = -1;
|
|
}
|
|
for (i = 0; i < n_defs68k; i++) {
|
|
build_insn (i);
|
|
}
|
|
}
|
|
|
|
static int imismatch;
|
|
|
|
static void handle_merges (long int opcode)
|
|
{
|
|
uae_u16 smsk;
|
|
uae_u16 dmsk;
|
|
int sbitdst, dstend;
|
|
int srcreg, dstreg;
|
|
|
|
if (table68k[opcode].spos == -1) {
|
|
sbitdst = 1; smsk = 0;
|
|
} else {
|
|
switch (table68k[opcode].stype) {
|
|
case 0:
|
|
smsk = 7; sbitdst = 8; break;
|
|
case 1:
|
|
smsk = 255; sbitdst = 256; break;
|
|
case 2:
|
|
smsk = 15; sbitdst = 16; break;
|
|
case 3:
|
|
smsk = 7; sbitdst = 8; break;
|
|
case 4:
|
|
smsk = 7; sbitdst = 8; break;
|
|
case 5:
|
|
smsk = 63; sbitdst = 64; break;
|
|
case 7:
|
|
smsk = 3; sbitdst = 4; break;
|
|
default:
|
|
smsk = 0; sbitdst = 0;
|
|
abort();
|
|
break;
|
|
}
|
|
smsk <<= table68k[opcode].spos;
|
|
}
|
|
if (table68k[opcode].dpos == -1) {
|
|
dstend = 1; dmsk = 0;
|
|
} else {
|
|
dmsk = 7 << table68k[opcode].dpos;
|
|
dstend = 8;
|
|
}
|
|
for (srcreg=0; srcreg < sbitdst; srcreg++) {
|
|
for (dstreg=0; dstreg < dstend; dstreg++) {
|
|
uae_u16 code = (uae_u16)opcode;
|
|
|
|
code = (code & ~smsk) | (srcreg << table68k[opcode].spos);
|
|
code = (code & ~dmsk) | (dstreg << table68k[opcode].dpos);
|
|
|
|
/* Check whether this is in fact the same instruction.
|
|
* The instructions should never differ, except for the
|
|
* Bcc.(BW) case. */
|
|
if (table68k[code].mnemo != table68k[opcode].mnemo
|
|
|| table68k[code].size != table68k[opcode].size
|
|
|| table68k[code].suse != table68k[opcode].suse
|
|
|| table68k[code].duse != table68k[opcode].duse)
|
|
{
|
|
imismatch++; continue;
|
|
}
|
|
if (table68k[opcode].suse
|
|
&& (table68k[opcode].spos != table68k[code].spos
|
|
|| table68k[opcode].smode != table68k[code].smode
|
|
|| table68k[opcode].stype != table68k[code].stype))
|
|
{
|
|
imismatch++; continue;
|
|
}
|
|
if (table68k[opcode].duse
|
|
&& (table68k[opcode].dpos != table68k[code].dpos
|
|
|| table68k[opcode].dmode != table68k[code].dmode))
|
|
{
|
|
imismatch++; continue;
|
|
}
|
|
|
|
if (code != opcode)
|
|
table68k[code].handler = opcode;
|
|
}
|
|
}
|
|
}
|
|
|
|
void do_merges (void)
|
|
{
|
|
long int opcode;
|
|
int nr = 0;
|
|
imismatch = 0;
|
|
for (opcode = 0; opcode < 65536; opcode++) {
|
|
if (table68k[opcode].handler != -1 || table68k[opcode].mnemo == i_ILLG)
|
|
continue;
|
|
nr++;
|
|
handle_merges (opcode);
|
|
}
|
|
nr_cpuop_funcs = nr;
|
|
}
|
|
|
|
int get_no_mismatches (void)
|
|
{
|
|
return imismatch;
|
|
}
|