From 8f9f196c8efabcbd10291896e9fbeb74443f0a87 Mon Sep 17 00:00:00 2001
From: Maschell <Maschell@gmx.de>
Date: Fri, 29 May 2020 19:26:27 +0200
Subject: [PATCH] Add support for KernelReadSRs and KernelWriteSRs

---
 source/kernel.s |  14 ++++++-
 source/main.c   | 100 +++++++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 112 insertions(+), 2 deletions(-)

diff --git a/source/kernel.s b/source/kernel.s
index 563e7f0..4759d36 100644
--- a/source/kernel.s
+++ b/source/kernel.s
@@ -24,4 +24,16 @@ SCKernelCopyData_loop:
 KernelCopyDataInternal:
 	li %r0, 0x2500
 	sc
-	blr
\ No newline at end of file
+	blr
+
+.globl KernelReadSRsInternal
+KernelReadSRsInternal:
+    li %r0, 0x3600
+    sc
+    blr
+
+.globl KernelWriteSRsInternal
+KernelWriteSRsInternal:
+    li %r0, 0x0A00
+    sc
+    blr
\ No newline at end of file
diff --git a/source/main.c b/source/main.c
index e36dd80..3a4e1bc 100644
--- a/source/main.c
+++ b/source/main.c
@@ -13,15 +13,109 @@ WUMS_MODULE_EXPORT_NAME("homebrew_kernel");
 #define KERN_SYSCALL_TBL4 0xFFEAAA60 //Home menu
 #define KERN_SYSCALL_TBL5 0xFFEAAE60 //Browser
 
+typedef struct _sr_table_t {
+    uint32_t value[16];
+    uint32_t sdr1;
+} sr_table_t;
+
 extern void SCKernelCopyData(uint32_t dst, uint32_t src, uint32_t len);
 extern void KernelCopyDataInternal(uint32_t dst, uint32_t src, uint32_t len);
+extern void KernelWriteSRsInternal(sr_table_t * table);
+extern void KernelReadSRsInternal(sr_table_t * table);
 
 void kernelInitialize();
 
-extern void  KernelCopyData(uint32_t dst, uint32_t src, uint32_t len){
+void KernelReadSRsInternalFunc(sr_table_t * table) {
+    uint32_t i = 0;
+
+    // calculate PT_size ((end-start)*8/4096)*4 or (end-start)/128
+    // Minimum page table size is 64Kbytes.
+
+    asm volatile("eieio; isync");
+
+    asm volatile("mfspr %0, 25" : "=r" (table->sdr1));
+
+    asm volatile("mfsr %0, 0" : "=r" (table->value[i]));
+    i++;
+    asm volatile("mfsr %0, 1" : "=r" (table->value[i]));
+    i++;
+    asm volatile("mfsr %0, 2" : "=r" (table->value[i]));
+    i++;
+    asm volatile("mfsr %0, 3" : "=r" (table->value[i]));
+    i++;
+    asm volatile("mfsr %0, 4" : "=r" (table->value[i]));
+    i++;
+    asm volatile("mfsr %0, 5" : "=r" (table->value[i]));
+    i++;
+    asm volatile("mfsr %0, 6" : "=r" (table->value[i]));
+    i++;
+    asm volatile("mfsr %0, 7" : "=r" (table->value[i]));
+    i++;
+    asm volatile("mfsr %0, 8" : "=r" (table->value[i]));
+    i++;
+    asm volatile("mfsr %0, 9" : "=r" (table->value[i]));
+    i++;
+    asm volatile("mfsr %0, 10" : "=r" (table->value[i]));
+    i++;
+    asm volatile("mfsr %0, 11" : "=r" (table->value[i]));
+    i++;
+    asm volatile("mfsr %0, 12" : "=r" (table->value[i]));
+    i++;
+    asm volatile("mfsr %0, 13" : "=r" (table->value[i]));
+    i++;
+    asm volatile("mfsr %0, 14" : "=r" (table->value[i]));
+    i++;
+    asm volatile("mfsr %0, 15" : "=r" (table->value[i]));
+    i++;
+
+    asm volatile("eieio; isync");
+}
+
+void KernelWriteSRsInternalFunc(sr_table_t * table) {
+    uint32_t i = 0;
+
+    asm volatile("eieio; isync");
+
+    // Writing didn't work for all at once so we only write number 8.
+    // TODO: fix this and change it if required.
+
+    /*asm volatile("mtsr 0, %0" : : "r" (table->value[i])); i++;
+    asm volatile("mtsr 1, %0" : : "r" (table->value[i])); i++;
+    asm volatile("mtsr 2, %0" : : "r" (table->value[i])); i++;
+    asm volatile("mtsr 3, %0" : : "r" (table->value[i])); i++;
+    asm volatile("mtsr 4, %0" : : "r" (table->value[i])); i++;
+    asm volatile("mtsr 5, %0" : : "r" (table->value[i])); i++;*/
+    //asm volatile("mtsr 6, %0" : : "r" (table->value[6])); i++;
+    /*asm volatile("mtsr 7, %0" : : "r" (table->value[i])); i++;*/
+    asm volatile("mtsr 8, %0" : : "r" (table->value[8]));
+    //i++;
+    /*asm volatile("mtsr 9, %0" : : "r" (table->value[i])); i++;
+    asm volatile("mtsr 10, %0" : : "r" (table->value[i])); i++;
+    asm volatile("mtsr 11, %0" : : "r" (table->value[i])); i++;
+    asm volatile("mtsr 12, %0" : : "r" (table->value[i])); i++;
+    asm volatile("mtsr 13, %0" : : "r" (table->value[i])); i++;
+    asm volatile("mtsr 14, %0" : : "r" (table->value[i])); i++;
+    asm volatile("mtsr 15, %0" : : "r" (table->value[i])); i++;*/
+
+
+    asm volatile("isync");
+}
+
+void  KernelCopyData(uint32_t dst, uint32_t src, uint32_t len){
     KernelCopyDataInternal(dst, src, len);
 }
+
+void KernelWriteSRs(sr_table_t * table) {
+    KernelWriteSRsInternal(table);
+}
+
+void KernelReadSRs(sr_table_t * table) {
+    KernelReadSRsInternal(table);
+}
+
 WUMS_EXPORT_FUNCTION(KernelCopyData);
+WUMS_EXPORT_FUNCTION(KernelWriteSRs);
+WUMS_EXPORT_FUNCTION(KernelReadSRs);
 
 /* Write a 32-bit word with kernel permissions */
 void __attribute__ ((noinline)) kern_write(void *addr, uint32_t value) {
@@ -87,6 +181,10 @@ void kernelInitialize() {
     ucSyscallsSetupRequired = 0;
 
     PatchSyscall(0x25, (uint32_t) SCKernelCopyData);
+    PatchSyscall(0x36, (uint32_t) KernelReadSRsInternalFunc);
+    PatchSyscall(0x0A, (uint32_t) KernelWriteSRsInternalFunc);
+}
+
 WUMS_INITIALIZE(){
     kernelInitialize();
 }