2015-07-22 01:38:59 +02:00
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// Copyright 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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2016-04-30 17:34:51 +02:00
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#include <array>
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#include <cstddef>
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#include <type_traits>
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#include <nihstro/shader_bytecode.h>
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#include "common/assert.h"
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2015-07-22 01:38:59 +02:00
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "common/vector_math.h"
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2016-04-30 17:34:51 +02:00
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#include "video_core/pica_types.h"
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2017-01-28 22:27:24 +01:00
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#include "video_core/regs.h"
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2015-07-22 01:38:59 +02:00
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using nihstro::RegisterType;
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using nihstro::SourceRegister;
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using nihstro::DestRegister;
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namespace Pica {
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namespace Shader {
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2016-12-19 01:42:19 +01:00
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struct AttributeBuffer {
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2016-04-28 19:01:47 +02:00
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alignas(16) Math::Vec4<float24> attr[16];
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2015-07-22 01:38:59 +02:00
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};
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struct OutputVertex {
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Math::Vec4<float24> pos;
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2015-08-16 15:12:43 +02:00
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Math::Vec4<float24> quat;
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2015-07-22 01:38:59 +02:00
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Math::Vec4<float24> color;
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Math::Vec2<float24> tc0;
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Math::Vec2<float24> tc1;
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2016-04-18 10:51:13 +02:00
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float24 tc0_w;
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INSERT_PADDING_WORDS(1);
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2015-09-10 04:39:43 +02:00
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Math::Vec3<float24> view;
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INSERT_PADDING_WORDS(1);
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2015-07-22 01:38:59 +02:00
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Math::Vec2<float24> tc2;
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2017-01-28 05:16:36 +01:00
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static OutputVertex FromAttributeBuffer(const RasterizerRegs& regs, AttributeBuffer& output);
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2015-07-22 01:38:59 +02:00
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};
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2016-12-19 08:43:37 +01:00
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#define ASSERT_POS(var, pos) \
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static_assert(offsetof(OutputVertex, var) == pos * sizeof(float24), "Semantic at wrong " \
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"offset.")
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2017-01-28 05:16:36 +01:00
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ASSERT_POS(pos, RasterizerRegs::VSOutputAttributes::POSITION_X);
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ASSERT_POS(quat, RasterizerRegs::VSOutputAttributes::QUATERNION_X);
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ASSERT_POS(color, RasterizerRegs::VSOutputAttributes::COLOR_R);
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ASSERT_POS(tc0, RasterizerRegs::VSOutputAttributes::TEXCOORD0_U);
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ASSERT_POS(tc1, RasterizerRegs::VSOutputAttributes::TEXCOORD1_U);
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ASSERT_POS(tc0_w, RasterizerRegs::VSOutputAttributes::TEXCOORD0_W);
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ASSERT_POS(view, RasterizerRegs::VSOutputAttributes::VIEW_X);
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ASSERT_POS(tc2, RasterizerRegs::VSOutputAttributes::TEXCOORD2_U);
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2016-12-19 08:43:37 +01:00
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#undef ASSERT_POS
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static_assert(std::is_pod<OutputVertex>::value, "Structure is not POD");
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static_assert(sizeof(OutputVertex) == 24 * sizeof(float), "OutputVertex has invalid size");
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2015-07-22 01:38:59 +02:00
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/**
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* This structure contains the state information that needs to be unique for a shader unit. The 3DS
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* has four shader units that process shaders in parallel. At the present, Citra only implements a
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* single shader unit that processes all shaders serially. Putting the state information in a struct
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* here will make it easier for us to parallelize the shader processing later.
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*/
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struct UnitState {
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2015-08-15 22:51:32 +02:00
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struct Registers {
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// The registers are accessed by the shader JIT using SSE instructions, and are therefore
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// required to be 16-byte aligned.
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2016-03-09 07:28:26 +01:00
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alignas(16) Math::Vec4<float24> input[16];
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alignas(16) Math::Vec4<float24> temporary[16];
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2016-12-17 23:38:03 +01:00
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alignas(16) Math::Vec4<float24> output[16];
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2015-08-15 22:51:32 +02:00
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} registers;
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static_assert(std::is_pod<Registers>::value, "Structure is not POD");
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2015-07-22 01:38:59 +02:00
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bool conditional_code[2];
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// Two Address registers and one loop counter
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// TODO: How many bits do these actually have?
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s32 address_registers[3];
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2015-09-07 07:49:57 +02:00
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static size_t InputOffset(const SourceRegister& reg) {
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switch (reg.GetRegisterType()) {
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case RegisterType::Input:
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2016-09-18 02:38:01 +02:00
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return offsetof(UnitState, registers.input) +
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reg.GetIndex() * sizeof(Math::Vec4<float24>);
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2015-07-22 01:38:59 +02:00
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case RegisterType::Temporary:
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return offsetof(UnitState, registers.temporary) +
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reg.GetIndex() * sizeof(Math::Vec4<float24>);
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2015-07-22 01:38:59 +02:00
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default:
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UNREACHABLE();
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return 0;
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}
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}
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2015-09-07 07:49:57 +02:00
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static size_t OutputOffset(const DestRegister& reg) {
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switch (reg.GetRegisterType()) {
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case RegisterType::Output:
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2016-12-17 23:38:03 +01:00
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return offsetof(UnitState, registers.output) +
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reg.GetIndex() * sizeof(Math::Vec4<float24>);
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case RegisterType::Temporary:
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return offsetof(UnitState, registers.temporary) +
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reg.GetIndex() * sizeof(Math::Vec4<float24>);
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2015-07-22 01:38:59 +02:00
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default:
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UNREACHABLE();
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return 0;
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}
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}
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2016-12-17 06:41:38 +01:00
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/**
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* Loads the unit state with an input vertex.
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*
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2016-12-19 02:25:03 +01:00
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* @param config Shader configuration registers corresponding to the unit.
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* @param input Attribute buffer to load into the input registers.
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2016-12-17 06:41:38 +01:00
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*/
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2017-01-28 22:03:13 +01:00
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void LoadInput(const ShaderRegs& config, const AttributeBuffer& input);
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2016-12-19 02:58:30 +01:00
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2017-01-28 22:03:13 +01:00
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void WriteOutput(const ShaderRegs& config, AttributeBuffer& output);
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2015-07-22 01:38:59 +02:00
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};
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2016-03-30 02:45:18 +02:00
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struct ShaderSetup {
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struct {
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// The float uniforms are accessed by the shader JIT using SSE instructions, and are
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// therefore required to be 16-byte aligned.
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alignas(16) Math::Vec4<float24> f[96];
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2015-07-23 05:25:30 +02:00
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2016-03-30 02:45:18 +02:00
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std::array<bool, 16> b;
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std::array<Math::Vec4<u8>, 4> i;
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} uniforms;
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2015-07-12 01:57:59 +02:00
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2016-12-16 07:35:34 +01:00
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static size_t GetFloatUniformOffset(unsigned index) {
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return offsetof(ShaderSetup, uniforms.f) + index * sizeof(Math::Vec4<float24>);
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}
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2016-05-13 08:46:14 +02:00
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2016-12-16 07:35:34 +01:00
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static size_t GetBoolUniformOffset(unsigned index) {
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return offsetof(ShaderSetup, uniforms.b) + index * sizeof(bool);
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}
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2016-05-13 08:46:14 +02:00
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2016-12-16 07:35:34 +01:00
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static size_t GetIntUniformOffset(unsigned index) {
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return offsetof(ShaderSetup, uniforms.i) + index * sizeof(Math::Vec4<u8>);
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2016-05-13 08:46:14 +02:00
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}
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2016-03-30 02:45:18 +02:00
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std::array<u32, 1024> program_code;
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std::array<u32, 1024> swizzle_data;
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2016-12-18 01:06:04 +01:00
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/// Data private to ShaderEngines
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struct EngineData {
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2016-12-18 01:16:02 +01:00
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unsigned int entry_point;
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2016-12-18 01:06:04 +01:00
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/// Used by the JIT, points to a compiled shader object.
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const void* cached_shader = nullptr;
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} engine_data;
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2016-12-17 08:21:26 +01:00
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};
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class ShaderEngine {
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public:
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virtual ~ShaderEngine() = default;
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2016-03-30 02:45:18 +02:00
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/**
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2016-09-18 02:38:01 +02:00
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* Performs any shader unit setup that only needs to happen once per shader (as opposed to once
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2016-09-19 03:01:46 +02:00
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* per vertex, which would happen within the `Run` function).
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2016-03-30 02:45:18 +02:00
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*/
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2016-12-18 01:16:02 +01:00
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virtual void SetupBatch(ShaderSetup& setup, unsigned int entry_point) = 0;
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2016-03-30 02:45:18 +02:00
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/**
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2016-12-18 01:06:04 +01:00
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* Runs the currently setup shader.
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*
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* @param setup Shader engine state, must be setup with SetupBatch on each shader change.
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* @param state Shader unit state, must be setup with input data before each shader invocation.
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2016-03-30 02:45:18 +02:00
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*/
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2016-12-18 01:16:02 +01:00
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virtual void Run(const ShaderSetup& setup, UnitState& state) const = 0;
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2016-03-30 02:45:18 +02:00
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};
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2015-07-22 01:38:59 +02:00
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2016-12-17 08:21:26 +01:00
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// TODO(yuriks): Remove and make it non-global state somewhere
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ShaderEngine* GetEngine();
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2016-12-17 10:21:16 +01:00
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void Shutdown();
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2016-12-17 08:21:26 +01:00
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2015-07-22 01:38:59 +02:00
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} // namespace Shader
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} // namespace Pica
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