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arm_disasm: ARMv6 packing and sign-extend media instructions
PKH, SEL SXTAB, SXTAB16, SXTB, SXTB16, SXTH, SXTAH UXTAB, UXTAB16, UXTB, UXTB16, UXTH, UXTAH
This commit is contained in:
aroulin
parent
f48a89af8b
commit
47657a1817
@ -1,6 +1,7 @@
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// Copyright 2006 The Android Open Source Project
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#include <string>
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#include <unordered_set>
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#include "common/string_util.h"
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#include "core/arm/disassembler/arm_disasm.h"
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@ -66,10 +67,12 @@ static const char *opcode_names[] = {
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"mvn",
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"nop",
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"orr",
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"pkh",
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"pld",
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"rsb",
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"rsc",
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"sbc",
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"sel",
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"sev",
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"smlal",
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"smull",
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@ -88,10 +91,22 @@ static const char *opcode_names[] = {
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"swi",
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"swp",
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"swpb",
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"sxtab",
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"sxtab16",
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"sxtah",
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"sxtb",
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"sxtb16",
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"sxth",
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"teq",
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"tst",
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"umlal",
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"umull",
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"uxtab",
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"uxtab16",
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"uxtah",
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"uxtb",
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"uxtb16",
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"uxth",
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"wfe",
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"wfi",
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"yield",
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@ -236,8 +251,12 @@ std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
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case OP_WFI:
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case OP_YIELD:
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return DisassembleNoOperands(opcode, insn);
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case OP_PKH:
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return DisassemblePKH(insn);
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case OP_PLD:
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return DisassemblePLD(insn);
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case OP_SEL:
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return DisassembleSEL(insn);
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case OP_STC:
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return "stc";
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case OP_SWI:
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@ -245,6 +264,19 @@ std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
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case OP_SWP:
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case OP_SWPB:
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return DisassembleSWP(opcode, insn);
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case OP_SXTAB:
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case OP_SXTAB16:
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case OP_SXTAH:
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case OP_SXTB:
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case OP_SXTB16:
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case OP_SXTH:
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case OP_UXTAB:
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case OP_UXTAB16:
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case OP_UXTAH:
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case OP_UXTB:
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case OP_UXTB16:
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case OP_UXTH:
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return DisassembleXT(opcode, insn);
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case OP_UMLAL:
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case OP_UMULL:
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case OP_SMLAL:
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@ -684,6 +716,30 @@ std::string ARM_Disasm::DisassembleNoOperands(Opcode opcode, uint32_t insn)
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return Common::StringFromFormat("%s%s", opcode_names[opcode], cond_to_str(cond));
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}
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std::string ARM_Disasm::DisassemblePKH(uint32_t insn)
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{
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uint32_t cond = BITS(insn, 28, 31);
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uint32_t rn = BITS(insn, 16, 19);
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uint32_t rd = BITS(insn, 12, 15);
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uint32_t imm5 = BITS(insn, 7, 11);
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uint32_t tb = BIT(insn, 6);
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uint32_t rm = BITS(insn, 0, 3);
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std::string suffix = tb ? "tb" : "bt";
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std::string shift = "";
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if (tb && imm5 == 0)
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imm5 = 32;
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if (imm5 > 0) {
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shift = tb ? ", ASR" : ", LSL";
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shift += " #" + std::to_string(imm5);
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}
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return Common::StringFromFormat("pkh%s%s\tr%u, r%u, r%u%s", suffix.c_str(), cond_to_str(cond),
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rd, rn, rm, shift.c_str());
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}
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std::string ARM_Disasm::DisassemblePLD(uint32_t insn)
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{
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uint8_t is_reg = (insn >> 25) & 0x1;
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@ -737,6 +793,17 @@ std::string ARM_Disasm::DisassembleREX(Opcode opcode, uint32_t insn) {
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}
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}
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std::string ARM_Disasm::DisassembleSEL(uint32_t insn)
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{
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uint32_t cond = BITS(insn, 28, 31);
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uint32_t rn = BITS(insn, 16, 19);
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uint32_t rd = BITS(insn, 12, 15);
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uint32_t rm = BITS(insn, 0, 3);
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return Common::StringFromFormat("%s%s\tr%u, r%u, r%u", opcode_names[OP_SEL], cond_to_str(cond),
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rd, rn, rm);
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}
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std::string ARM_Disasm::DisassembleSWI(uint32_t insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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@ -756,6 +823,30 @@ std::string ARM_Disasm::DisassembleSWP(Opcode opcode, uint32_t insn)
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return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opname, cond_to_str(cond), rd, rm, rn);
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}
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std::string ARM_Disasm::DisassembleXT(Opcode opcode, uint32_t insn)
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{
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uint32_t cond = BITS(insn, 28, 31);
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uint32_t rn = BITS(insn, 16, 19);
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uint32_t rd = BITS(insn, 12, 15);
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uint32_t rotate = BITS(insn, 10, 11);
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uint32_t rm = BITS(insn, 0, 3);
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std::string rn_part = "";
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static std::unordered_set<Opcode, std::hash<int>> extend_with_add = {
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OP_SXTAB, OP_SXTAB16, OP_SXTAH,
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OP_UXTAB, OP_UXTAB16, OP_UXTAH
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};
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if (extend_with_add.find(opcode) != extend_with_add.end())
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rn_part = ", r" + std::to_string(rn);
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std::string rotate_part = "";
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if (rotate != 0)
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rotate_part = ", ROR #" + std::to_string(rotate << 3);
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return Common::StringFromFormat("%s%s\tr%u%s, r%u%s", opcode_names[opcode], cond_to_str(cond),
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rd, rn_part.c_str(), rm, rotate_part.c_str());
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}
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Opcode ARM_Disasm::Decode(uint32_t insn) {
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uint32_t bits27_26 = (insn >> 26) & 0x3;
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switch (bits27_26) {
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@ -818,7 +909,7 @@ Opcode ARM_Disasm::Decode01(uint32_t insn) {
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uint8_t is_reg = (insn >> 25) & 0x1;
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uint8_t bit4 = (insn >> 4) & 0x1;
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if (is_reg == 1 && bit4 == 1)
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return OP_UNDEFINED;
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return DecodeMedia(insn);
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uint8_t is_load = (insn >> 20) & 0x1;
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uint8_t is_byte = (insn >> 22) & 0x1;
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if ((insn & 0xfd70f000) == 0xf550f000) {
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@ -940,6 +1031,59 @@ Opcode ARM_Disasm::DecodeSyncPrimitive(uint32_t insn) {
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}
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}
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Opcode ARM_Disasm::DecodePackingSaturationReversal(uint32_t insn) {
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uint32_t op1 = BITS(insn, 20, 22);
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uint32_t a = BITS(insn, 16, 19);
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uint32_t op2 = BITS(insn, 5, 7);
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switch (op1) {
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case 0x0:
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if (BIT(op2, 0) == 0)
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return OP_PKH;
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if (op2 == 0x3 && a != 0xf)
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return OP_SXTAB16;
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if (op2 == 0x3 && a == 0xf)
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return OP_SXTB16;
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if (op2 == 0x5)
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return OP_SEL;
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break;
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case 0x2:
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if (op2 == 0x3 && a != 0xf)
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return OP_SXTAB;
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if (op2 == 0x3 && a == 0xf)
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return OP_SXTB;
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break;
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case 0x3:
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if (op2 == 0x3 && a != 0xf)
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return OP_SXTAH;
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if (op2 == 0x3 && a == 0xf)
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return OP_SXTH;
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break;
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case 0x4:
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if (op2 == 0x3 && a != 0xf)
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return OP_UXTAB16;
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if (op2 == 0x3 && a == 0xf)
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return OP_UXTB16;
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break;
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case 0x6:
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if (op2 == 0x3 && a != 0xf)
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return OP_UXTAB;
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if (op2 == 0x3 && a == 0xf)
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return OP_UXTB;
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break;
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case 0x7:
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if (op2 == 0x3 && a != 0xf)
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return OP_UXTAH;
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if (op2 == 0x3 && a == 0xf)
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return OP_UXTH;
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break;
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default:
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break;
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}
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return OP_UNDEFINED;
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}
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Opcode ARM_Disasm::DecodeMUL(uint32_t insn) {
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uint8_t bit24 = (insn >> 24) & 0x1;
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if (bit24 != 0) {
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@ -999,6 +1143,23 @@ Opcode ARM_Disasm::DecodeMSRImmAndHints(uint32_t insn) {
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return OP_MSR;
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}
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Opcode ARM_Disasm::DecodeMedia(uint32_t insn) {
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uint32_t op1 = BITS(insn, 20, 24);
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uint32_t rd = BITS(insn, 12, 15);
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uint32_t op2 = BITS(insn, 5, 7);
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uint32_t rn = BITS(insn, 0, 3);
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switch (BITS(op1, 3, 4)) {
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case 0x1:
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// Packing, unpacking, saturation, and reversal
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return DecodePackingSaturationReversal(insn);
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default:
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break;
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}
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return OP_UNDEFINED;
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}
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Opcode ARM_Disasm::DecodeLDRH(uint32_t insn) {
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uint8_t is_load = (insn >> 20) & 0x1;
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uint8_t bits_65 = (insn >> 5) & 0x3;
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@ -48,10 +48,12 @@ enum Opcode {
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OP_MVN,
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OP_NOP,
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OP_ORR,
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OP_PKH,
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OP_PLD,
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OP_RSB,
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OP_RSC,
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OP_SBC,
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OP_SEL,
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OP_SEV,
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OP_SMLAL,
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OP_SMULL,
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@ -70,10 +72,22 @@ enum Opcode {
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OP_SWI,
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OP_SWP,
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OP_SWPB,
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OP_SXTAB,
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OP_SXTAB16,
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OP_SXTAH,
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OP_SXTB,
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OP_SXTB16,
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OP_SXTH,
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OP_TEQ,
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OP_TST,
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OP_UMLAL,
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OP_UMULL,
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OP_UXTAB,
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OP_UXTAB16,
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OP_UXTAH,
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OP_UXTB,
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OP_UXTB16,
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OP_UXTH,
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OP_WFE,
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OP_WFI,
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OP_YIELD,
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@ -132,8 +146,10 @@ class ARM_Disasm {
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static Opcode Decode10(uint32_t insn);
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static Opcode Decode11(uint32_t insn);
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static Opcode DecodeSyncPrimitive(uint32_t insn);
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static Opcode DecodePackingSaturationReversal(uint32_t insn);
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static Opcode DecodeMUL(uint32_t insn);
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static Opcode DecodeMSRImmAndHints(uint32_t insn);
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static Opcode DecodeMedia(uint32_t insn);
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static Opcode DecodeLDRH(uint32_t insn);
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static Opcode DecodeALU(uint32_t insn);
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@ -152,8 +168,11 @@ class ARM_Disasm {
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static std::string DisassembleMRS(uint32_t insn);
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static std::string DisassembleMSR(uint32_t insn);
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static std::string DisassembleNoOperands(Opcode opcode, uint32_t insn);
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static std::string DisassemblePKH(uint32_t insn);
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static std::string DisassemblePLD(uint32_t insn);
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static std::string DisassembleREX(Opcode opcode, uint32_t insn);
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static std::string DisassembleSEL(uint32_t insn);
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static std::string DisassembleSWI(uint32_t insn);
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static std::string DisassembleSWP(Opcode opcode, uint32_t insn);
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static std::string DisassembleXT(Opcode opcode, uint32_t insn);
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};
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