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GPU: Add documentation.
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@ -84,11 +84,14 @@ struct Regs::Struct<Regs::FramebufferTop> {
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union {
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u32 active_fb;
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// 0: Use parameters ending with "1"
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// 1: Use parameters ending with "2"
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BitField<0, 1, u32> second_fb_active;
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};
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u32 pad2[5];
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// Distance between two pixel rows, in bytes
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u32 stride;
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u32 address_right1;
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@ -132,23 +135,32 @@ struct Regs::Struct<Regs::DisplayTransfer> {
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union {
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u32 flags;
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BitField< 0, 1, u32> flip_data;
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BitField< 0, 1, u32> flip_data; // flips input data horizontally (TODO) if true
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BitField< 8, 3, Format> input_format;
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BitField<12, 3, Format> output_format;
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BitField<16, 1, u32> output_tiled;
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BitField<16, 1, u32> output_tiled; // stores output in a tiled format
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};
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u32 unknown;
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// it seems that writing to this field triggers the display transfer
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u32 trigger;
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};
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static_assert(sizeof(Regs::Struct<Regs::DisplayTransfer>) == 0x1C, "Structure size and register block length don't match");
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template<>
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struct Regs::Struct<Regs::CommandProcessor> {
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// command list size
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u32 size;
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u32 pad0;
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// command list address
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u32 address;
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u32 pad1;
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// it seems that writing to this field triggers command list processing
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u32 trigger;
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};
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static_assert(sizeof(Regs::Struct<Regs::CommandProcessor>) == 0x14, "Structure size and register block length don't match");
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