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dyncom: Implement SMLAW
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@ -2369,7 +2369,25 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index)
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLALXY"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLAW"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst));
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smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->Ra = BITS(inst, 12, 15);
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inst_cream->Rm = BITS(inst, 8, 11);
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inst_cream->Rn = BITS(inst, 0, 3);
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inst_cream->Rd = BITS(inst, 16, 19);
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inst_cream->m = BIT(inst, 6);
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlald)(unsigned int inst, int index)
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{
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@ -5552,7 +5570,31 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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SMLALXY_INST:
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SMLAW_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
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const u32 rm_val = RM;
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const u32 rn_val = RN;
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const u32 ra_val = cpu->Reg[inst_cream->Ra];
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const bool high = (inst_cream->m == 1);
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const s16 operand2 = (high) ? ((rm_val >> 16) & 0xFFFF) : (rm_val & 0xFFFF);
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const s64 result = (s64)(s32)rn_val * (s64)(s32)operand2 + ((s64)(s32)ra_val << 16);
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RD = (result & (0xFFFFFFFFFFFFFFFFLL >> 15)) >> 16;
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if ((result >> 16) != (s32)RD)
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cpu->Cpsr |= (1 << 27);
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(smlad_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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SMLALD_INST:
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SMLSLD_INST:
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