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arm: Clean out armos.h and armmmu.h
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Lioncash
parent
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commit
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@ -18,19 +18,10 @@
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ARMMMU_H_
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#define _ARMMMU_H_
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#pragma once
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#define WORD_SHT 2
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#define WORD_SIZE (1<<WORD_SHT)
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/* The MMU is accessible with MCR and MRC operations to copro 15: */
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#define MMU_COPRO (15)
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/* Register numbers in the MMU: */
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typedef enum mmu_regnum_t
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// Register numbers in the MMU
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enum
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{
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MMU_ID = 0,
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MMU_CONTROL = 1,
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@ -44,94 +35,22 @@ typedef enum mmu_regnum_t
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MMU_TLB_LOCKDOWN = 10,
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MMU_PID = 13,
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/*MMU_V4 */
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// MMU_V4
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MMU_V4_CACHE_OPS = 7,
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MMU_V4_TLB_OPS = 8,
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/*MMU_V3 */
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// MMU_V3
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MMU_V3_FLUSH_TLB = 5,
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MMU_V3_FLUSH_TLB_ENTRY = 6,
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MMU_V3_FLUSH_CACHE = 7,
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/*MMU Intel SA-1100 */
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// MMU Intel SA-1100
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MMU_SA_RB_OPS = 9,
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MMU_SA_DEBUG = 14,
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MMU_SA_CP15_R15 = 15,
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//chy 2003-08-24
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/*Intel xscale CP15 */
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// Intel xscale CP15
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XSCALE_CP15_CACHE_TYPE = 0,
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XSCALE_CP15_AUX_CONTROL = 1,
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XSCALE_CP15_COPRO_ACCESS = 15,
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} mmu_regnum_t;
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/* Bits in the control register */
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#define CONTROL_MMU (1<<0)
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#define CONTROL_ALIGN_FAULT (1<<1)
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#define CONTROL_CACHE (1<<2)
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#define CONTROL_DATA_CACHE (1<<2)
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#define CONTROL_WRITE_BUFFER (1<<3)
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#define CONTROL_BIG_ENDIAN (1<<7)
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#define CONTROL_SYSTEM (1<<8)
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#define CONTROL_ROM (1<<9)
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#define CONTROL_UNDEFINED (1<<10)
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#define CONTROL_BRANCH_PREDICT (1<<11)
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#define CONTROL_INSTRUCTION_CACHE (1<<12)
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#define CONTROL_VECTOR (1<<13)
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#define CONTROL_RR (1<<14)
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#define CONTROL_L4 (1<<15)
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#define CONTROL_XP (1<<23)
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#define CONTROL_EE (1<<25)
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/*Macro defines for MMU state*/
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#define MMU_CTL (state->mmu.control)
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#define MMU_Enabled (state->mmu.control & CONTROL_MMU)
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#define MMU_Disabled (!(MMU_Enabled))
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#define MMU_Aligned (state->mmu.control & CONTROL_ALIGN_FAULT)
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#define MMU_ICacheEnabled (MMU_CTL & CONTROL_INSTRUCTION_CACHE)
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#define MMU_ICacheDisabled (!(MMU_ICacheDisabled))
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#define MMU_DCacheEnabled (MMU_CTL & CONTROL_DATA_CACHE)
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#define MMU_DCacheDisabled (!(MMU_DCacheEnabled))
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#define MMU_CacheEnabled (MMU_CTL & CONTROL_CACHE)
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#define MMU_CacheDisabled (!(MMU_CacheEnabled))
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#define MMU_WBEnabled (MMU_CTL & CONTROL_WRITE_BUFFER)
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#define MMU_WBDisabled (!(MMU_WBEnabled))
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/*virt_addr exchange according to CP15.R13(process id virtul mapping)*/
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#define PID_VA_MAP_MASK 0xfe000000
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//#define mmu_pid_va_map(va) ({\
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// ARMword ret; \
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// if ((va) & PID_VA_MAP_MASK)\
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// ret = (va); \
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// else \
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// ret = ((va) | (state->mmu.process_id & PID_VA_MAP_MASK));\
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// ret;\
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//})
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#define mmu_pid_va_map(va) ((va) & PID_VA_MAP_MASK) ? (va) : ((va) | (state->mmu.process_id & PID_VA_MAP_MASK))
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/* FS[3:0] in the fault status register: */
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typedef enum fault_t
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{
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NO_FAULT = 0x0,
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ALIGNMENT_FAULT = 0x1,
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SECTION_TRANSLATION_FAULT = 0x5,
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PAGE_TRANSLATION_FAULT = 0x7,
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SECTION_DOMAIN_FAULT = 0x9,
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PAGE_DOMAIN_FAULT = 0xB,
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SECTION_PERMISSION_FAULT = 0xD,
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SUBPAGE_PERMISSION_FAULT = 0xF,
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/* defined by skyeye */
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TLB_READ_MISS = 0x30,
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TLB_WRITE_MISS = 0x40,
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} fault_t;
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#endif /* _ARMMMU_H_ */
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};
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@ -13,26 +13,12 @@
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <stdint.h>
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#if FAST_MEMORY
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/* in user mode, mmap_base will be on initial brk,
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set at the first mmap request */
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#define mmap_base -1
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#else
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#define mmap_base 0x50000000
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#endif
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static long mmap_next_base = mmap_base;
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//static mmap_area_t* new_mmap_area(int sim_addr, int len);
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static char mmap_mem_write(short size, int addr, uint32_t value);
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static char mmap_mem_read(short size, int addr, uint32_t * value);
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/***************************************************************************\
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* SWI numbers *
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\***************************************************************************/
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//
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// SWI Numbers
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//
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#define SWI_Syscall 0x0
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#define SWI_Exit 0x1
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@ -58,15 +44,6 @@ static char mmap_mem_read(short size, int addr, uint32_t * value);
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#define SWI_ExitGroup 0xf8
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#if 0
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#define SWI_Time 0xd
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#define SWI_Clock 0x61
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#define SWI_Time 0x63
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#define SWI_Remove 0x64
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#define SWI_Rename 0x65
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#define SWI_Flen 0x6c
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#endif
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#define SWI_Uname 0x7a
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#define SWI_Fcntl 0xdd
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#define SWI_Fstat64 0xc5
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@ -75,57 +52,3 @@ static char mmap_mem_read(short size, int addr, uint32_t * value);
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#define SWI_Breakpoint 0x180000 /* see gdb's tm-arm.h */
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/***************************************************************************\
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* SWI structures *
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\***************************************************************************/
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/* Arm binaries (for now) only support 32 bit, and expect to receive
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32-bit compliant structure in return of a systen call. Because
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we use host system calls to emulate system calls, the returned
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structure can be 32-bit compliant or 64-bit compliant, depending
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on the OS running skyeye. Therefore, we need a fixed size structure
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adapted to arm.*/
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/* Borrowed from qemu */
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struct target_stat64 {
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unsigned short st_dev;
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unsigned char __pad0[10];
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uint32_t __st_ino;
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unsigned int st_mode;
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unsigned int st_nlink;
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uint32_t st_uid;
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uint32_t st_gid;
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unsigned short st_rdev;
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unsigned char __pad3[10];
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unsigned char __pad31[4];
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long long st_size;
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uint32_t st_blksize;
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unsigned char __pad32[4];
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uint32_t st_blocks;
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uint32_t __pad4;
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uint32_t st32_atime;
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uint32_t __pad5;
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uint32_t st32_mtime;
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uint32_t __pad6;
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uint32_t st32_ctime;
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uint32_t __pad7;
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unsigned long long st_ino;
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};// __attribute__((packed));
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struct target_tms32 {
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uint32_t tms_utime;
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uint32_t tms_stime;
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uint32_t tms_cutime;
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uint32_t tms_cstime;
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};
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struct target_timeval32 {
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uint32_t tv_sec; /* seconds */
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uint32_t tv_usec; /* microseconds */
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};
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struct target_timezone32 {
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int32_t tz_minuteswest; /* minutes west of Greenwich */
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int32_t tz_dsttime; /* type of DST correction */
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};
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