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Merge pull request #516 from lioncash/cleanup

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ARM: More cleanup.
This commit is contained in:
bunnei 2015-01-30 17:11:12 -05:00
commit dbff4e5e12
14 changed files with 36 additions and 370 deletions
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2
src/core/CMakeLists.txt
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@ -110,13 +110,11 @@ set(HEADERS
arm/dyncom/arm_dyncom_thumb.h arm/dyncom/arm_dyncom_thumb.h
arm/interpreter/arm_interpreter.h arm/interpreter/arm_interpreter.h
arm/skyeye_common/arm_regformat.h arm/skyeye_common/arm_regformat.h
arm/skyeye_common/armcpu.h
arm/skyeye_common/armdefs.h arm/skyeye_common/armdefs.h
arm/skyeye_common/armemu.h arm/skyeye_common/armemu.h
arm/skyeye_common/armmmu.h arm/skyeye_common/armmmu.h
arm/skyeye_common/armos.h arm/skyeye_common/armos.h
arm/skyeye_common/skyeye_defs.h arm/skyeye_common/skyeye_defs.h
arm/skyeye_common/skyeye_types.h
arm/skyeye_common/vfp/asm_vfp.h arm/skyeye_common/vfp/asm_vfp.h
arm/skyeye_common/vfp/vfp.h arm/skyeye_common/vfp/vfp.h
arm/skyeye_common/vfp/vfp_helper.h arm/skyeye_common/vfp/vfp_helper.h

1
src/core/arm/dyncom/arm_dyncom.cpp
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@ -2,7 +2,6 @@
// Licensed under GPLv2 or any later version // Licensed under GPLv2 or any later version
// Refer to the license.txt file included. // Refer to the license.txt file included.
#include "core/arm/skyeye_common/armcpu.h"
#include "core/arm/skyeye_common/armemu.h" #include "core/arm/skyeye_common/armemu.h"
#include "core/arm/skyeye_common/vfp/vfp.h" #include "core/arm/skyeye_common/vfp/vfp.h"

45
src/core/arm/dyncom/arm_dyncom_dec.h
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@ -6,14 +6,6 @@
#define BITS(a,b) ((instr >> (a)) & ((1 << (1+(b)-(a)))-1)) #define BITS(a,b) ((instr >> (a)) & ((1 << (1+(b)-(a)))-1))
#define BIT(n) ((instr >> (n)) & 1) #define BIT(n) ((instr >> (n)) & 1)
#define BAD do { printf("meet BAD at %s, instr is %x\n", __FUNCTION__, instr ); } while(0);
#define ptr_N cpu->ptr_N
#define ptr_Z cpu->ptr_Z
#define ptr_C cpu->ptr_C
#define ptr_V cpu->ptr_V
#define ptr_I cpu->ptr_I
#define ptr_T cpu->ptr_T
#define ptr_CPSR cpu->ptr_gpr[16]
// For MUL instructions // For MUL instructions
#define RDHi ((instr >> 16) & 0xF) #define RDHi ((instr >> 16) & 0xF)
@ -49,24 +41,6 @@
#define SBIT BIT(20) #define SBIT BIT(20)
#define DESTReg (BITS (12, 15)) #define DESTReg (BITS (12, 15))
// They are in unused state, give a corrent value when using
#define IS_V5E 0
#define IS_V5 0
#define IS_V6 0
#define LHSReg 0
// Temp define the using the pc reg need implement a flow
#define STORE_CHECK_RD_PC ADD(R(RD), CONST(INSTR_SIZE * 2))
#define OPERAND operand(cpu,instr,bb,NULL)
#define SCO_OPERAND(sco) operand(cpu,instr,bb,sco)
#define BOPERAND boperand(instr)
#define CHECK_RN_PC (RN == 15 ? ADD(AND(R(RN), CONST(~0x1)), CONST(INSTR_SIZE * 2)) : R(RN))
#define CHECK_RN_PC_WA (RN == 15 ? ADD(AND(R(RN), CONST(~0x3)), CONST(INSTR_SIZE * 2)) : R(RN))
#define GET_USER_MODE() (OR(ICMP_EQ(R(MODE_REG), CONST(USER32MODE)), ICMP_EQ(R(MODE_REG), CONST(SYSTEM32MODE))))
int decode_arm_instr(uint32_t instr, int32_t *idx); int decode_arm_instr(uint32_t instr, int32_t *idx);
enum DECODE_STATUS { enum DECODE_STATUS {
@ -83,23 +57,8 @@ struct instruction_set_encoding_item {
typedef struct instruction_set_encoding_item ISEITEM; typedef struct instruction_set_encoding_item ISEITEM;
#define RECORD_WB(value, flag) { cpu->dyncom_engine->wb_value = value;cpu->dyncom_engine->wb_flag = flag; } // ARM versions
#define INIT_WB(wb_value, wb_flag) RECORD_WB(wb_value, wb_flag) enum {
#define EXECUTE_WB(base_reg) { if(cpu->dyncom_engine->wb_flag) LET(base_reg, cpu->dyncom_engine->wb_value); }
inline int get_reg_count(uint32_t instr) {
int i = BITS(0, 15);
int count = 0;
while (i) {
if (i & 1)
count++;
i = i >> 1;
}
return count;
}
enum ARMVER {
INVALID = 0, INVALID = 0,
ARMALL, ARMALL,
ARMV4, ARMV4,

7
src/core/arm/dyncom/arm_dyncom_run.h
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@ -16,10 +16,7 @@
* *
*/ */
#ifndef __ARM_DYNCOM_RUN__ #pragma once
#define __ARM_DYNCOM_RUN__
#include "core/arm/skyeye_common/skyeye_types.h"
void switch_mode(arm_core_t *core, uint32_t mode); void switch_mode(arm_core_t *core, uint32_t mode);
@ -51,5 +48,3 @@ static inline addr_t CHECK_READ_REG15_WA(arm_core_t* core, int Rn) {
static inline u32 CHECK_READ_REG15(arm_core_t* core, int Rn) { static inline u32 CHECK_READ_REG15(arm_core_t* core, int Rn) {
return (Rn == 15)? ((core->Reg[15] & ~0x1) + GET_INST_SIZE(core) * 2) : core->Reg[Rn]; return (Rn == 15)? ((core->Reg[15] & ~0x1) + GET_INST_SIZE(core) * 2) : core->Reg[Rn];
} }
#endif

6
src/core/arm/dyncom/arm_dyncom_thumb.h
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@ -24,11 +24,9 @@
* @date 2011-11-07 * @date 2011-11-07
*/ */
#ifndef __ARM_DYNCOM_THUMB_H__ #pragma once
#define __ARM_DYNCOM_THUMB_H__
#include "core/arm/skyeye_common/armdefs.h" #include "core/arm/skyeye_common/armdefs.h"
#include "core/arm/skyeye_common/skyeye_types.h"
enum tdstate { enum tdstate {
t_undefined, // Undefined Thumb instruction t_undefined, // Undefined Thumb instruction
@ -47,5 +45,3 @@ static inline u32 get_thumb_instr(u32 instr, addr_t pc) {
tinstr = instr & 0xFFFF; tinstr = instr & 0xFFFF;
return tinstr; return tinstr;
} }
#endif

11
src/core/arm/skyeye_common/arm_regformat.h
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@ -1,7 +1,6 @@
#ifndef __ARM_REGFORMAT_H__ #pragma once
#define __ARM_REGFORMAT_H__
enum arm_regno{ enum {
R0 = 0, R0 = 0,
R1, R1,
R2, R2,
@ -20,7 +19,7 @@ enum arm_regno{
R15, //PC, R15, //PC,
CPSR_REG, CPSR_REG,
SPSR_REG, SPSR_REG,
#if 1
PHYS_PC, PHYS_PC,
R13_USR, R13_USR,
R14_USR, R14_USR,
@ -95,11 +94,9 @@ enum arm_regno{
VFP_FPSID = VFP_BASE, VFP_FPSID = VFP_BASE,
VFP_FPSCR, VFP_FPSCR,
VFP_FPEXC, VFP_FPEXC,
#endif
MAX_REG_NUM, MAX_REG_NUM,
}; };
#define CP15(idx) (idx - CP15_BASE) #define CP15(idx) (idx - CP15_BASE)
#define VFP_OFFSET(x) (x - VFP_BASE) #define VFP_OFFSET(x) (x - VFP_BASE)
#endif

78
src/core/arm/skyeye_common/armcpu.h
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@ -1,78 +0,0 @@
/*
* arm
* armcpu.h
*
* Copyright (C) 2003, 2004 Sebastian Biallas (sb@biallas.net)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ARM_CPU_H__
#define __ARM_CPU_H__
#include <stddef.h>
#include <stdio.h>
#include "core/arm/skyeye_common/armdefs.h"
typedef struct ARM_CPU_State_s {
ARMul_State * core;
uint32_t core_num;
/* The core id that boot from
*/
uint32_t boot_core_id;
}ARM_CPU_State;
//static ARM_CPU_State* get_current_cpu(){
// machine_config_t* mach = get_current_mach();
// /* Casting a conf_obj_t to ARM_CPU_State type */
// ARM_CPU_State* cpu = (ARM_CPU_State*)mach->cpu_data->obj;
//
// return cpu;
//}
/**
* @brief Get the core instance boot from
*
* @return
*/
//static ARMul_State* get_boot_core(){
// ARM_CPU_State* cpu = get_current_cpu();
// return &cpu->core[cpu->boot_core_id];
//}
/**
* @brief Get the instance of running core
*
* @return the core instance
*/
//static ARMul_State* get_current_core(){
// /* Casting a conf_obj_t to ARM_CPU_State type */
// int id = Common::CurrentThreadId();
// /* If thread is not in running mode, we should give the boot core */
// if(get_thread_state(id) != Running_state){
// return get_boot_core();
// }
// /* Judge if we are running in paralell or sequenial */
// if(thread_exist(id)){
// conf_object_t* conf_obj = get_current_exec_priv(id);
// return (ARMul_State*)get_cast_conf_obj(conf_obj, "arm_core_t");
// }
//
// return NULL;
//}
#define CURRENT_CORE get_current_core()
#endif

9
src/core/arm/skyeye_common/armemu.h
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@ -14,14 +14,10 @@
You should have received a copy of the GNU General Public License You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef __ARMEMU_H__
#define __ARMEMU_H__
#pragma once
#include "core/arm/skyeye_common/armdefs.h" #include "core/arm/skyeye_common/armdefs.h"
//#include "skyeye.h"
//extern ARMword isize;
/* Shift Opcodes. */ /* Shift Opcodes. */
#define LSL 0 #define LSL 0
@ -625,6 +621,3 @@ extern unsigned DSPCDP5 (ARMul_State *, unsigned, ARMword);
extern unsigned DSPMCR6 (ARMul_State *, unsigned, ARMword, ARMword); extern unsigned DSPMCR6 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPMRC6 (ARMul_State *, unsigned, ARMword, ARMword *); extern unsigned DSPMRC6 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned DSPCDP6 (ARMul_State *, unsigned, ARMword); extern unsigned DSPCDP6 (ARMul_State *, unsigned, ARMword);
#endif

99
src/core/arm/skyeye_common/armmmu.h
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@ -18,19 +18,10 @@
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/ */
#ifndef _ARMMMU_H_ #pragma once
#define _ARMMMU_H_
// Register numbers in the MMU
#define WORD_SHT 2 enum
#define WORD_SIZE (1<<WORD_SHT)
/* The MMU is accessible with MCR and MRC operations to copro 15: */
#define MMU_COPRO (15)
/* Register numbers in the MMU: */
typedef enum mmu_regnum_t
{ {
MMU_ID = 0, MMU_ID = 0,
MMU_CONTROL = 1, MMU_CONTROL = 1,
@ -44,94 +35,22 @@ typedef enum mmu_regnum_t
MMU_TLB_LOCKDOWN = 10, MMU_TLB_LOCKDOWN = 10,
MMU_PID = 13, MMU_PID = 13,
/*MMU_V4 */ // MMU_V4
MMU_V4_CACHE_OPS = 7, MMU_V4_CACHE_OPS = 7,
MMU_V4_TLB_OPS = 8, MMU_V4_TLB_OPS = 8,
/*MMU_V3 */ // MMU_V3
MMU_V3_FLUSH_TLB = 5, MMU_V3_FLUSH_TLB = 5,
MMU_V3_FLUSH_TLB_ENTRY = 6, MMU_V3_FLUSH_TLB_ENTRY = 6,
MMU_V3_FLUSH_CACHE = 7, MMU_V3_FLUSH_CACHE = 7,
/*MMU Intel SA-1100 */ // MMU Intel SA-1100
MMU_SA_RB_OPS = 9, MMU_SA_RB_OPS = 9,
MMU_SA_DEBUG = 14, MMU_SA_DEBUG = 14,
MMU_SA_CP15_R15 = 15, MMU_SA_CP15_R15 = 15,
//chy 2003-08-24
/*Intel xscale CP15 */ // Intel xscale CP15
XSCALE_CP15_CACHE_TYPE = 0, XSCALE_CP15_CACHE_TYPE = 0,
XSCALE_CP15_AUX_CONTROL = 1, XSCALE_CP15_AUX_CONTROL = 1,
XSCALE_CP15_COPRO_ACCESS = 15, XSCALE_CP15_COPRO_ACCESS = 15,
};
} mmu_regnum_t;
/* Bits in the control register */
#define CONTROL_MMU (1<<0)
#define CONTROL_ALIGN_FAULT (1<<1)
#define CONTROL_CACHE (1<<2)
#define CONTROL_DATA_CACHE (1<<2)
#define CONTROL_WRITE_BUFFER (1<<3)
#define CONTROL_BIG_ENDIAN (1<<7)
#define CONTROL_SYSTEM (1<<8)
#define CONTROL_ROM (1<<9)
#define CONTROL_UNDEFINED (1<<10)
#define CONTROL_BRANCH_PREDICT (1<<11)
#define CONTROL_INSTRUCTION_CACHE (1<<12)
#define CONTROL_VECTOR (1<<13)
#define CONTROL_RR (1<<14)
#define CONTROL_L4 (1<<15)
#define CONTROL_XP (1<<23)
#define CONTROL_EE (1<<25)
/*Macro defines for MMU state*/
#define MMU_CTL (state->mmu.control)
#define MMU_Enabled (state->mmu.control & CONTROL_MMU)
#define MMU_Disabled (!(MMU_Enabled))
#define MMU_Aligned (state->mmu.control & CONTROL_ALIGN_FAULT)
#define MMU_ICacheEnabled (MMU_CTL & CONTROL_INSTRUCTION_CACHE)
#define MMU_ICacheDisabled (!(MMU_ICacheDisabled))
#define MMU_DCacheEnabled (MMU_CTL & CONTROL_DATA_CACHE)
#define MMU_DCacheDisabled (!(MMU_DCacheEnabled))
#define MMU_CacheEnabled (MMU_CTL & CONTROL_CACHE)
#define MMU_CacheDisabled (!(MMU_CacheEnabled))
#define MMU_WBEnabled (MMU_CTL & CONTROL_WRITE_BUFFER)
#define MMU_WBDisabled (!(MMU_WBEnabled))
/*virt_addr exchange according to CP15.R13(process id virtul mapping)*/
#define PID_VA_MAP_MASK 0xfe000000
//#define mmu_pid_va_map(va) ({\
// ARMword ret; \
// if ((va) & PID_VA_MAP_MASK)\
// ret = (va); \
// else \
// ret = ((va) | (state->mmu.process_id & PID_VA_MAP_MASK));\
// ret;\
//})
#define mmu_pid_va_map(va) ((va) & PID_VA_MAP_MASK) ? (va) : ((va) | (state->mmu.process_id & PID_VA_MAP_MASK))
/* FS[3:0] in the fault status register: */
typedef enum fault_t
{
NO_FAULT = 0x0,
ALIGNMENT_FAULT = 0x1,
SECTION_TRANSLATION_FAULT = 0x5,
PAGE_TRANSLATION_FAULT = 0x7,
SECTION_DOMAIN_FAULT = 0x9,
PAGE_DOMAIN_FAULT = 0xB,
SECTION_PERMISSION_FAULT = 0xD,
SUBPAGE_PERMISSION_FAULT = 0xF,
/* defined by skyeye */
TLB_READ_MISS = 0x30,
TLB_WRITE_MISS = 0x40,
} fault_t;
#endif /* _ARMMMU_H_ */

87
src/core/arm/skyeye_common/armos.h
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@ -13,26 +13,12 @@
You should have received a copy of the GNU General Public License You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <stdint.h> //
// SWI Numbers
#if FAST_MEMORY //
/* in user mode, mmap_base will be on initial brk,
set at the first mmap request */
#define mmap_base -1
#else
#define mmap_base 0x50000000
#endif
static long mmap_next_base = mmap_base;
//static mmap_area_t* new_mmap_area(int sim_addr, int len);
static char mmap_mem_write(short size, int addr, uint32_t value);
static char mmap_mem_read(short size, int addr, uint32_t * value);
/***************************************************************************\
* SWI numbers *
\***************************************************************************/
#define SWI_Syscall 0x0 #define SWI_Syscall 0x0
#define SWI_Exit 0x1 #define SWI_Exit 0x1
@ -58,15 +44,6 @@ static char mmap_mem_read(short size, int addr, uint32_t * value);
#define SWI_ExitGroup 0xf8 #define SWI_ExitGroup 0xf8
#if 0
#define SWI_Time 0xd
#define SWI_Clock 0x61
#define SWI_Time 0x63
#define SWI_Remove 0x64
#define SWI_Rename 0x65
#define SWI_Flen 0x6c
#endif
#define SWI_Uname 0x7a #define SWI_Uname 0x7a
#define SWI_Fcntl 0xdd #define SWI_Fcntl 0xdd
#define SWI_Fstat64 0xc5 #define SWI_Fstat64 0xc5
@ -75,57 +52,3 @@ static char mmap_mem_read(short size, int addr, uint32_t * value);
#define SWI_Breakpoint 0x180000 /* see gdb's tm-arm.h */ #define SWI_Breakpoint 0x180000 /* see gdb's tm-arm.h */
/***************************************************************************\
* SWI structures *
\***************************************************************************/
/* Arm binaries (for now) only support 32 bit, and expect to receive
32-bit compliant structure in return of a systen call. Because
we use host system calls to emulate system calls, the returned
structure can be 32-bit compliant or 64-bit compliant, depending
on the OS running skyeye. Therefore, we need a fixed size structure
adapted to arm.*/
/* Borrowed from qemu */
struct target_stat64 {
unsigned short st_dev;
unsigned char __pad0[10];
uint32_t __st_ino;
unsigned int st_mode;
unsigned int st_nlink;
uint32_t st_uid;
uint32_t st_gid;
unsigned short st_rdev;
unsigned char __pad3[10];
unsigned char __pad31[4];
long long st_size;
uint32_t st_blksize;
unsigned char __pad32[4];
uint32_t st_blocks;
uint32_t __pad4;
uint32_t st32_atime;
uint32_t __pad5;
uint32_t st32_mtime;
uint32_t __pad6;
uint32_t st32_ctime;
uint32_t __pad7;
unsigned long long st_ino;
};// __attribute__((packed));
struct target_tms32 {
uint32_t tms_utime;
uint32_t tms_stime;
uint32_t tms_cutime;
uint32_t tms_cstime;
};
struct target_timeval32 {
uint32_t tv_sec; /* seconds */
uint32_t tv_usec; /* microseconds */
};
struct target_timezone32 {
int32_t tz_minuteswest; /* minutes west of Greenwich */
int32_t tz_dsttime; /* type of DST correction */
};

31
src/core/arm/skyeye_common/skyeye_types.h
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@ -1,31 +0,0 @@
/*
skyeye_types.h - some data types definition for skyeye debugger
Copyright (C) 2003 Skyeye Develop Group
for help please send mail to <skyeye-developer@lists.sf.linuxforum.net>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* 12/16/2006 Michael.Kang <blackfin.kang@gmail.com>
*/
#pragma once
#include <cstdint>
typedef uint32_t address_t;
typedef uint32_t physical_address_t;
typedef uint32_t generic_address_t;

2
src/core/arm/skyeye_common/vfp/asm_vfp.h
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@ -5,6 +5,8 @@
* First, the standard VFP set. * First, the standard VFP set.
*/ */
#pragma once
#define FPSID cr0 #define FPSID cr0
#define FPSCR cr1 #define FPSCR cr1
#define MVFR1 cr6 #define MVFR1 cr6

5
src/core/arm/skyeye_common/vfp/vfp.h
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@ -18,8 +18,7 @@
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/ */
#ifndef __VFP_H__ #pragma once
#define __VFP_H__
#include "core/arm/skyeye_common/vfp/vfp_helper.h" /* for references to cdp SoftFloat functions */ #include "core/arm/skyeye_common/vfp/vfp_helper.h" /* for references to cdp SoftFloat functions */
@ -109,5 +108,3 @@ int VLDR(ARMul_State * state, int type, ARMword instr, ARMword value);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif

5
src/core/arm/skyeye_common/vfp/vfp_helper.h
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@ -30,8 +30,7 @@
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#ifndef __VFP_HELPER_H__ #pragma once
#define __VFP_HELPER_H__
/* Custom edit */ /* Custom edit */
@ -536,5 +535,3 @@ u32 vfp_double_normaliseroundintern(ARMul_State* state, struct vfp_double *vd, u
u32 vfp_double_multiply(struct vfp_double *vdd, struct vfp_double *vdn, struct vfp_double *vdm, u32 fpscr); u32 vfp_double_multiply(struct vfp_double *vdd, struct vfp_double *vdn, struct vfp_double *vdm, u32 fpscr);
u32 vfp_double_add(struct vfp_double *vdd, struct vfp_double *vdn, struct vfp_double *vdm, u32 fpscr); u32 vfp_double_add(struct vfp_double *vdd, struct vfp_double *vdn, struct vfp_double *vdm, u32 fpscr);
u32 vfp_double_fcvtsinterncutting(ARMul_State* state, int sd, struct vfp_double* dm, u32 fpscr); u32 vfp_double_fcvtsinterncutting(ARMul_State* state, int sd, struct vfp_double* dm, u32 fpscr);
#endif