mirror of
https://github.com/Lime3DS/Lime3DS.git
synced 2024-11-13 13:35:14 +01:00
1345 lines
39 KiB
C++
1345 lines
39 KiB
C++
// Copyright 2006 The Android Open Source Project
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#include <string>
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#include <unordered_set>
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#include "common/common_types.h"
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#include "common/string_util.h"
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#include "core/arm/disassembler/arm_disasm.h"
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#include "core/arm/skyeye_common/armsupp.h"
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static const char* cond_names[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
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"hi", "ls", "ge", "lt", "gt", "le", "", "RESERVED"};
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static const char* opcode_names[] = {
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"invalid", "undefined", "adc", "add", "and", "b", "bl", "bic",
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"bkpt", "blx", "bx", "cdp", "clrex", "clz", "cmn", "cmp",
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"eor", "ldc", "ldm", "ldr", "ldrb", "ldrbt", "ldrex", "ldrexb",
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"ldrexd", "ldrexh", "ldrh", "ldrsb", "ldrsh", "ldrt", "mcr", "mla",
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"mov", "mrc", "mrs", "msr", "mul", "mvn", "nop", "orr",
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"pkh", "pld", "qadd16", "qadd8", "qasx", "qsax", "qsub16", "qsub8",
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"rev", "rev16", "revsh", "rsb", "rsc", "sadd16", "sadd8", "sasx",
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"sbc", "sel", "sev", "shadd16", "shadd8", "shasx", "shsax", "shsub16",
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"shsub8", "smlad", "smlal", "smlald", "smlsd", "smlsld", "smmla", "smmls",
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"smmul", "smuad", "smull", "smusd", "ssat", "ssat16", "ssax", "ssub16",
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"ssub8", "stc", "stm", "str", "strb", "strbt", "strex", "strexb",
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"strexd", "strexh", "strh", "strt", "sub", "swi", "swp", "swpb",
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"sxtab", "sxtab16", "sxtah", "sxtb", "sxtb16", "sxth", "teq", "tst",
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"uadd16", "uadd8", "uasx", "uhadd16", "uhadd8", "uhasx", "uhsax", "uhsub16",
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"uhsub8", "umlal", "umull", "uqadd16", "uqadd8", "uqasx", "uqsax", "uqsub16",
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"uqsub8", "usad8", "usada8", "usat", "usat16", "usax", "usub16", "usub8",
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"uxtab", "uxtab16", "uxtah", "uxtb", "uxtb16", "uxth", "wfe", "wfi",
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"yield",
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"undefined", "adc", "add", "and", "asr", "b", "bic", "bkpt",
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"bl", "blx", "bx", "cmn", "cmp", "eor", "ldmia", "ldr",
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"ldrb", "ldrh", "ldrsb", "ldrsh", "lsl", "lsr", "mov", "mul",
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"mvn", "neg", "orr", "pop", "push", "ror", "sbc", "stmia",
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"str", "strb", "strh", "sub", "swi", "tst",
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nullptr};
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// Indexed by the shift type (bits 6-5)
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static const char* shift_names[] = {"LSL", "LSR", "ASR", "ROR"};
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static const char* cond_to_str(u32 cond) {
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return cond_names[cond];
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}
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std::string ARM_Disasm::Disassemble(u32 addr, u32 insn) {
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Opcode opcode = Decode(insn);
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switch (opcode) {
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case OP_INVALID:
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return "Invalid";
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case OP_UNDEFINED:
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return "Undefined";
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case OP_ADC:
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case OP_ADD:
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case OP_AND:
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case OP_BIC:
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case OP_CMN:
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case OP_CMP:
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case OP_EOR:
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case OP_MOV:
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case OP_MVN:
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case OP_ORR:
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case OP_RSB:
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case OP_RSC:
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case OP_SBC:
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case OP_SUB:
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case OP_TEQ:
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case OP_TST:
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return DisassembleALU(opcode, insn);
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case OP_B:
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case OP_BL:
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return DisassembleBranch(addr, opcode, insn);
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case OP_BKPT:
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return DisassembleBKPT(insn);
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case OP_BLX:
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// not supported yet
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break;
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case OP_BX:
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return DisassembleBX(insn);
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case OP_CDP:
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return "cdp";
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case OP_CLREX:
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return "clrex";
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case OP_CLZ:
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return DisassembleCLZ(insn);
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case OP_LDC:
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return "ldc";
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case OP_LDM:
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case OP_STM:
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return DisassembleMemblock(opcode, insn);
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case OP_LDR:
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case OP_LDRB:
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case OP_LDRBT:
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case OP_LDRT:
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case OP_STR:
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case OP_STRB:
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case OP_STRBT:
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case OP_STRT:
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return DisassembleMem(insn);
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case OP_LDREX:
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case OP_LDREXB:
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case OP_LDREXD:
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case OP_LDREXH:
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case OP_STREX:
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case OP_STREXB:
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case OP_STREXD:
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case OP_STREXH:
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return DisassembleREX(opcode, insn);
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case OP_LDRH:
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case OP_LDRSB:
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case OP_LDRSH:
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case OP_STRH:
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return DisassembleMemHalf(insn);
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case OP_MCR:
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case OP_MRC:
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return DisassembleMCR(opcode, insn);
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case OP_MLA:
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return DisassembleMLA(opcode, insn);
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case OP_MRS:
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return DisassembleMRS(insn);
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case OP_MSR:
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return DisassembleMSR(insn);
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case OP_MUL:
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return DisassembleMUL(opcode, insn);
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case OP_NOP:
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case OP_SEV:
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case OP_WFE:
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case OP_WFI:
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case OP_YIELD:
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return DisassembleNoOperands(opcode, insn);
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case OP_PKH:
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return DisassemblePKH(insn);
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case OP_PLD:
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return DisassemblePLD(insn);
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case OP_QADD16:
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case OP_QADD8:
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case OP_QASX:
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case OP_QSAX:
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case OP_QSUB16:
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case OP_QSUB8:
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case OP_SADD16:
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case OP_SADD8:
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case OP_SASX:
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case OP_SHADD16:
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case OP_SHADD8:
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case OP_SHASX:
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case OP_SHSAX:
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case OP_SHSUB16:
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case OP_SHSUB8:
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case OP_SSAX:
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case OP_SSUB16:
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case OP_SSUB8:
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case OP_UADD16:
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case OP_UADD8:
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case OP_UASX:
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case OP_UHADD16:
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case OP_UHADD8:
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case OP_UHASX:
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case OP_UHSAX:
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case OP_UHSUB16:
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case OP_UHSUB8:
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case OP_UQADD16:
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case OP_UQADD8:
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case OP_UQASX:
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case OP_UQSAX:
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case OP_UQSUB16:
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case OP_UQSUB8:
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case OP_USAX:
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case OP_USUB16:
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case OP_USUB8:
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return DisassembleParallelAddSub(opcode, insn);
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case OP_REV:
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case OP_REV16:
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case OP_REVSH:
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return DisassembleREV(opcode, insn);
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case OP_SEL:
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return DisassembleSEL(insn);
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case OP_SMLAD:
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case OP_SMLALD:
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case OP_SMLSD:
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case OP_SMLSLD:
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case OP_SMMLA:
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case OP_SMMLS:
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case OP_SMMUL:
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case OP_SMUAD:
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case OP_SMUSD:
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case OP_USAD8:
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case OP_USADA8:
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return DisassembleMediaMulDiv(opcode, insn);
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case OP_SSAT:
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case OP_SSAT16:
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case OP_USAT:
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case OP_USAT16:
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return DisassembleSAT(opcode, insn);
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case OP_STC:
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return "stc";
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case OP_SWI:
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return DisassembleSWI(insn);
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case OP_SWP:
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case OP_SWPB:
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return DisassembleSWP(opcode, insn);
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case OP_SXTAB:
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case OP_SXTAB16:
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case OP_SXTAH:
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case OP_SXTB:
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case OP_SXTB16:
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case OP_SXTH:
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case OP_UXTAB:
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case OP_UXTAB16:
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case OP_UXTAH:
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case OP_UXTB:
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case OP_UXTB16:
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case OP_UXTH:
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return DisassembleXT(opcode, insn);
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case OP_UMLAL:
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case OP_UMULL:
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case OP_SMLAL:
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case OP_SMULL:
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return DisassembleUMLAL(opcode, insn);
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default:
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return "Error";
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}
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return nullptr;
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}
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std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn) {
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static const u8 kNoOperand1 = 1;
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static const u8 kNoDest = 2;
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static const u8 kNoSbit = 4;
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std::string rn_str;
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std::string rd_str;
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u8 flags = 0;
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u8 cond = (insn >> 28) & 0xf;
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u8 is_immed = (insn >> 25) & 0x1;
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u8 bit_s = (insn >> 20) & 1;
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u8 rn = (insn >> 16) & 0xf;
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u8 rd = (insn >> 12) & 0xf;
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u8 immed = insn & 0xff;
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const char* opname = opcode_names[opcode];
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switch (opcode) {
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case OP_CMN:
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case OP_CMP:
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case OP_TEQ:
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case OP_TST:
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flags = kNoDest | kNoSbit;
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break;
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case OP_MOV:
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case OP_MVN:
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flags = kNoOperand1;
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break;
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default:
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break;
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}
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// The "mov" instruction ignores the first operand (rn).
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rn_str[0] = 0;
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if ((flags & kNoOperand1) == 0) {
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rn_str = Common::StringFromFormat("r%d, ", rn);
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}
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// The following instructions do not write the result register (rd):
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// tst, teq, cmp, cmn.
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rd_str[0] = 0;
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if ((flags & kNoDest) == 0) {
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rd_str = Common::StringFromFormat("r%d, ", rd);
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}
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const char* sbit_str = "";
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if (bit_s && !(flags & kNoSbit))
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sbit_str = "s";
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if (is_immed) {
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return Common::StringFromFormat("%s%s%s\t%s%s#%u ; 0x%x", opname, cond_to_str(cond),
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sbit_str, rd_str.c_str(), rn_str.c_str(), immed, immed);
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}
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u8 shift_is_reg = (insn >> 4) & 1;
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u8 rotate = (insn >> 8) & 0xf;
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u8 rm = insn & 0xf;
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u8 shift_type = (insn >> 5) & 0x3;
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u8 rs = (insn >> 8) & 0xf;
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u8 shift_amount = (insn >> 7) & 0x1f;
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u32 rotated_val = immed;
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u8 rotate2 = rotate << 1;
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rotated_val = (rotated_val >> rotate2) | (rotated_val << (32 - rotate2));
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if (!shift_is_reg && shift_type == 0 && shift_amount == 0) {
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return Common::StringFromFormat("%s%s%s\t%s%sr%d", opname, cond_to_str(cond), sbit_str,
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rd_str.c_str(), rn_str.c_str(), rm);
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}
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const char* shift_name = shift_names[shift_type];
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if (shift_is_reg) {
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return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s r%d", opname, cond_to_str(cond),
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sbit_str, rd_str.c_str(), rn_str.c_str(), rm, shift_name,
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rs);
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}
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if (shift_amount == 0) {
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if (shift_type == 3) {
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return Common::StringFromFormat("%s%s%s\t%s%sr%d, RRX", opname, cond_to_str(cond),
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sbit_str, rd_str.c_str(), rn_str.c_str(), rm);
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}
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shift_amount = 32;
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}
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return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s #%u", opname, cond_to_str(cond), sbit_str,
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rd_str.c_str(), rn_str.c_str(), rm, shift_name, shift_amount);
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}
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std::string ARM_Disasm::DisassembleBranch(u32 addr, Opcode opcode, u32 insn) {
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u8 cond = (insn >> 28) & 0xf;
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u32 offset = insn & 0xffffff;
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// Sign-extend the 24-bit offset
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if ((offset >> 23) & 1)
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offset |= 0xff000000;
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// Pre-compute the left-shift and the prefetch offset
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offset <<= 2;
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offset += 8;
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addr += offset;
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const char* opname = opcode_names[opcode];
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return Common::StringFromFormat("%s%s\t0x%x", opname, cond_to_str(cond), addr);
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}
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std::string ARM_Disasm::DisassembleBX(u32 insn) {
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u8 cond = (insn >> 28) & 0xf;
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u8 rn = insn & 0xf;
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return Common::StringFromFormat("bx%s\tr%d", cond_to_str(cond), rn);
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}
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std::string ARM_Disasm::DisassembleBKPT(u32 insn) {
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u8 cond = (insn >> 28) & 0xf;
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u32 immed = (((insn >> 8) & 0xfff) << 4) | (insn & 0xf);
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return Common::StringFromFormat("bkpt%s\t#%d", cond_to_str(cond), immed);
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}
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std::string ARM_Disasm::DisassembleCLZ(u32 insn) {
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u8 cond = (insn >> 28) & 0xf;
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u8 rd = (insn >> 12) & 0xf;
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u8 rm = insn & 0xf;
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return Common::StringFromFormat("clz%s\tr%d, r%d", cond_to_str(cond), rd, rm);
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}
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std::string ARM_Disasm::DisassembleMediaMulDiv(Opcode opcode, u32 insn) {
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u32 cond = BITS(insn, 28, 31);
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u32 rd = BITS(insn, 16, 19);
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u32 ra = BITS(insn, 12, 15);
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u32 rm = BITS(insn, 8, 11);
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u32 m = BIT(insn, 5);
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u32 rn = BITS(insn, 0, 3);
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std::string cross = "";
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if (m) {
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if (opcode == OP_SMMLA || opcode == OP_SMMUL || opcode == OP_SMMLS)
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cross = "r";
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else
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cross = "x";
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}
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std::string ext_reg = "";
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std::unordered_set<Opcode, std::hash<int>> with_ext_reg = {OP_SMLAD, OP_SMLSD, OP_SMMLA,
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OP_SMMLS, OP_USADA8};
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if (with_ext_reg.find(opcode) != with_ext_reg.end())
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ext_reg = Common::StringFromFormat(", r%u", ra);
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std::string rd_low = "";
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if (opcode == OP_SMLALD || opcode == OP_SMLSLD)
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rd_low = Common::StringFromFormat("r%u, ", ra);
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return Common::StringFromFormat("%s%s%s\t%sr%u, r%u, r%u%s", opcode_names[opcode],
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cross.c_str(), cond_to_str(cond), rd_low.c_str(), rd, rn, rm,
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ext_reg.c_str());
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}
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std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn) {
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std::string tmp_list;
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u8 cond = (insn >> 28) & 0xf;
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u8 write_back = (insn >> 21) & 0x1;
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u8 bit_s = (insn >> 22) & 0x1;
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u8 is_up = (insn >> 23) & 0x1;
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u8 is_pre = (insn >> 24) & 0x1;
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u8 rn = (insn >> 16) & 0xf;
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u16 reg_list = insn & 0xffff;
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const char* opname = opcode_names[opcode];
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const char* bang = "";
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if (write_back)
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bang = "!";
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const char* carret = "";
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if (bit_s)
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carret = "^";
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const char* comma = "";
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tmp_list[0] = 0;
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for (int ii = 0; ii < 16; ++ii) {
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if (reg_list & (1 << ii)) {
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tmp_list += Common::StringFromFormat("%sr%d", comma, ii);
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comma = ",";
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}
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}
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const char* addr_mode = "";
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if (is_pre) {
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if (is_up) {
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addr_mode = "ib";
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} else {
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addr_mode = "db";
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}
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} else {
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if (is_up) {
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addr_mode = "ia";
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} else {
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addr_mode = "da";
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}
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}
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return Common::StringFromFormat("%s%s%s\tr%d%s, {%s}%s", opname, cond_to_str(cond), addr_mode,
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rn, bang, tmp_list.c_str(), carret);
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}
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std::string ARM_Disasm::DisassembleMem(u32 insn) {
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u8 cond = (insn >> 28) & 0xf;
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u8 is_reg = (insn >> 25) & 0x1;
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u8 is_load = (insn >> 20) & 0x1;
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u8 write_back = (insn >> 21) & 0x1;
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u8 is_byte = (insn >> 22) & 0x1;
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u8 is_up = (insn >> 23) & 0x1;
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u8 is_pre = (insn >> 24) & 0x1;
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u8 rn = (insn >> 16) & 0xf;
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u8 rd = (insn >> 12) & 0xf;
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u16 offset = insn & 0xfff;
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const char* opname = "ldr";
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if (!is_load)
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opname = "str";
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const char* bang = "";
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if (write_back)
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bang = "!";
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const char* minus = "";
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if (is_up == 0)
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minus = "-";
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|
const char* byte = "";
|
|
if (is_byte)
|
|
byte = "b";
|
|
|
|
if (is_reg == 0) {
|
|
if (is_pre) {
|
|
if (offset == 0) {
|
|
return Common::StringFromFormat("%s%s%s\tr%d, [r%d]", opname, cond_to_str(cond),
|
|
byte, rd, rn);
|
|
} else {
|
|
return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s", opname,
|
|
cond_to_str(cond), byte, rd, rn, minus, offset,
|
|
bang);
|
|
}
|
|
} else {
|
|
const char* transfer = "";
|
|
if (write_back)
|
|
transfer = "t";
|
|
|
|
return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], #%s%u", opname,
|
|
cond_to_str(cond), byte, transfer, rd, rn, minus,
|
|
offset);
|
|
}
|
|
}
|
|
|
|
u8 rm = insn & 0xf;
|
|
u8 shift_type = (insn >> 5) & 0x3;
|
|
u8 shift_amount = (insn >> 7) & 0x1f;
|
|
|
|
const char* shift_name = shift_names[shift_type];
|
|
|
|
if (is_pre) {
|
|
if (shift_amount == 0) {
|
|
if (shift_type == 0) {
|
|
return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s", opname,
|
|
cond_to_str(cond), byte, rd, rn, minus, rm, bang);
|
|
}
|
|
if (shift_type == 3) {
|
|
return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, RRX]%s", opname,
|
|
cond_to_str(cond), byte, rd, rn, minus, rm, bang);
|
|
}
|
|
shift_amount = 32;
|
|
}
|
|
return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, %s #%u]%s", opname,
|
|
cond_to_str(cond), byte, rd, rn, minus, rm, shift_name,
|
|
shift_amount, bang);
|
|
}
|
|
|
|
const char* transfer = "";
|
|
if (write_back)
|
|
transfer = "t";
|
|
|
|
if (shift_amount == 0) {
|
|
if (shift_type == 0) {
|
|
return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d", opname,
|
|
cond_to_str(cond), byte, transfer, rd, rn, minus, rm);
|
|
}
|
|
if (shift_type == 3) {
|
|
return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, RRX", opname,
|
|
cond_to_str(cond), byte, transfer, rd, rn, minus, rm);
|
|
}
|
|
shift_amount = 32;
|
|
}
|
|
|
|
return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, %s #%u", opname,
|
|
cond_to_str(cond), byte, transfer, rd, rn, minus, rm,
|
|
shift_name, shift_amount);
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleMemHalf(u32 insn) {
|
|
u8 cond = (insn >> 28) & 0xf;
|
|
u8 is_load = (insn >> 20) & 0x1;
|
|
u8 write_back = (insn >> 21) & 0x1;
|
|
u8 is_immed = (insn >> 22) & 0x1;
|
|
u8 is_up = (insn >> 23) & 0x1;
|
|
u8 is_pre = (insn >> 24) & 0x1;
|
|
u8 rn = (insn >> 16) & 0xf;
|
|
u8 rd = (insn >> 12) & 0xf;
|
|
u8 bits_65 = (insn >> 5) & 0x3;
|
|
u8 rm = insn & 0xf;
|
|
u8 offset = (((insn >> 8) & 0xf) << 4) | (insn & 0xf);
|
|
|
|
const char* opname = "ldr";
|
|
if (is_load == 0)
|
|
opname = "str";
|
|
|
|
const char* width = "";
|
|
if (bits_65 == 1)
|
|
width = "h";
|
|
else if (bits_65 == 2)
|
|
width = "sb";
|
|
else
|
|
width = "sh";
|
|
|
|
const char* bang = "";
|
|
if (write_back)
|
|
bang = "!";
|
|
const char* minus = "";
|
|
if (is_up == 0)
|
|
minus = "-";
|
|
|
|
if (is_immed) {
|
|
if (is_pre) {
|
|
if (offset == 0) {
|
|
return Common::StringFromFormat("%s%s%s\tr%d, [r%d]", opname, cond_to_str(cond),
|
|
width, rd, rn);
|
|
} else {
|
|
return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s", opname,
|
|
cond_to_str(cond), width, rd, rn, minus, offset,
|
|
bang);
|
|
}
|
|
} else {
|
|
return Common::StringFromFormat("%s%s%s\tr%d, [r%d], #%s%u", opname, cond_to_str(cond),
|
|
width, rd, rn, minus, offset);
|
|
}
|
|
}
|
|
|
|
if (is_pre) {
|
|
return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s", opname, cond_to_str(cond),
|
|
width, rd, rn, minus, rm, bang);
|
|
} else {
|
|
return Common::StringFromFormat("%s%s%s\tr%d, [r%d], %sr%d", opname, cond_to_str(cond),
|
|
width, rd, rn, minus, rm);
|
|
}
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleMCR(Opcode opcode, u32 insn) {
|
|
u8 cond = (insn >> 28) & 0xf;
|
|
u8 crn = (insn >> 16) & 0xf;
|
|
u8 crd = (insn >> 12) & 0xf;
|
|
u8 cpnum = (insn >> 8) & 0xf;
|
|
u8 opcode2 = (insn >> 5) & 0x7;
|
|
u8 crm = insn & 0xf;
|
|
|
|
const char* opname = opcode_names[opcode];
|
|
return Common::StringFromFormat("%s%s\t%d, 0, r%d, cr%d, cr%d, {%d}", opname, cond_to_str(cond),
|
|
cpnum, crd, crn, crm, opcode2);
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleMLA(Opcode opcode, u32 insn) {
|
|
u8 cond = (insn >> 28) & 0xf;
|
|
u8 rd = (insn >> 16) & 0xf;
|
|
u8 rn = (insn >> 12) & 0xf;
|
|
u8 rs = (insn >> 8) & 0xf;
|
|
u8 rm = insn & 0xf;
|
|
u8 bit_s = (insn >> 20) & 1;
|
|
|
|
const char* opname = opcode_names[opcode];
|
|
return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", opname, cond_to_str(cond),
|
|
bit_s ? "s" : "", rd, rm, rs, rn);
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, u32 insn) {
|
|
u8 cond = (insn >> 28) & 0xf;
|
|
u8 rdhi = (insn >> 16) & 0xf;
|
|
u8 rdlo = (insn >> 12) & 0xf;
|
|
u8 rs = (insn >> 8) & 0xf;
|
|
u8 rm = insn & 0xf;
|
|
u8 bit_s = (insn >> 20) & 1;
|
|
|
|
const char* opname = opcode_names[opcode];
|
|
return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", opname, cond_to_str(cond),
|
|
bit_s ? "s" : "", rdlo, rdhi, rm, rs);
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleMUL(Opcode opcode, u32 insn) {
|
|
u8 cond = (insn >> 28) & 0xf;
|
|
u8 rd = (insn >> 16) & 0xf;
|
|
u8 rs = (insn >> 8) & 0xf;
|
|
u8 rm = insn & 0xf;
|
|
u8 bit_s = (insn >> 20) & 1;
|
|
|
|
const char* opname = opcode_names[opcode];
|
|
return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d", opname, cond_to_str(cond),
|
|
bit_s ? "s" : "", rd, rm, rs);
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleMRS(u32 insn) {
|
|
u8 cond = (insn >> 28) & 0xf;
|
|
u8 rd = (insn >> 12) & 0xf;
|
|
u8 ps = (insn >> 22) & 1;
|
|
|
|
return Common::StringFromFormat("mrs%s\tr%d, %s", cond_to_str(cond), rd, ps ? "spsr" : "cpsr");
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleMSR(u32 insn) {
|
|
char flags[8];
|
|
int flag_index = 0;
|
|
u8 cond = (insn >> 28) & 0xf;
|
|
u8 is_immed = (insn >> 25) & 0x1;
|
|
u8 pd = (insn >> 22) & 1;
|
|
u8 mask = (insn >> 16) & 0xf;
|
|
|
|
if (mask & 1)
|
|
flags[flag_index++] = 'c';
|
|
if (mask & 2)
|
|
flags[flag_index++] = 'x';
|
|
if (mask & 4)
|
|
flags[flag_index++] = 's';
|
|
if (mask & 8)
|
|
flags[flag_index++] = 'f';
|
|
flags[flag_index] = 0;
|
|
|
|
if (is_immed) {
|
|
u32 immed = insn & 0xff;
|
|
u8 rotate = (insn >> 8) & 0xf;
|
|
u8 rotate2 = rotate << 1;
|
|
u32 rotated_val = (immed >> rotate2) | (immed << (32 - rotate2));
|
|
return Common::StringFromFormat("msr%s\t%s_%s, #0x%x", cond_to_str(cond),
|
|
pd ? "spsr" : "cpsr", flags, rotated_val);
|
|
}
|
|
|
|
u8 rm = insn & 0xf;
|
|
|
|
return Common::StringFromFormat("msr%s\t%s_%s, r%d", cond_to_str(cond), pd ? "spsr" : "cpsr",
|
|
flags, rm);
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleNoOperands(Opcode opcode, u32 insn) {
|
|
u32 cond = BITS(insn, 28, 31);
|
|
return Common::StringFromFormat("%s%s", opcode_names[opcode], cond_to_str(cond));
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleParallelAddSub(Opcode opcode, u32 insn) {
|
|
u32 cond = BITS(insn, 28, 31);
|
|
u32 rn = BITS(insn, 16, 19);
|
|
u32 rd = BITS(insn, 12, 15);
|
|
u32 rm = BITS(insn, 0, 3);
|
|
|
|
return Common::StringFromFormat("%s%s\tr%u, r%u, r%u", opcode_names[opcode], cond_to_str(cond),
|
|
rd, rn, rm);
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassemblePKH(u32 insn) {
|
|
u32 cond = BITS(insn, 28, 31);
|
|
u32 rn = BITS(insn, 16, 19);
|
|
u32 rd = BITS(insn, 12, 15);
|
|
u32 imm5 = BITS(insn, 7, 11);
|
|
u32 tb = BIT(insn, 6);
|
|
u32 rm = BITS(insn, 0, 3);
|
|
|
|
std::string suffix = tb ? "tb" : "bt";
|
|
std::string shift = "";
|
|
|
|
if (tb && imm5 == 0)
|
|
imm5 = 32;
|
|
|
|
if (imm5 > 0) {
|
|
shift = tb ? ", ASR" : ", LSL";
|
|
shift += " #" + std::to_string(imm5);
|
|
}
|
|
|
|
return Common::StringFromFormat("pkh%s%s\tr%u, r%u, r%u%s", suffix.c_str(), cond_to_str(cond),
|
|
rd, rn, rm, shift.c_str());
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassemblePLD(u32 insn) {
|
|
u8 is_reg = (insn >> 25) & 0x1;
|
|
u8 is_up = (insn >> 23) & 0x1;
|
|
u8 rn = (insn >> 16) & 0xf;
|
|
|
|
const char* minus = "";
|
|
if (is_up == 0)
|
|
minus = "-";
|
|
|
|
if (is_reg) {
|
|
u8 rm = insn & 0xf;
|
|
return Common::StringFromFormat("pld\t[r%d, %sr%d]", rn, minus, rm);
|
|
}
|
|
|
|
u16 offset = insn & 0xfff;
|
|
if (offset == 0) {
|
|
return Common::StringFromFormat("pld\t[r%d]", rn);
|
|
} else {
|
|
return Common::StringFromFormat("pld\t[r%d, #%s%u]", rn, minus, offset);
|
|
}
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleREV(Opcode opcode, u32 insn) {
|
|
u32 cond = BITS(insn, 28, 31);
|
|
u32 rd = BITS(insn, 12, 15);
|
|
u32 rm = BITS(insn, 0, 3);
|
|
|
|
return Common::StringFromFormat("%s%s\tr%u, r%u", opcode_names[opcode], cond_to_str(cond), rd,
|
|
rm);
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleREX(Opcode opcode, u32 insn) {
|
|
u32 rn = BITS(insn, 16, 19);
|
|
u32 rd = BITS(insn, 12, 15);
|
|
u32 rt = BITS(insn, 0, 3);
|
|
u32 cond = BITS(insn, 28, 31);
|
|
|
|
switch (opcode) {
|
|
case OP_STREX:
|
|
case OP_STREXB:
|
|
case OP_STREXH:
|
|
return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode],
|
|
cond_to_str(cond), rd, rt, rn);
|
|
case OP_STREXD:
|
|
return Common::StringFromFormat("%s%s\tr%d, r%d, r%d, [r%d]", opcode_names[opcode],
|
|
cond_to_str(cond), rd, rt, rt + 1, rn);
|
|
|
|
// for LDREX instructions, rd corresponds to Rt from reference manual
|
|
case OP_LDREX:
|
|
case OP_LDREXB:
|
|
case OP_LDREXH:
|
|
return Common::StringFromFormat("%s%s\tr%d, [r%d]", opcode_names[opcode], cond_to_str(cond),
|
|
rd, rn);
|
|
case OP_LDREXD:
|
|
return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode],
|
|
cond_to_str(cond), rd, rd + 1, rn);
|
|
default:
|
|
return opcode_names[OP_UNDEFINED];
|
|
}
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleSAT(Opcode opcode, u32 insn) {
|
|
u32 cond = BITS(insn, 28, 31);
|
|
u32 sat_imm = BITS(insn, 16, 20);
|
|
u32 rd = BITS(insn, 12, 15);
|
|
u32 imm5 = BITS(insn, 7, 11);
|
|
u32 sh = BIT(insn, 6);
|
|
u32 rn = BITS(insn, 0, 3);
|
|
|
|
std::string shift_part = "";
|
|
bool opcode_has_shift = (opcode == OP_SSAT) || (opcode == OP_USAT);
|
|
if (opcode_has_shift && !(sh == 0 && imm5 == 0)) {
|
|
if (sh == 0)
|
|
shift_part += ", LSL #";
|
|
else
|
|
shift_part += ", ASR #";
|
|
|
|
if (imm5 == 0)
|
|
imm5 = 32;
|
|
shift_part += std::to_string(imm5);
|
|
}
|
|
|
|
if (opcode == OP_SSAT || opcode == OP_SSAT16)
|
|
sat_imm++;
|
|
|
|
return Common::StringFromFormat("%s%s\tr%u, #%u, r%u%s", opcode_names[opcode],
|
|
cond_to_str(cond), rd, sat_imm, rn, shift_part.c_str());
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleSEL(u32 insn) {
|
|
u32 cond = BITS(insn, 28, 31);
|
|
u32 rn = BITS(insn, 16, 19);
|
|
u32 rd = BITS(insn, 12, 15);
|
|
u32 rm = BITS(insn, 0, 3);
|
|
|
|
return Common::StringFromFormat("%s%s\tr%u, r%u, r%u", opcode_names[OP_SEL], cond_to_str(cond),
|
|
rd, rn, rm);
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleSWI(u32 insn) {
|
|
u8 cond = (insn >> 28) & 0xf;
|
|
u32 sysnum = insn & 0x00ffffff;
|
|
|
|
return Common::StringFromFormat("swi%s 0x%x", cond_to_str(cond), sysnum);
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleSWP(Opcode opcode, u32 insn) {
|
|
u8 cond = (insn >> 28) & 0xf;
|
|
u8 rn = (insn >> 16) & 0xf;
|
|
u8 rd = (insn >> 12) & 0xf;
|
|
u8 rm = insn & 0xf;
|
|
|
|
const char* opname = opcode_names[opcode];
|
|
return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opname, cond_to_str(cond), rd, rm, rn);
|
|
}
|
|
|
|
std::string ARM_Disasm::DisassembleXT(Opcode opcode, u32 insn) {
|
|
u32 cond = BITS(insn, 28, 31);
|
|
u32 rn = BITS(insn, 16, 19);
|
|
u32 rd = BITS(insn, 12, 15);
|
|
u32 rotate = BITS(insn, 10, 11);
|
|
u32 rm = BITS(insn, 0, 3);
|
|
|
|
std::string rn_part = "";
|
|
static std::unordered_set<Opcode, std::hash<int>> extend_with_add = {
|
|
OP_SXTAB, OP_SXTAB16, OP_SXTAH, OP_UXTAB, OP_UXTAB16, OP_UXTAH};
|
|
if (extend_with_add.find(opcode) != extend_with_add.end())
|
|
rn_part = ", r" + std::to_string(rn);
|
|
|
|
std::string rotate_part = "";
|
|
if (rotate != 0)
|
|
rotate_part = ", ROR #" + std::to_string(rotate << 3);
|
|
|
|
return Common::StringFromFormat("%s%s\tr%u%s, r%u%s", opcode_names[opcode], cond_to_str(cond),
|
|
rd, rn_part.c_str(), rm, rotate_part.c_str());
|
|
}
|
|
|
|
Opcode ARM_Disasm::Decode(u32 insn) {
|
|
u32 bits27_26 = (insn >> 26) & 0x3;
|
|
switch (bits27_26) {
|
|
case 0x0:
|
|
return Decode00(insn);
|
|
case 0x1:
|
|
return Decode01(insn);
|
|
case 0x2:
|
|
return Decode10(insn);
|
|
case 0x3:
|
|
return Decode11(insn);
|
|
}
|
|
return OP_INVALID;
|
|
}
|
|
|
|
Opcode ARM_Disasm::Decode00(u32 insn) {
|
|
u8 bit25 = (insn >> 25) & 0x1;
|
|
u8 bit4 = (insn >> 4) & 0x1;
|
|
if (bit25 == 0 && bit4 == 1) {
|
|
if ((insn & 0x0ffffff0) == 0x012fff10) {
|
|
// Bx instruction
|
|
return OP_BX;
|
|
}
|
|
if ((insn & 0x0ff000f0) == 0x01600010) {
|
|
// Clz instruction
|
|
return OP_CLZ;
|
|
}
|
|
if ((insn & 0xfff000f0) == 0xe1200070) {
|
|
// Bkpt instruction
|
|
return OP_BKPT;
|
|
}
|
|
u32 bits7_4 = (insn >> 4) & 0xf;
|
|
if (bits7_4 == 0x9) {
|
|
u32 bit24 = BIT(insn, 24);
|
|
if (bit24) {
|
|
return DecodeSyncPrimitive(insn);
|
|
}
|
|
// One of the multiply instructions
|
|
return DecodeMUL(insn);
|
|
}
|
|
|
|
u8 bit7 = (insn >> 7) & 0x1;
|
|
if (bit7 == 1) {
|
|
// One of the load/store halfword/byte instructions
|
|
return DecodeLDRH(insn);
|
|
}
|
|
}
|
|
|
|
u32 op1 = BITS(insn, 20, 24);
|
|
if (bit25 && (op1 == 0x12 || op1 == 0x16)) {
|
|
// One of the MSR (immediate) and hints instructions
|
|
return DecodeMSRImmAndHints(insn);
|
|
}
|
|
|
|
// One of the data processing instructions
|
|
return DecodeALU(insn);
|
|
}
|
|
|
|
Opcode ARM_Disasm::Decode01(u32 insn) {
|
|
u8 is_reg = (insn >> 25) & 0x1;
|
|
u8 bit4 = (insn >> 4) & 0x1;
|
|
if (is_reg == 1 && bit4 == 1)
|
|
return DecodeMedia(insn);
|
|
u8 is_load = (insn >> 20) & 0x1;
|
|
u8 is_byte = (insn >> 22) & 0x1;
|
|
if ((insn & 0xfd70f000) == 0xf550f000) {
|
|
// Pre-load
|
|
return OP_PLD;
|
|
}
|
|
if (insn == 0xf57ff01f) {
|
|
// Clear-Exclusive
|
|
return OP_CLREX;
|
|
}
|
|
if (is_load) {
|
|
if (is_byte) {
|
|
// Load byte
|
|
return OP_LDRB;
|
|
}
|
|
// Load word
|
|
return OP_LDR;
|
|
}
|
|
if (is_byte) {
|
|
// Store byte
|
|
return OP_STRB;
|
|
}
|
|
// Store word
|
|
return OP_STR;
|
|
}
|
|
|
|
Opcode ARM_Disasm::Decode10(u32 insn) {
|
|
u8 bit25 = (insn >> 25) & 0x1;
|
|
if (bit25 == 0) {
|
|
// LDM/STM
|
|
u8 is_load = (insn >> 20) & 0x1;
|
|
if (is_load)
|
|
return OP_LDM;
|
|
return OP_STM;
|
|
}
|
|
|
|
// Branch with link
|
|
if ((insn >> 24) & 1)
|
|
return OP_BL;
|
|
|
|
return OP_B;
|
|
}
|
|
|
|
Opcode ARM_Disasm::Decode11(u32 insn) {
|
|
u8 bit25 = (insn >> 25) & 0x1;
|
|
if (bit25 == 0) {
|
|
// LDC, SDC
|
|
u8 is_load = (insn >> 20) & 0x1;
|
|
if (is_load) {
|
|
// LDC
|
|
return OP_LDC;
|
|
}
|
|
// STC
|
|
return OP_STC;
|
|
}
|
|
|
|
u8 bit24 = (insn >> 24) & 0x1;
|
|
if (bit24 == 0x1) {
|
|
// SWI
|
|
return OP_SWI;
|
|
}
|
|
|
|
u8 bit4 = (insn >> 4) & 0x1;
|
|
u8 cpnum = (insn >> 8) & 0xf;
|
|
|
|
if (cpnum == 15) {
|
|
// Special case for coprocessor 15
|
|
u8 opcode = (insn >> 21) & 0x7;
|
|
if (bit4 == 0 || opcode != 0) {
|
|
// This is an unexpected bit pattern. Create an undefined
|
|
// instruction in case this is ever executed.
|
|
return OP_UNDEFINED;
|
|
}
|
|
|
|
// MRC, MCR
|
|
u8 is_mrc = (insn >> 20) & 0x1;
|
|
if (is_mrc)
|
|
return OP_MRC;
|
|
return OP_MCR;
|
|
}
|
|
|
|
if (bit4 == 0) {
|
|
// CDP
|
|
return OP_CDP;
|
|
}
|
|
// MRC, MCR
|
|
u8 is_mrc = (insn >> 20) & 0x1;
|
|
if (is_mrc)
|
|
return OP_MRC;
|
|
return OP_MCR;
|
|
}
|
|
|
|
Opcode ARM_Disasm::DecodeSyncPrimitive(u32 insn) {
|
|
u32 op = BITS(insn, 20, 23);
|
|
u32 bit22 = BIT(insn, 22);
|
|
switch (op) {
|
|
case 0x0:
|
|
if (bit22)
|
|
return OP_SWPB;
|
|
return OP_SWP;
|
|
case 0x8:
|
|
return OP_STREX;
|
|
case 0x9:
|
|
return OP_LDREX;
|
|
case 0xA:
|
|
return OP_STREXD;
|
|
case 0xB:
|
|
return OP_LDREXD;
|
|
case 0xC:
|
|
return OP_STREXB;
|
|
case 0xD:
|
|
return OP_LDREXB;
|
|
case 0xE:
|
|
return OP_STREXH;
|
|
case 0xF:
|
|
return OP_LDREXH;
|
|
default:
|
|
return OP_UNDEFINED;
|
|
}
|
|
}
|
|
|
|
Opcode ARM_Disasm::DecodeParallelAddSub(u32 insn) {
|
|
u32 op1 = BITS(insn, 20, 21);
|
|
u32 op2 = BITS(insn, 5, 7);
|
|
u32 is_unsigned = BIT(insn, 22);
|
|
|
|
if (op1 == 0x0 || op2 == 0x5 || op2 == 0x6)
|
|
return OP_UNDEFINED;
|
|
|
|
// change op1 range from [1, 3] to range [0, 2]
|
|
op1--;
|
|
|
|
// change op2 range from [0, 4] U {7} to range [0, 5]
|
|
if (op2 == 0x7)
|
|
op2 = 0x5;
|
|
|
|
static std::vector<Opcode> opcodes = {
|
|
// op1 = 0
|
|
OP_SADD16, OP_UADD16, OP_SASX, OP_UASX, OP_SSAX, OP_USAX, OP_SSUB16, OP_USUB16, OP_SADD8,
|
|
OP_UADD8, OP_SSUB8, OP_USUB8,
|
|
// op1 = 1
|
|
OP_QADD16, OP_UQADD16, OP_QASX, OP_UQASX, OP_QSAX, OP_UQSAX, OP_QSUB16, OP_UQSUB16,
|
|
OP_QADD8, OP_UQADD8, OP_QSUB8, OP_UQSUB8,
|
|
// op1 = 2
|
|
OP_SHADD16, OP_UHADD16, OP_SHASX, OP_UHASX, OP_SHSAX, OP_UHSAX, OP_SHSUB16, OP_UHSUB16,
|
|
OP_SHADD8, OP_UHADD8, OP_SHSUB8, OP_UHSUB8};
|
|
|
|
u32 opcode_index = op1 * 12 + op2 * 2 + is_unsigned;
|
|
return opcodes[opcode_index];
|
|
}
|
|
|
|
Opcode ARM_Disasm::DecodePackingSaturationReversal(u32 insn) {
|
|
u32 op1 = BITS(insn, 20, 22);
|
|
u32 a = BITS(insn, 16, 19);
|
|
u32 op2 = BITS(insn, 5, 7);
|
|
|
|
switch (op1) {
|
|
case 0x0:
|
|
if (BIT(op2, 0) == 0)
|
|
return OP_PKH;
|
|
if (op2 == 0x3 && a != 0xf)
|
|
return OP_SXTAB16;
|
|
if (op2 == 0x3 && a == 0xf)
|
|
return OP_SXTB16;
|
|
if (op2 == 0x5)
|
|
return OP_SEL;
|
|
break;
|
|
case 0x2:
|
|
if (BIT(op2, 0) == 0)
|
|
return OP_SSAT;
|
|
if (op2 == 0x1)
|
|
return OP_SSAT16;
|
|
if (op2 == 0x3 && a != 0xf)
|
|
return OP_SXTAB;
|
|
if (op2 == 0x3 && a == 0xf)
|
|
return OP_SXTB;
|
|
break;
|
|
case 0x3:
|
|
if (op2 == 0x1)
|
|
return OP_REV;
|
|
if (BIT(op2, 0) == 0)
|
|
return OP_SSAT;
|
|
if (op2 == 0x3 && a != 0xf)
|
|
return OP_SXTAH;
|
|
if (op2 == 0x3 && a == 0xf)
|
|
return OP_SXTH;
|
|
if (op2 == 0x5)
|
|
return OP_REV16;
|
|
break;
|
|
case 0x4:
|
|
if (op2 == 0x3 && a != 0xf)
|
|
return OP_UXTAB16;
|
|
if (op2 == 0x3 && a == 0xf)
|
|
return OP_UXTB16;
|
|
break;
|
|
case 0x6:
|
|
if (BIT(op2, 0) == 0)
|
|
return OP_USAT;
|
|
if (op2 == 0x1)
|
|
return OP_USAT16;
|
|
if (op2 == 0x3 && a != 0xf)
|
|
return OP_UXTAB;
|
|
if (op2 == 0x3 && a == 0xf)
|
|
return OP_UXTB;
|
|
break;
|
|
case 0x7:
|
|
if (BIT(op2, 0) == 0)
|
|
return OP_USAT;
|
|
if (op2 == 0x3 && a != 0xf)
|
|
return OP_UXTAH;
|
|
if (op2 == 0x3 && a == 0xf)
|
|
return OP_UXTH;
|
|
if (op2 == 0x5)
|
|
return OP_REVSH;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return OP_UNDEFINED;
|
|
}
|
|
|
|
Opcode ARM_Disasm::DecodeMUL(u32 insn) {
|
|
u8 bit24 = (insn >> 24) & 0x1;
|
|
if (bit24 != 0) {
|
|
// This is an unexpected bit pattern. Create an undefined
|
|
// instruction in case this is ever executed.
|
|
return OP_UNDEFINED;
|
|
}
|
|
u8 bit23 = (insn >> 23) & 0x1;
|
|
u8 bit22_U = (insn >> 22) & 0x1;
|
|
u8 bit21_A = (insn >> 21) & 0x1;
|
|
if (bit23 == 0) {
|
|
// 32-bit multiply
|
|
if (bit22_U != 0) {
|
|
// This is an unexpected bit pattern. Create an undefined
|
|
// instruction in case this is ever executed.
|
|
return OP_UNDEFINED;
|
|
}
|
|
if (bit21_A == 0)
|
|
return OP_MUL;
|
|
return OP_MLA;
|
|
}
|
|
// 64-bit multiply
|
|
if (bit22_U == 0) {
|
|
// Unsigned multiply long
|
|
if (bit21_A == 0)
|
|
return OP_UMULL;
|
|
return OP_UMLAL;
|
|
}
|
|
// Signed multiply long
|
|
if (bit21_A == 0)
|
|
return OP_SMULL;
|
|
return OP_SMLAL;
|
|
}
|
|
|
|
Opcode ARM_Disasm::DecodeMSRImmAndHints(u32 insn) {
|
|
u32 op = BIT(insn, 22);
|
|
u32 op1 = BITS(insn, 16, 19);
|
|
u32 op2 = BITS(insn, 0, 7);
|
|
|
|
if (op == 0 && op1 == 0) {
|
|
switch (op2) {
|
|
case 0x0:
|
|
return OP_NOP;
|
|
case 0x1:
|
|
return OP_YIELD;
|
|
case 0x2:
|
|
return OP_WFE;
|
|
case 0x3:
|
|
return OP_WFI;
|
|
case 0x4:
|
|
return OP_SEV;
|
|
default:
|
|
return OP_UNDEFINED;
|
|
}
|
|
}
|
|
|
|
return OP_MSR;
|
|
}
|
|
|
|
Opcode ARM_Disasm::DecodeMediaMulDiv(u32 insn) {
|
|
u32 op1 = BITS(insn, 20, 22);
|
|
u32 op2_h = BITS(insn, 6, 7);
|
|
u32 a = BITS(insn, 12, 15);
|
|
|
|
switch (op1) {
|
|
case 0x0:
|
|
if (op2_h == 0x0) {
|
|
if (a != 0xf)
|
|
return OP_SMLAD;
|
|
else
|
|
return OP_SMUAD;
|
|
} else if (op2_h == 0x1) {
|
|
if (a != 0xf)
|
|
return OP_SMLSD;
|
|
else
|
|
return OP_SMUSD;
|
|
}
|
|
break;
|
|
case 0x4:
|
|
if (op2_h == 0x0)
|
|
return OP_SMLALD;
|
|
else if (op2_h == 0x1)
|
|
return OP_SMLSLD;
|
|
break;
|
|
case 0x5:
|
|
if (op2_h == 0x0) {
|
|
if (a != 0xf)
|
|
return OP_SMMLA;
|
|
else
|
|
return OP_SMMUL;
|
|
} else if (op2_h == 0x3) {
|
|
return OP_SMMLS;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return OP_UNDEFINED;
|
|
}
|
|
|
|
Opcode ARM_Disasm::DecodeMedia(u32 insn) {
|
|
u32 op1 = BITS(insn, 20, 24);
|
|
u32 rd = BITS(insn, 12, 15);
|
|
u32 op2 = BITS(insn, 5, 7);
|
|
|
|
switch (BITS(op1, 3, 4)) {
|
|
case 0x0:
|
|
// unsigned and signed parallel addition and subtraction
|
|
return DecodeParallelAddSub(insn);
|
|
case 0x1:
|
|
// Packing, unpacking, saturation, and reversal
|
|
return DecodePackingSaturationReversal(insn);
|
|
case 0x2:
|
|
// Signed multiply, signed and unsigned divide
|
|
return DecodeMediaMulDiv(insn);
|
|
case 0x3:
|
|
if (op2 == 0 && rd == 0xf)
|
|
return OP_USAD8;
|
|
if (op2 == 0 && rd != 0xf)
|
|
return OP_USADA8;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return OP_UNDEFINED;
|
|
}
|
|
|
|
Opcode ARM_Disasm::DecodeLDRH(u32 insn) {
|
|
u8 is_load = (insn >> 20) & 0x1;
|
|
u8 bits_65 = (insn >> 5) & 0x3;
|
|
if (is_load) {
|
|
if (bits_65 == 0x1) {
|
|
// Load unsigned halfword
|
|
return OP_LDRH;
|
|
} else if (bits_65 == 0x2) {
|
|
// Load signed byte
|
|
return OP_LDRSB;
|
|
}
|
|
// Signed halfword
|
|
if (bits_65 != 0x3) {
|
|
// This is an unexpected bit pattern. Create an undefined
|
|
// instruction in case this is ever executed.
|
|
return OP_UNDEFINED;
|
|
}
|
|
// Load signed halfword
|
|
return OP_LDRSH;
|
|
}
|
|
// Store halfword
|
|
if (bits_65 != 0x1) {
|
|
// This is an unexpected bit pattern. Create an undefined
|
|
// instruction in case this is ever executed.
|
|
return OP_UNDEFINED;
|
|
}
|
|
// Store halfword
|
|
return OP_STRH;
|
|
}
|
|
|
|
Opcode ARM_Disasm::DecodeALU(u32 insn) {
|
|
u8 is_immed = (insn >> 25) & 0x1;
|
|
u8 opcode = (insn >> 21) & 0xf;
|
|
u8 bit_s = (insn >> 20) & 1;
|
|
u8 shift_is_reg = (insn >> 4) & 1;
|
|
u8 bit7 = (insn >> 7) & 1;
|
|
if (!is_immed && shift_is_reg && (bit7 != 0)) {
|
|
// This is an unexpected bit pattern. Create an undefined
|
|
// instruction in case this is ever executed.
|
|
return OP_UNDEFINED;
|
|
}
|
|
switch (opcode) {
|
|
case 0x0:
|
|
return OP_AND;
|
|
case 0x1:
|
|
return OP_EOR;
|
|
case 0x2:
|
|
return OP_SUB;
|
|
case 0x3:
|
|
return OP_RSB;
|
|
case 0x4:
|
|
return OP_ADD;
|
|
case 0x5:
|
|
return OP_ADC;
|
|
case 0x6:
|
|
return OP_SBC;
|
|
case 0x7:
|
|
return OP_RSC;
|
|
case 0x8:
|
|
if (bit_s)
|
|
return OP_TST;
|
|
return OP_MRS;
|
|
case 0x9:
|
|
if (bit_s)
|
|
return OP_TEQ;
|
|
return OP_MSR;
|
|
case 0xa:
|
|
if (bit_s)
|
|
return OP_CMP;
|
|
return OP_MRS;
|
|
case 0xb:
|
|
if (bit_s)
|
|
return OP_CMN;
|
|
return OP_MSR;
|
|
case 0xc:
|
|
return OP_ORR;
|
|
case 0xd:
|
|
return OP_MOV;
|
|
case 0xe:
|
|
return OP_BIC;
|
|
case 0xf:
|
|
return OP_MVN;
|
|
}
|
|
// Unreachable
|
|
return OP_INVALID;
|
|
}
|