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LICENSE
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GNU GENERAL PUBLIC LICENSE
|
||||||
|
Version 2, June 1991
|
||||||
|
|
||||||
|
Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
|
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|
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
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|
Everyone is permitted to copy and distribute verbatim copies
|
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of this license document, but changing it is not allowed.
|
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|
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|
Preamble
|
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|
||||||
|
The licenses for most software are designed to take away your
|
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|
freedom to share and change it. By contrast, the GNU General Public
|
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|
License is intended to guarantee your freedom to share and change free
|
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|
software--to make sure the software is free for all its users. This
|
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|
General Public License applies to most of the Free Software
|
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|
Foundation's software and to any other program whose authors commit to
|
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using it. (Some other Free Software Foundation software is covered by
|
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|
the GNU Lesser General Public License instead.) You can apply it to
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your programs, too.
|
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|
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|
When we speak of free software, we are referring to freedom, not
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price. Our General Public Licenses are designed to make sure that you
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have the freedom to distribute copies of free software (and charge for
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this service if you wish), that you receive source code or can get it
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if you want it, that you can change the software or use pieces of it
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in new free programs; and that you know you can do these things.
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To protect your rights, we need to make restrictions that forbid
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anyone to deny you these rights or to ask you to surrender the rights.
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These restrictions translate to certain responsibilities for you if you
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distribute copies of the software, or if you modify it.
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For example, if you distribute copies of such a program, whether
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gratis or for a fee, you must give the recipients all the rights that
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you have. You must make sure that they, too, receive or can get the
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source code. And you must show them these terms so they know their
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rights.
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We protect your rights with two steps: (1) copyright the software, and
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(2) offer you this license which gives you legal permission to copy,
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distribute and/or modify the software.
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Also, for each author's protection and ours, we want to make certain
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Finally, any free program is threatened constantly by software
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patents. We wish to avoid the danger that redistributors of a free
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program will individually obtain patent licenses, in effect making the
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program proprietary. To prevent this, we have made it clear that any
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patent must be licensed for everyone's free use or not licensed at all.
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The precise terms and conditions for copying, distribution and
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modification follow.
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GNU GENERAL PUBLIC LICENSE
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TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
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0. This License applies to any program or other work which contains
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a notice placed by the copyright holder saying it may be distributed
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under the terms of this General Public License. The "Program", below,
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refers to any such program or work, and a "work based on the Program"
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means either the Program or any derivative work under copyright law:
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that is to say, a work containing the Program or a portion of it,
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either verbatim or with modifications and/or translated into another
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language. (Hereinafter, translation is included without limitation in
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the term "modification".) Each licensee is addressed as "you".
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Activities other than copying, distribution and modification are not
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covered by this License; they are outside its scope. The act of
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running the Program is not restricted, and the output from the Program
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is covered only if its contents constitute a work based on the
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Program (independent of having been made by running the Program).
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Whether that is true depends on what the Program does.
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1. You may copy and distribute verbatim copies of the Program's
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source code as you receive it, in any medium, provided that you
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conspicuously and appropriately publish on each copy an appropriate
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copyright notice and disclaimer of warranty; keep intact all the
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notices that refer to this License and to the absence of any warranty;
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and give any other recipients of the Program a copy of this License
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along with the Program.
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You may charge a fee for the physical act of transferring a copy, and
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you may at your option offer warranty protection in exchange for a fee.
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2. You may modify your copy or copies of the Program or any portion
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distribute such modifications or work under the terms of Section 1
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above, provided that you also meet all of these conditions:
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a) You must cause the modified files to carry prominent notices
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stating that you changed the files and the date of any change.
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b) You must cause any work that you distribute or publish, that in
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whole or in part contains or is derived from the Program or any
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part thereof, to be licensed as a whole at no charge to all third
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parties under the terms of this License.
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c) If the modified program normally reads commands interactively
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when run, you must cause it, when started running for such
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interactive use in the most ordinary way, to print or display an
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announcement including an appropriate copyright notice and a
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notice that there is no warranty (or else, saying that you provide
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a warranty) and that users may redistribute the program under
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these conditions, and telling the user how to view a copy of this
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License. (Exception: if the Program itself is interactive but
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does not normally print such an announcement, your work based on
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the Program is not required to print an announcement.)
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These requirements apply to the modified work as a whole. If
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identifiable sections of that work are not derived from the Program,
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and can be reasonably considered independent and separate works in
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sections when you distribute them as separate works. But when you
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distribute the same sections as part of a whole which is a work based
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on the Program, the distribution of the whole must be on the terms of
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this License, whose permissions for other licensees extend to the
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entire whole, and thus to each and every part regardless of who wrote it.
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Thus, it is not the intent of this section to claim rights or contest
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your rights to work written entirely by you; rather, the intent is to
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exercise the right to control the distribution of derivative or
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collective works based on the Program.
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In addition, mere aggregation of another work not based on the Program
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with the Program (or with a work based on the Program) on a volume of
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a storage or distribution medium does not bring the other work under
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the scope of this License.
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3. You may copy and distribute the Program (or a work based on it,
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under Section 2) in object code or executable form under the terms of
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Sections 1 and 2 above provided that you also do one of the following:
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|
||||||
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a) Accompany it with the complete corresponding machine-readable
|
||||||
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source code, which must be distributed under the terms of Sections
|
||||||
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1 and 2 above on a medium customarily used for software interchange; or,
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||||||
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|
||||||
|
b) Accompany it with a written offer, valid for at least three
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years, to give any third party, for a charge no more than your
|
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cost of physically performing source distribution, a complete
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machine-readable copy of the corresponding source code, to be
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distributed under the terms of Sections 1 and 2 above on a medium
|
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customarily used for software interchange; or,
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|
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c) Accompany it with the information you received as to the offer
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to distribute corresponding source code. (This alternative is
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allowed only for noncommercial distribution and only if you
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received the program in object code or executable form with such
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an offer, in accord with Subsection b above.)
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The source code for a work means the preferred form of the work for
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making modifications to it. For an executable work, complete source
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code means all the source code for all modules it contains, plus any
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associated interface definition files, plus the scripts used to
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control compilation and installation of the executable. However, as a
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special exception, the source code distributed need not include
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anything that is normally distributed (in either source or binary
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form) with the major components (compiler, kernel, and so on) of the
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operating system on which the executable runs, unless that component
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itself accompanies the executable.
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If distribution of executable or object code is made by offering
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access to copy from a designated place, then offering equivalent
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access to copy the source code from the same place counts as
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distribution of the source code, even though third parties are not
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compelled to copy the source along with the object code.
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4. You may not copy, modify, sublicense, or distribute the Program
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except as expressly provided under this License. Any attempt
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otherwise to copy, modify, sublicense or distribute the Program is
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void, and will automatically terminate your rights under this License.
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However, parties who have received copies, or rights, from you under
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this License will not have their licenses terminated so long as such
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parties remain in full compliance.
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5. You are not required to accept this License, since you have not
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signed it. However, nothing else grants you permission to modify or
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distribute the Program or its derivative works. These actions are
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prohibited by law if you do not accept this License. Therefore, by
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modifying or distributing the Program (or any work based on the
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Program), you indicate your acceptance of this License to do so, and
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all its terms and conditions for copying, distributing or modifying
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the Program or works based on it.
|
||||||
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|
||||||
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6. Each time you redistribute the Program (or any work based on the
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||||||
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Program), the recipient automatically receives a license from the
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original licensor to copy, distribute or modify the Program subject to
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these terms and conditions. You may not impose any further
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restrictions on the recipients' exercise of the rights granted herein.
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||||||
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You are not responsible for enforcing compliance by third parties to
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this License.
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||||||
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|
||||||
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7. If, as a consequence of a court judgment or allegation of patent
|
||||||
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infringement or for any other reason (not limited to patent issues),
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||||||
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conditions are imposed on you (whether by court order, agreement or
|
||||||
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otherwise) that contradict the conditions of this License, they do not
|
||||||
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excuse you from the conditions of this License. If you cannot
|
||||||
|
distribute so as to satisfy simultaneously your obligations under this
|
||||||
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License and any other pertinent obligations, then as a consequence you
|
||||||
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may not distribute the Program at all. For example, if a patent
|
||||||
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license would not permit royalty-free redistribution of the Program by
|
||||||
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all those who receive copies directly or indirectly through you, then
|
||||||
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the only way you could satisfy both it and this License would be to
|
||||||
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refrain entirely from distribution of the Program.
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||||||
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|
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If any portion of this section is held invalid or unenforceable under
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||||||
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any particular circumstance, the balance of the section is intended to
|
||||||
|
apply and the section as a whole is intended to apply in other
|
||||||
|
circumstances.
|
||||||
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|
||||||
|
It is not the purpose of this section to induce you to infringe any
|
||||||
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patents or other property right claims or to contest validity of any
|
||||||
|
such claims; this section has the sole purpose of protecting the
|
||||||
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integrity of the free software distribution system, which is
|
||||||
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implemented by public license practices. Many people have made
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||||||
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generous contributions to the wide range of software distributed
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||||||
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through that system in reliance on consistent application of that
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system; it is up to the author/donor to decide if he or she is willing
|
||||||
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to distribute software through any other system and a licensee cannot
|
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impose that choice.
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||||||
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|
||||||
|
This section is intended to make thoroughly clear what is believed to
|
||||||
|
be a consequence of the rest of this License.
|
||||||
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|
||||||
|
8. If the distribution and/or use of the Program is restricted in
|
||||||
|
certain countries either by patents or by copyrighted interfaces, the
|
||||||
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original copyright holder who places the Program under this License
|
||||||
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may add an explicit geographical distribution limitation excluding
|
||||||
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those countries, so that distribution is permitted only in or among
|
||||||
|
countries not thus excluded. In such case, this License incorporates
|
||||||
|
the limitation as if written in the body of this License.
|
||||||
|
|
||||||
|
9. The Free Software Foundation may publish revised and/or new versions
|
||||||
|
of the General Public License from time to time. Such new versions will
|
||||||
|
be similar in spirit to the present version, but may differ in detail to
|
||||||
|
address new problems or concerns.
|
||||||
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|
||||||
|
Each version is given a distinguishing version number. If the Program
|
||||||
|
specifies a version number of this License which applies to it and "any
|
||||||
|
later version", you have the option of following the terms and conditions
|
||||||
|
either of that version or of any later version published by the Free
|
||||||
|
Software Foundation. If the Program does not specify a version number of
|
||||||
|
this License, you may choose any version ever published by the Free Software
|
||||||
|
Foundation.
|
||||||
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|
||||||
|
10. If you wish to incorporate parts of the Program into other free
|
||||||
|
programs whose distribution conditions are different, write to the author
|
||||||
|
to ask for permission. For software which is copyrighted by the Free
|
||||||
|
Software Foundation, write to the Free Software Foundation; we sometimes
|
||||||
|
make exceptions for this. Our decision will be guided by the two goals
|
||||||
|
of preserving the free status of all derivatives of our free software and
|
||||||
|
of promoting the sharing and reuse of software generally.
|
||||||
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|
||||||
|
NO WARRANTY
|
||||||
|
|
||||||
|
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
|
||||||
|
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
|
||||||
|
OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
|
||||||
|
PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
|
||||||
|
OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||||
|
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
|
||||||
|
TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
|
||||||
|
PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
|
||||||
|
REPAIR OR CORRECTION.
|
||||||
|
|
||||||
|
12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
|
||||||
|
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
|
||||||
|
REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
|
||||||
|
INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
|
||||||
|
OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
|
||||||
|
TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
|
||||||
|
YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
|
||||||
|
PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
|
||||||
|
POSSIBILITY OF SUCH DAMAGES.
|
||||||
|
|
||||||
|
END OF TERMS AND CONDITIONS
|
||||||
|
|
||||||
|
How to Apply These Terms to Your New Programs
|
||||||
|
|
||||||
|
If you develop a new program, and you want it to be of the greatest
|
||||||
|
possible use to the public, the best way to achieve this is to make it
|
||||||
|
free software which everyone can redistribute and change under these terms.
|
||||||
|
|
||||||
|
To do so, attach the following notices to the program. It is safest
|
||||||
|
to attach them to the start of each source file to most effectively
|
||||||
|
convey the exclusion of warranty; and each file should have at least
|
||||||
|
the "copyright" line and a pointer to where the full notice is found.
|
||||||
|
|
||||||
|
<one line to give the program's name and a brief idea of what it does.>
|
||||||
|
Copyright (C) <year> <name of author>
|
||||||
|
|
||||||
|
This program is free software; you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 2 of the License, or
|
||||||
|
(at your option) any later version.
|
||||||
|
|
||||||
|
This program is distributed in the hope that it will be useful,
|
||||||
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
GNU General Public License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License along
|
||||||
|
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||||
|
|
||||||
|
Also add information on how to contact you by electronic and paper mail.
|
||||||
|
|
||||||
|
If the program is interactive, make it output a short notice like this
|
||||||
|
when it starts in an interactive mode:
|
||||||
|
|
||||||
|
Gnomovision version 69, Copyright (C) year name of author
|
||||||
|
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
|
||||||
|
This is free software, and you are welcome to redistribute it
|
||||||
|
under certain conditions; type `show c' for details.
|
||||||
|
|
||||||
|
The hypothetical commands `show w' and `show c' should show the appropriate
|
||||||
|
parts of the General Public License. Of course, the commands you use may
|
||||||
|
be called something other than `show w' and `show c'; they could even be
|
||||||
|
mouse-clicks or menu items--whatever suits your program.
|
||||||
|
|
||||||
|
You should also get your employer (if you work as a programmer) or your
|
||||||
|
school, if any, to sign a "copyright disclaimer" for the program, if
|
||||||
|
necessary. Here is a sample; alter the names:
|
||||||
|
|
||||||
|
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
|
||||||
|
`Gnomovision' (which makes passes at compilers) written by James Hacker.
|
||||||
|
|
||||||
|
<signature of Ty Coon>, 1 April 1989
|
||||||
|
Ty Coon, President of Vice
|
||||||
|
|
||||||
|
This General Public License does not permit incorporating your program into
|
||||||
|
proprietary programs. If your program is a subroutine library, you may
|
||||||
|
consider it more useful to permit linking proprietary applications with the
|
||||||
|
library. If this is what you want to do, use the GNU Lesser General
|
||||||
|
Public License instead of this License.
|
91
Makefile
Normal file
91
Makefile
Normal file
@ -0,0 +1,91 @@
|
|||||||
|
ifeq ($(strip $(DEVKITARM)),)
|
||||||
|
$(error "Please set DEVKITARM in your environment. export DEVKITARM=<path to>devkitARM")
|
||||||
|
endif
|
||||||
|
|
||||||
|
include $(DEVKITARM)/base_rules
|
||||||
|
|
||||||
|
IPL_LOAD_ADDR := 0x40008000
|
||||||
|
|
||||||
|
TARGET := Lockpick_RCM
|
||||||
|
BLVERSION_MAJOR := 1
|
||||||
|
BLVERSION_MINOR := 0
|
||||||
|
BUILD := build
|
||||||
|
OUTPUT := output
|
||||||
|
SOURCEDIR = source
|
||||||
|
VPATH = $(dir $(wildcard ./$(SOURCEDIR)/*/)) $(dir $(wildcard ./$(SOURCEDIR)/*/*/))
|
||||||
|
|
||||||
|
OBJS = $(addprefix $(BUILD)/$(TARGET)/, \
|
||||||
|
start.o \
|
||||||
|
main.o \
|
||||||
|
keys.o \
|
||||||
|
heap.o \
|
||||||
|
btn.o \
|
||||||
|
clock.o \
|
||||||
|
cluster.o \
|
||||||
|
fuse.o \
|
||||||
|
gpio.o \
|
||||||
|
sept.o \
|
||||||
|
i2c.o \
|
||||||
|
max7762x.o \
|
||||||
|
max17050.o \
|
||||||
|
mc.o \
|
||||||
|
nx_emmc.o \
|
||||||
|
sdmmc.o \
|
||||||
|
sdmmc_driver.o \
|
||||||
|
sdram.o \
|
||||||
|
sdram_lp0.o \
|
||||||
|
util.o \
|
||||||
|
di.o \
|
||||||
|
gfx.o \
|
||||||
|
pinmux.o \
|
||||||
|
pkg1.o \
|
||||||
|
pkg2.o \
|
||||||
|
se.o \
|
||||||
|
tsec.o \
|
||||||
|
hw_init.o \
|
||||||
|
smmu.o \
|
||||||
|
max77620-rtc.o \
|
||||||
|
)
|
||||||
|
|
||||||
|
OBJS += $(addprefix $(BUILD)/$(TARGET)/, \
|
||||||
|
lz.o blz.o \
|
||||||
|
diskio.o ff.o ffunicode.o ffsystem.o \
|
||||||
|
)
|
||||||
|
|
||||||
|
CUSTOMDEFINES := -DIPL_LOAD_ADDR=$(IPL_LOAD_ADDR)
|
||||||
|
|
||||||
|
ARCH := -march=armv4t -mtune=arm7tdmi -mthumb-interwork
|
||||||
|
CFLAGS = $(ARCH) -O2 -nostdlib -ffunction-sections -fdata-sections -fomit-frame-pointer -std=gnu11 -Wall $(CUSTOMDEFINES)
|
||||||
|
LDFLAGS = $(ARCH) -nostartfiles -lgcc -Wl,--nmagic,--gc-sections -Xlinker --defsym=IPL_LOAD_ADDR=$(IPL_LOAD_ADDR)
|
||||||
|
|
||||||
|
MODULEDIRS := $(wildcard modules/*)
|
||||||
|
|
||||||
|
.PHONY: all clean $(MODULEDIRS)
|
||||||
|
|
||||||
|
all: $(TARGET).bin
|
||||||
|
@echo -n "Payload size is "
|
||||||
|
@wc -c < $(OUTPUT)/$(TARGET).bin
|
||||||
|
@echo "Max size is 126296 Bytes."
|
||||||
|
|
||||||
|
clean:
|
||||||
|
@rm -rf $(OBJS)
|
||||||
|
@rm -rf $(BUILD)
|
||||||
|
@rm -rf $(OUTPUT)
|
||||||
|
|
||||||
|
$(MODULEDIRS):
|
||||||
|
$(MAKE) -C $@ $(MAKECMDGOALS)
|
||||||
|
|
||||||
|
$(TARGET).bin: $(BUILD)/$(TARGET)/$(TARGET).elf $(MODULEDIRS)
|
||||||
|
$(OBJCOPY) -S -O binary $< $(OUTPUT)/$@
|
||||||
|
|
||||||
|
$(BUILD)/$(TARGET)/$(TARGET).elf: $(OBJS)
|
||||||
|
$(CC) $(LDFLAGS) -T $(SOURCEDIR)/link.ld $^ -o $@
|
||||||
|
|
||||||
|
$(BUILD)/$(TARGET)/%.o: %.c
|
||||||
|
$(CC) $(CFLAGS) -c $< -o $@
|
||||||
|
|
||||||
|
$(BUILD)/$(TARGET)/%.o: %.S
|
||||||
|
@mkdir -p "$(BUILD)"
|
||||||
|
@mkdir -p "$(BUILD)/$(TARGET)"
|
||||||
|
@mkdir -p "$(OUTPUT)"
|
||||||
|
$(CC) $(CFLAGS) -c $< -o $@
|
23
README.md
Normal file
23
README.md
Normal file
@ -0,0 +1,23 @@
|
|||||||
|
Lockpick_RCM
|
||||||
|
=
|
||||||
|
Lockpick_RCM is a bare metal Nintendo Switch payload that derives encryption keys for use in Switch file handling software like hactool, hactoolnet/LibHac, ChoiDujour, etc. without booting Horizon OS.
|
||||||
|
|
||||||
|
Due to changes imposed by firmware 7.0.0, Lockpick homebrew can no longer derive the latest keys. In the boot-time environment however, there are fewer limitations.
|
||||||
|
|
||||||
|
Usage
|
||||||
|
=
|
||||||
|
* Launch Lockpick_RCM.bin using your favorite payload injector
|
||||||
|
* Upon completion, keys will be saved to `/switch/prod.keys` on SD
|
||||||
|
* If the console has Firmware 7.x, the `/sept/` folder from [Atmosphère](https://github.com/Atmosphere-NX/Atmosphere/releases) or [Kosmos](https://github.com/AtlasNX/Kosmos/releases) release zip containing both `sept-primary.bin` and `sept-secondary.enc` must be present on SD or else only keyblob master key derivation is possible (ie. up to `master_key_05` only)
|
||||||
|
|
||||||
|
Building
|
||||||
|
=
|
||||||
|
Install [devkitARM](https://devkitpro.org/) and run `make`.
|
||||||
|
|
||||||
|
Massive Thanks to CTCaer!
|
||||||
|
=
|
||||||
|
This software is heavily based on [Hekate](https://github.com/CTCaer/hekate). Beyond that, CTCaer was exceptionally helpful in the development of this project, lending loads of advice, expertise, and humor.
|
||||||
|
|
||||||
|
Known Issues
|
||||||
|
=
|
||||||
|
* Chainloading from SX will hang immediately due to quirks in their hwinit code, please launch payload directly
|
44
common/common_gfx.h
Normal file
44
common/common_gfx.h
Normal file
@ -0,0 +1,44 @@
|
|||||||
|
/*
|
||||||
|
* Common Gfx Header
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (C) 2018 CTCaer
|
||||||
|
* Copyright (C) 2018 M4xw
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#pragma once
|
||||||
|
//TODO: Move it to BDK
|
||||||
|
#include "../source/utils/types.h"
|
||||||
|
|
||||||
|
typedef struct _gfx_ctxt_t
|
||||||
|
{
|
||||||
|
u32 *fb;
|
||||||
|
u32 width;
|
||||||
|
u32 height;
|
||||||
|
u32 stride;
|
||||||
|
} gfx_ctxt_t;
|
||||||
|
|
||||||
|
typedef struct _gfx_con_t
|
||||||
|
{
|
||||||
|
gfx_ctxt_t *gfx_ctxt;
|
||||||
|
u32 fntsz;
|
||||||
|
u32 x;
|
||||||
|
u32 y;
|
||||||
|
u32 savedx;
|
||||||
|
u32 savedy;
|
||||||
|
u32 fgcol;
|
||||||
|
int fillbg;
|
||||||
|
u32 bgcol;
|
||||||
|
bool mute;
|
||||||
|
} gfx_con_t;
|
34
common/common_heap.h
Normal file
34
common/common_heap.h
Normal file
@ -0,0 +1,34 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (c) 2018 M4xw
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#pragma once
|
||||||
|
//TODO: Move it to BDK
|
||||||
|
#include "../source/utils/types.h"
|
||||||
|
|
||||||
|
typedef struct _hnode
|
||||||
|
{
|
||||||
|
int used;
|
||||||
|
u32 size;
|
||||||
|
struct _hnode *prev;
|
||||||
|
struct _hnode *next;
|
||||||
|
} hnode_t;
|
||||||
|
|
||||||
|
typedef struct _heap
|
||||||
|
{
|
||||||
|
u32 start;
|
||||||
|
hnode_t *first;
|
||||||
|
} heap_t;
|
262
source/gfx/di.c
Normal file
262
source/gfx/di.c
Normal file
@ -0,0 +1,262 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (c) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include "di.h"
|
||||||
|
#include "../soc/t210.h"
|
||||||
|
#include "../utils/util.h"
|
||||||
|
#include "../soc/i2c.h"
|
||||||
|
#include "../soc/pmc.h"
|
||||||
|
#include "../power/max77620.h"
|
||||||
|
#include "../power/max7762x.h"
|
||||||
|
#include "../soc/gpio.h"
|
||||||
|
#include "../soc/pinmux.h"
|
||||||
|
#include "../soc/clock.h"
|
||||||
|
|
||||||
|
#include "di.inl"
|
||||||
|
|
||||||
|
static u32 _display_ver = 0;
|
||||||
|
|
||||||
|
static void _display_dsi_wait(u32 timeout, u32 off, u32 mask)
|
||||||
|
{
|
||||||
|
u32 end = get_tmr_us() + timeout;
|
||||||
|
while (get_tmr_us() < end && DSI(off) & mask)
|
||||||
|
;
|
||||||
|
usleep(5);
|
||||||
|
}
|
||||||
|
|
||||||
|
void display_init()
|
||||||
|
{
|
||||||
|
// Power on.
|
||||||
|
max77620_regulator_set_volt_and_flags(REGULATOR_LDO0, 1200000, MAX77620_POWER_MODE_NORMAL); // Configure to 1.2V.
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO7, MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH | MAX77620_CNFG_GPIO_DRV_PUSHPULL);
|
||||||
|
|
||||||
|
// Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks.
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x1010000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = 0x1010000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = 0x18000000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = 0x20000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIP_CAL) = 0xA;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = 0x80000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = 0xA;
|
||||||
|
|
||||||
|
// DPD idle.
|
||||||
|
PMC(APBDEV_PMC_IO_DPD_REQ) = 0x40000000;
|
||||||
|
PMC(APBDEV_PMC_IO_DPD2_REQ) = 0x40000000;
|
||||||
|
|
||||||
|
// Config pins.
|
||||||
|
PINMUX_AUX(PINMUX_AUX_NFC_EN) &= ~PINMUX_TRISTATE;
|
||||||
|
PINMUX_AUX(PINMUX_AUX_NFC_INT) &= ~PINMUX_TRISTATE;
|
||||||
|
PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) &= ~PINMUX_TRISTATE;
|
||||||
|
PINMUX_AUX(PINMUX_AUX_LCD_BL_EN) &= ~PINMUX_TRISTATE;
|
||||||
|
PINMUX_AUX(PINMUX_AUX_LCD_RST) &= ~PINMUX_TRISTATE;
|
||||||
|
|
||||||
|
gpio_config(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_MODE_GPIO); // Backlight +-5V.
|
||||||
|
gpio_output_enable(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_OUTPUT_ENABLE); // Backlight +-5V.
|
||||||
|
gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_HIGH); // Backlight +5V enable.
|
||||||
|
|
||||||
|
usleep(10000);
|
||||||
|
|
||||||
|
gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_HIGH); // Backlight -5V enable.
|
||||||
|
|
||||||
|
usleep(10000);
|
||||||
|
|
||||||
|
gpio_config(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_MODE_GPIO); // Backlight PWM, Enable, Reset.
|
||||||
|
gpio_output_enable(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_OUTPUT_ENABLE);
|
||||||
|
gpio_write(GPIO_PORT_V, GPIO_PIN_1, GPIO_HIGH); // Backlight Enable enable.
|
||||||
|
|
||||||
|
// Config display interface and display.
|
||||||
|
MIPI_CAL(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0;
|
||||||
|
|
||||||
|
exec_cfg((u32 *)CLOCK_BASE, _display_config_1, 4);
|
||||||
|
exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_2, 94);
|
||||||
|
exec_cfg((u32 *)DSI_BASE, _display_config_3, 61);
|
||||||
|
|
||||||
|
usleep(10000);
|
||||||
|
|
||||||
|
gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_HIGH); // Backlight Reset enable.
|
||||||
|
|
||||||
|
usleep(60000);
|
||||||
|
|
||||||
|
DSI(_DSIREG(DSI_BTA_TIMING)) = 0x50204;
|
||||||
|
DSI(_DSIREG(DSI_WR_DATA)) = 0x337; // MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE
|
||||||
|
DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
|
||||||
|
_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
|
||||||
|
|
||||||
|
DSI(_DSIREG(DSI_WR_DATA)) = 0x406; // MIPI_DCS_GET_DISPLAY_ID
|
||||||
|
DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
|
||||||
|
_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
|
||||||
|
|
||||||
|
DSI(_DSIREG(DSI_HOST_CONTROL)) = DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
|
||||||
|
_display_dsi_wait(150000, _DSIREG(DSI_HOST_CONTROL), DSI_HOST_CONTROL_IMM_BTA);
|
||||||
|
|
||||||
|
usleep(5000);
|
||||||
|
|
||||||
|
_display_ver = DSI(_DSIREG(DSI_RD_DATA));
|
||||||
|
if (_display_ver == 0x10)
|
||||||
|
exec_cfg((u32 *)DSI_BASE, _display_config_4, 43);
|
||||||
|
|
||||||
|
DSI(_DSIREG(DSI_WR_DATA)) = 0x1105; // MIPI_DCS_EXIT_SLEEP_MODE
|
||||||
|
DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
|
||||||
|
|
||||||
|
usleep(180000);
|
||||||
|
|
||||||
|
DSI(_DSIREG(DSI_WR_DATA)) = 0x2905; // MIPI_DCS_SET_DISPLAY_ON
|
||||||
|
DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
|
||||||
|
|
||||||
|
usleep(20000);
|
||||||
|
|
||||||
|
exec_cfg((u32 *)CLOCK_BASE, _display_config_6, 3);
|
||||||
|
exec_cfg((u32 *)DSI_BASE, _display_config_5, 21);
|
||||||
|
DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4;
|
||||||
|
exec_cfg((u32 *)DSI_BASE, _display_config_7, 10);
|
||||||
|
|
||||||
|
usleep(10000);
|
||||||
|
|
||||||
|
exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_8, 6);
|
||||||
|
exec_cfg((u32 *)DSI_BASE, _display_config_9, 4);
|
||||||
|
exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_10, 16);
|
||||||
|
|
||||||
|
usleep(10000);
|
||||||
|
|
||||||
|
exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_11, 113);
|
||||||
|
}
|
||||||
|
|
||||||
|
void display_backlight_pwm_init()
|
||||||
|
{
|
||||||
|
clock_enable_pwm();
|
||||||
|
|
||||||
|
PWM(PWM_CONTROLLER_PWM_CSR) = (1 << 31); // Enable PWM
|
||||||
|
|
||||||
|
PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) >> 2) << 2 | 1; // PWM clock source.
|
||||||
|
gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight power mode.
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
void display_backlight(bool enable)
|
||||||
|
{
|
||||||
|
gpio_write(GPIO_PORT_V, GPIO_PIN_0, enable ? GPIO_HIGH : GPIO_LOW); // Backlight PWM GPIO.
|
||||||
|
}
|
||||||
|
|
||||||
|
void display_backlight_brightness(u32 brightness, u32 step_delay)
|
||||||
|
{
|
||||||
|
u32 old_value = (PWM(PWM_CONTROLLER_PWM_CSR) >> 16) & 0xFF;
|
||||||
|
if (brightness == old_value)
|
||||||
|
return;
|
||||||
|
|
||||||
|
if (brightness > 255)
|
||||||
|
brightness = 255;
|
||||||
|
|
||||||
|
if (old_value < brightness)
|
||||||
|
{
|
||||||
|
for (u32 i = old_value; i < brightness + 1; i++)
|
||||||
|
{
|
||||||
|
PWM(PWM_CONTROLLER_PWM_CSR) = (1 << 31) | (i << 16); // Enable PWM
|
||||||
|
usleep(step_delay);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
for (u32 i = old_value; i > brightness; i--)
|
||||||
|
{
|
||||||
|
PWM(PWM_CONTROLLER_PWM_CSR) = (1 << 31) | (i << 16); // Enable PWM
|
||||||
|
usleep(step_delay);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (!brightness)
|
||||||
|
PWM(PWM_CONTROLLER_PWM_CSR) = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void display_end()
|
||||||
|
{
|
||||||
|
display_backlight_brightness(0, 1000);
|
||||||
|
|
||||||
|
DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 1;
|
||||||
|
DSI(_DSIREG(DSI_WR_DATA)) = 0x2805; // MIPI_DCS_SET_DISPLAY_OFF
|
||||||
|
|
||||||
|
DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX;
|
||||||
|
DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
|
||||||
|
|
||||||
|
exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_12, 17);
|
||||||
|
exec_cfg((u32 *)DSI_BASE, _display_config_13, 16);
|
||||||
|
|
||||||
|
usleep(10000);
|
||||||
|
|
||||||
|
if (_display_ver == 0x10)
|
||||||
|
exec_cfg((u32 *)DSI_BASE, _display_config_14, 22);
|
||||||
|
|
||||||
|
DSI(_DSIREG(DSI_WR_DATA)) = 0x1005; // MIPI_DCS_ENTER_SLEEP_MODE
|
||||||
|
DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
|
||||||
|
|
||||||
|
usleep(50000);
|
||||||
|
|
||||||
|
gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_LOW); //Backlight Reset disable.
|
||||||
|
|
||||||
|
usleep(10000);
|
||||||
|
|
||||||
|
gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_LOW); //Backlight -5V disable.
|
||||||
|
|
||||||
|
usleep(10000);
|
||||||
|
|
||||||
|
gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_LOW); //Backlight +5V disable.
|
||||||
|
|
||||||
|
usleep(10000);
|
||||||
|
|
||||||
|
// Disable clocks.
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x1010000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_CLR) = 0x1010000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = 0x18000000;
|
||||||
|
|
||||||
|
DSI(_DSIREG(DSI_PAD_CONTROL_0)) = DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF);
|
||||||
|
DSI(_DSIREG(DSI_POWER_CONTROL)) = 0;
|
||||||
|
|
||||||
|
gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight PWM.
|
||||||
|
|
||||||
|
PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_TRISTATE) | PINMUX_TRISTATE;
|
||||||
|
PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) >> 2) << 2 | 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void display_color_screen(u32 color)
|
||||||
|
{
|
||||||
|
exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_one_color, 8);
|
||||||
|
|
||||||
|
// Configure display to show single color.
|
||||||
|
DISPLAY_A(_DIREG(DC_WIN_AD_WIN_OPTIONS)) = 0;
|
||||||
|
DISPLAY_A(_DIREG(DC_WIN_BD_WIN_OPTIONS)) = 0;
|
||||||
|
DISPLAY_A(_DIREG(DC_WIN_CD_WIN_OPTIONS)) = 0;
|
||||||
|
DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color;
|
||||||
|
DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = (DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE) | GENERAL_ACT_REQ;
|
||||||
|
|
||||||
|
usleep(35000);
|
||||||
|
|
||||||
|
display_backlight(true);
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 *display_init_framebuffer()
|
||||||
|
{
|
||||||
|
// Sanitize framebuffer area.
|
||||||
|
memset((u32 *)0xC0000000, 0, 0x3C0000);
|
||||||
|
// This configures the framebuffer @ 0xC0000000 with a resolution of 1280x720 (line stride 768).
|
||||||
|
exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer, 32);
|
||||||
|
|
||||||
|
usleep(35000);
|
||||||
|
|
||||||
|
return (u32 *)0xC0000000;
|
||||||
|
}
|
370
source/gfx/di.h
Normal file
370
source/gfx/di.h
Normal file
@ -0,0 +1,370 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (C) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _DI_H_
|
||||||
|
#define _DI_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
/*! Display registers. */
|
||||||
|
#define _DIREG(reg) ((reg) * 4)
|
||||||
|
|
||||||
|
#define DC_CMD_GENERAL_INCR_SYNCPT 0x00
|
||||||
|
|
||||||
|
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01
|
||||||
|
#define SYNCPT_CNTRL_NO_STALL (1 << 8)
|
||||||
|
#define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
|
||||||
|
|
||||||
|
#define DC_CMD_CONT_SYNCPT_VSYNC 0x28
|
||||||
|
#define SYNCPT_VSYNC_ENABLE (1 << 8)
|
||||||
|
|
||||||
|
#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
|
||||||
|
|
||||||
|
#define DC_CMD_DISPLAY_COMMAND 0x32
|
||||||
|
#define DISP_CTRL_MODE_STOP (0 << 5)
|
||||||
|
#define DISP_CTRL_MODE_C_DISPLAY (1 << 5)
|
||||||
|
#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
|
||||||
|
#define DISP_CTRL_MODE_MASK (3 << 5)
|
||||||
|
|
||||||
|
#define DC_CMD_DISPLAY_POWER_CONTROL 0x36
|
||||||
|
#define PW0_ENABLE (1 << 0)
|
||||||
|
#define PW1_ENABLE (1 << 2)
|
||||||
|
#define PW2_ENABLE (1 << 4)
|
||||||
|
#define PW3_ENABLE (1 << 6)
|
||||||
|
#define PW4_ENABLE (1 << 8)
|
||||||
|
#define PM0_ENABLE (1 << 16)
|
||||||
|
#define PM1_ENABLE (1 << 18)
|
||||||
|
|
||||||
|
#define DC_CMD_INT_MASK 0x38
|
||||||
|
#define DC_CMD_INT_ENABLE 0x39
|
||||||
|
|
||||||
|
#define DC_CMD_STATE_ACCESS 0x40
|
||||||
|
#define READ_MUX (1 << 0)
|
||||||
|
#define WRITE_MUX (1 << 2)
|
||||||
|
|
||||||
|
#define DC_CMD_STATE_CONTROL 0x41
|
||||||
|
#define GENERAL_ACT_REQ (1 << 0)
|
||||||
|
#define WIN_A_ACT_REQ (1 << 1)
|
||||||
|
#define WIN_B_ACT_REQ (1 << 2)
|
||||||
|
#define WIN_C_ACT_REQ (1 << 3)
|
||||||
|
#define CURSOR_ACT_REQ (1 << 7)
|
||||||
|
#define GENERAL_UPDATE (1 << 8)
|
||||||
|
#define WIN_A_UPDATE (1 << 9)
|
||||||
|
#define WIN_B_UPDATE (1 << 10)
|
||||||
|
#define WIN_C_UPDATE (1 << 11)
|
||||||
|
#define CURSOR_UPDATE (1 << 15)
|
||||||
|
#define NC_HOST_TRIG (1 << 24)
|
||||||
|
|
||||||
|
#define DC_CMD_DISPLAY_WINDOW_HEADER 0x42
|
||||||
|
#define WINDOW_A_SELECT (1 << 4)
|
||||||
|
#define WINDOW_B_SELECT (1 << 5)
|
||||||
|
#define WINDOW_C_SELECT (1 << 6)
|
||||||
|
|
||||||
|
#define DC_CMD_REG_ACT_CONTROL 0x043
|
||||||
|
|
||||||
|
#define DC_COM_CRC_CONTROL 0x300
|
||||||
|
#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
|
||||||
|
#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
|
||||||
|
|
||||||
|
#define DC_COM_DSC_TOP_CTL 0x33E
|
||||||
|
|
||||||
|
#define DC_DISP_DISP_WIN_OPTIONS 0x402
|
||||||
|
#define HDMI_ENABLE (1 << 30)
|
||||||
|
#define DSI_ENABLE (1 << 29)
|
||||||
|
#define SOR1_TIMING_CYA (1 << 27)
|
||||||
|
#define SOR1_ENABLE (1 << 26)
|
||||||
|
#define SOR_ENABLE (1 << 25)
|
||||||
|
#define CURSOR_ENABLE (1 << 16)
|
||||||
|
|
||||||
|
#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
|
||||||
|
#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
|
||||||
|
#define DC_DISP_DISP_TIMING_OPTIONS 0x405
|
||||||
|
#define DC_DISP_REF_TO_SYNC 0x406
|
||||||
|
#define DC_DISP_SYNC_WIDTH 0x407
|
||||||
|
#define DC_DISP_BACK_PORCH 0x408
|
||||||
|
#define DC_DISP_ACTIVE 0x409
|
||||||
|
#define DC_DISP_FRONT_PORCH 0x40A
|
||||||
|
|
||||||
|
#define DC_DISP_DISP_CLOCK_CONTROL 0x42E
|
||||||
|
#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
|
||||||
|
#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
|
||||||
|
#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
|
||||||
|
#define PIXEL_CLK_DIVIDER_PCD3 (3 << 8)
|
||||||
|
#define PIXEL_CLK_DIVIDER_PCD4 (4 << 8)
|
||||||
|
#define PIXEL_CLK_DIVIDER_PCD6 (5 << 8)
|
||||||
|
#define PIXEL_CLK_DIVIDER_PCD8 (6 << 8)
|
||||||
|
#define PIXEL_CLK_DIVIDER_PCD9 (7 << 8)
|
||||||
|
#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
|
||||||
|
#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
|
||||||
|
#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
|
||||||
|
#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
|
||||||
|
#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
|
||||||
|
#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
|
||||||
|
|
||||||
|
#define DC_DISP_DISP_INTERFACE_CONTROL 0x42F
|
||||||
|
#define DISP_DATA_FORMAT_DF1P1C (0 << 0)
|
||||||
|
#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
|
||||||
|
#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
|
||||||
|
#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
|
||||||
|
#define DISP_DATA_FORMAT_DF2S (4 << 0)
|
||||||
|
#define DISP_DATA_FORMAT_DF3S (5 << 0)
|
||||||
|
#define DISP_DATA_FORMAT_DFSPI (6 << 0)
|
||||||
|
#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
|
||||||
|
#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
|
||||||
|
#define DISP_ALIGNMENT_MSB (0 << 8)
|
||||||
|
#define DISP_ALIGNMENT_LSB (1 << 8)
|
||||||
|
#define DISP_ORDER_RED_BLUE (0 << 9)
|
||||||
|
#define DISP_ORDER_BLUE_RED (1 << 9)
|
||||||
|
|
||||||
|
#define DC_DISP_DISP_COLOR_CONTROL 0x430
|
||||||
|
#define DITHER_CONTROL_MASK (3 << 8)
|
||||||
|
#define DITHER_CONTROL_DISABLE (0 << 8)
|
||||||
|
#define DITHER_CONTROL_ORDERED (2 << 8)
|
||||||
|
#define DITHER_CONTROL_ERRDIFF (3 << 8)
|
||||||
|
#define BASE_COLOR_SIZE_MASK (0xf << 0)
|
||||||
|
#define BASE_COLOR_SIZE_666 (0 << 0)
|
||||||
|
#define BASE_COLOR_SIZE_111 (1 << 0)
|
||||||
|
#define BASE_COLOR_SIZE_222 (2 << 0)
|
||||||
|
#define BASE_COLOR_SIZE_333 (3 << 0)
|
||||||
|
#define BASE_COLOR_SIZE_444 (4 << 0)
|
||||||
|
#define BASE_COLOR_SIZE_555 (5 << 0)
|
||||||
|
#define BASE_COLOR_SIZE_565 (6 << 0)
|
||||||
|
#define BASE_COLOR_SIZE_332 (7 << 0)
|
||||||
|
#define BASE_COLOR_SIZE_888 (8 << 0)
|
||||||
|
|
||||||
|
#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
|
||||||
|
#define SC1_H_QUALIFIER_NONE (1 << 16)
|
||||||
|
#define SC0_H_QUALIFIER_NONE (1 << 0)
|
||||||
|
|
||||||
|
#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
|
||||||
|
#define DE_SELECT_ACTIVE_BLANK (0 << 0)
|
||||||
|
#define DE_SELECT_ACTIVE (1 << 0)
|
||||||
|
#define DE_SELECT_ACTIVE_IS (2 << 0)
|
||||||
|
#define DE_CONTROL_ONECLK (0 << 2)
|
||||||
|
#define DE_CONTROL_NORMAL (1 << 2)
|
||||||
|
#define DE_CONTROL_EARLY_EXT (2 << 2)
|
||||||
|
#define DE_CONTROL_EARLY (3 << 2)
|
||||||
|
#define DE_CONTROL_ACTIVE_BLANK (4 << 2)
|
||||||
|
|
||||||
|
#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
|
||||||
|
#define DC_DISP_SD_BL_PARAMETERS 0x4D7
|
||||||
|
#define DC_DISP_SD_BL_CONTROL 0x4DC
|
||||||
|
#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4
|
||||||
|
|
||||||
|
#define DC_WIN_CSC_YOF 0x611
|
||||||
|
#define DC_WIN_CSC_KYRGB 0x612
|
||||||
|
#define DC_WIN_CSC_KUR 0x613
|
||||||
|
#define DC_WIN_CSC_KVR 0x614
|
||||||
|
#define DC_WIN_CSC_KUG 0x615
|
||||||
|
#define DC_WIN_CSC_KVG 0x616
|
||||||
|
#define DC_WIN_CSC_KUB 0x617
|
||||||
|
#define DC_WIN_CSC_KVB 0x618
|
||||||
|
#define DC_WIN_AD_WIN_OPTIONS 0xB80
|
||||||
|
#define DC_WIN_BD_WIN_OPTIONS 0xD80
|
||||||
|
#define DC_WIN_CD_WIN_OPTIONS 0xF80
|
||||||
|
|
||||||
|
// The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER).
|
||||||
|
#define DC_WIN_WIN_OPTIONS 0x700
|
||||||
|
#define H_DIRECTION (1 << 0)
|
||||||
|
#define V_DIRECTION (1 << 2)
|
||||||
|
#define SCAN_COLUMN (1 << 4)
|
||||||
|
#define COLOR_EXPAND (1 << 6)
|
||||||
|
#define CSC_ENABLE (1 << 18)
|
||||||
|
#define WIN_ENABLE (1 << 30)
|
||||||
|
|
||||||
|
#define DC_WIN_COLOR_DEPTH 0x703
|
||||||
|
#define WIN_COLOR_DEPTH_P1 0x0
|
||||||
|
#define WIN_COLOR_DEPTH_P2 0x1
|
||||||
|
#define WIN_COLOR_DEPTH_P4 0x2
|
||||||
|
#define WIN_COLOR_DEPTH_P8 0x3
|
||||||
|
#define WIN_COLOR_DEPTH_B4G4R4A4 0x4
|
||||||
|
#define WIN_COLOR_DEPTH_B5G5R5A 0x5
|
||||||
|
#define WIN_COLOR_DEPTH_B5G6R5 0x6
|
||||||
|
#define WIN_COLOR_DEPTH_AB5G5R5 0x7
|
||||||
|
#define WIN_COLOR_DEPTH_B8G8R8A8 0xC
|
||||||
|
#define WIN_COLOR_DEPTH_R8G8B8A8 0xD
|
||||||
|
#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 0xE
|
||||||
|
#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 0xF
|
||||||
|
#define WIN_COLOR_DEPTH_YCbCr422 0x10
|
||||||
|
#define WIN_COLOR_DEPTH_YUV422 0x11
|
||||||
|
#define WIN_COLOR_DEPTH_YCbCr420P 0x12
|
||||||
|
#define WIN_COLOR_DEPTH_YUV420P 0x13
|
||||||
|
#define WIN_COLOR_DEPTH_YCbCr422P 0x14
|
||||||
|
#define WIN_COLOR_DEPTH_YUV422P 0x15
|
||||||
|
#define WIN_COLOR_DEPTH_YCbCr422R 0x16
|
||||||
|
#define WIN_COLOR_DEPTH_YUV422R 0x17
|
||||||
|
#define WIN_COLOR_DEPTH_YCbCr422RA 0x18
|
||||||
|
#define WIN_COLOR_DEPTH_YUV422RA 0x19
|
||||||
|
|
||||||
|
#define DC_WIN_BUFFER_CONTROL 0x702
|
||||||
|
#define DC_WIN_POSITION 0x704
|
||||||
|
|
||||||
|
#define DC_WIN_SIZE 0x705
|
||||||
|
#define H_SIZE(x) (((x) & 0x1fff) << 0)
|
||||||
|
#define V_SIZE(x) (((x) & 0x1fff) << 16)
|
||||||
|
|
||||||
|
#define DC_WIN_PRESCALED_SIZE 0x706
|
||||||
|
#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
|
||||||
|
#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16)
|
||||||
|
|
||||||
|
#define DC_WIN_H_INITIAL_DDA 0x707
|
||||||
|
#define DC_WIN_V_INITIAL_DDA 0x708
|
||||||
|
|
||||||
|
#define DC_WIN_DDA_INC 0x709
|
||||||
|
#define H_DDA_INC(x) (((x) & 0xffff) << 0)
|
||||||
|
#define V_DDA_INC(x) (((x) & 0xffff) << 16)
|
||||||
|
|
||||||
|
#define DC_WIN_LINE_STRIDE 0x70A
|
||||||
|
#define LINE_STRIDE(x) (x)
|
||||||
|
#define UV_LINE_STRIDE(x) (((x) & 0xffff) << 16)
|
||||||
|
#define DC_WIN_DV_CONTROL 0x70E
|
||||||
|
|
||||||
|
// The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER).
|
||||||
|
#define DC_WINBUF_START_ADDR 0x800
|
||||||
|
#define DC_WINBUF_ADDR_H_OFFSET 0x806
|
||||||
|
#define DC_WINBUF_ADDR_V_OFFSET 0x808
|
||||||
|
#define DC_WINBUF_SURFACE_KIND 0x80B
|
||||||
|
#define PITCH (0 << 0)
|
||||||
|
#define TILED (1 << 0)
|
||||||
|
#define BLOCK (2 << 0)
|
||||||
|
#define BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
|
||||||
|
|
||||||
|
/*! Display serial interface registers. */
|
||||||
|
#define _DSIREG(reg) ((reg) * 4)
|
||||||
|
|
||||||
|
#define DSI_RD_DATA 0x9
|
||||||
|
#define DSI_WR_DATA 0xA
|
||||||
|
|
||||||
|
#define DSI_POWER_CONTROL 0xB
|
||||||
|
#define DSI_POWER_CONTROL_ENABLE 1
|
||||||
|
|
||||||
|
#define DSI_INT_ENABLE 0xC
|
||||||
|
#define DSI_INT_STATUS 0xD
|
||||||
|
#define DSI_INT_MASK 0xE
|
||||||
|
|
||||||
|
#define DSI_HOST_CONTROL 0xF
|
||||||
|
#define DSI_HOST_CONTROL_FIFO_RESET (1 << 21)
|
||||||
|
#define DSI_HOST_CONTROL_CRC_RESET (1 << 20)
|
||||||
|
#define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12)
|
||||||
|
#define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12)
|
||||||
|
#define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12)
|
||||||
|
#define DSI_HOST_CONTROL_RAW (1 << 6)
|
||||||
|
#define DSI_HOST_CONTROL_HS (1 << 5)
|
||||||
|
#define DSI_HOST_CONTROL_FIFO_SEL (1 << 4)
|
||||||
|
#define DSI_HOST_CONTROL_IMM_BTA (1 << 3)
|
||||||
|
#define DSI_HOST_CONTROL_PKT_BTA (1 << 2)
|
||||||
|
#define DSI_HOST_CONTROL_CS (1 << 1)
|
||||||
|
#define DSI_HOST_CONTROL_ECC (1 << 0)
|
||||||
|
|
||||||
|
#define DSI_CONTROL 0x10
|
||||||
|
#define DSI_CONTROL_HS_CLK_CTRL (1 << 20)
|
||||||
|
#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16)
|
||||||
|
#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12)
|
||||||
|
#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8)
|
||||||
|
#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4)
|
||||||
|
#define DSI_CONTROL_DCS_ENABLE (1 << 3)
|
||||||
|
#define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2)
|
||||||
|
#define DSI_CONTROL_VIDEO_ENABLE (1 << 1)
|
||||||
|
#define DSI_CONTROL_HOST_ENABLE (1 << 0)
|
||||||
|
|
||||||
|
#define DSI_SOL_DELAY 0x11
|
||||||
|
#define DSI_MAX_THRESHOLD 0x12
|
||||||
|
|
||||||
|
#define DSI_TRIGGER 0x13
|
||||||
|
#define DSI_TRIGGER_HOST (1 << 1)
|
||||||
|
#define DSI_TRIGGER_VIDEO (1 << 0)
|
||||||
|
|
||||||
|
#define DSI_TX_CRC 0x14
|
||||||
|
#define DSI_STATUS 0x15
|
||||||
|
#define DSI_INIT_SEQ_CONTROL 0x1A
|
||||||
|
#define DSI_INIT_SEQ_DATA_0 0x1B
|
||||||
|
#define DSI_INIT_SEQ_DATA_1 0x1C
|
||||||
|
#define DSI_INIT_SEQ_DATA_2 0x1D
|
||||||
|
#define DSI_INIT_SEQ_DATA_3 0x1E
|
||||||
|
#define DSI_PKT_SEQ_0_LO 0x23
|
||||||
|
#define DSI_PKT_SEQ_0_HI 0x24
|
||||||
|
#define DSI_PKT_SEQ_1_LO 0x25
|
||||||
|
#define DSI_PKT_SEQ_1_HI 0x26
|
||||||
|
#define DSI_PKT_SEQ_2_LO 0x27
|
||||||
|
#define DSI_PKT_SEQ_2_HI 0x28
|
||||||
|
#define DSI_PKT_SEQ_3_LO 0x29
|
||||||
|
#define DSI_PKT_SEQ_3_HI 0x2A
|
||||||
|
#define DSI_PKT_SEQ_4_LO 0x2B
|
||||||
|
#define DSI_PKT_SEQ_4_HI 0x2C
|
||||||
|
#define DSI_PKT_SEQ_5_LO 0x2D
|
||||||
|
#define DSI_PKT_SEQ_5_HI 0x2E
|
||||||
|
#define DSI_DCS_CMDS 0x33
|
||||||
|
#define DSI_PKT_LEN_0_1 0x34
|
||||||
|
#define DSI_PKT_LEN_2_3 0x35
|
||||||
|
#define DSI_PKT_LEN_4_5 0x36
|
||||||
|
#define DSI_PKT_LEN_6_7 0x37
|
||||||
|
#define DSI_PHY_TIMING_0 0x3C
|
||||||
|
#define DSI_PHY_TIMING_1 0x3D
|
||||||
|
#define DSI_PHY_TIMING_2 0x3E
|
||||||
|
#define DSI_BTA_TIMING 0x3F
|
||||||
|
|
||||||
|
#define DSI_TIMEOUT_0 0x44
|
||||||
|
#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
|
||||||
|
#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0)
|
||||||
|
|
||||||
|
#define DSI_TIMEOUT_1 0x45
|
||||||
|
#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
|
||||||
|
#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0)
|
||||||
|
|
||||||
|
#define DSI_TO_TALLY 0x46
|
||||||
|
|
||||||
|
#define DSI_PAD_CONTROL_0 0x4B
|
||||||
|
#define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24)
|
||||||
|
#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16)
|
||||||
|
#define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8)
|
||||||
|
#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0)
|
||||||
|
|
||||||
|
#define DSI_PAD_CONTROL_CD 0x4c
|
||||||
|
#define DSI_VIDEO_MODE_CONTROL 0x4E
|
||||||
|
|
||||||
|
#define DSI_PAD_CONTROL_1 0x4F
|
||||||
|
#define DSI_PAD_CONTROL_2 0x50
|
||||||
|
|
||||||
|
#define DSI_PAD_CONTROL_3 0x51
|
||||||
|
#define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
|
||||||
|
#define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
|
||||||
|
#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4)
|
||||||
|
#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0)
|
||||||
|
|
||||||
|
#define DSI_PAD_CONTROL_4 0x52
|
||||||
|
#define DSI_INIT_SEQ_DATA_15 0x5F
|
||||||
|
|
||||||
|
#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 0x60
|
||||||
|
|
||||||
|
/*! Display backlight related PWM registers. */
|
||||||
|
#define PWM_CONTROLLER_PWM_CSR 0x00
|
||||||
|
|
||||||
|
void display_init();
|
||||||
|
void display_backlight_pwm_init();
|
||||||
|
void display_end();
|
||||||
|
|
||||||
|
/*! Show one single color on the display. */
|
||||||
|
void display_color_screen(u32 color);
|
||||||
|
|
||||||
|
/*! Switches screen backlight ON/OFF. */
|
||||||
|
void display_backlight(bool enable);
|
||||||
|
void display_backlight_brightness(u32 brightness, u32 step_delay);
|
||||||
|
|
||||||
|
/*! Init display in full 1280x720 resolution (B8G8R8A8, line stride 768, framebuffer size = 1280*768*4 bytes). */
|
||||||
|
u32 *display_init_framebuffer();
|
||||||
|
|
||||||
|
#endif
|
564
source/gfx/di.inl
Normal file
564
source/gfx/di.inl
Normal file
@ -0,0 +1,564 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (C) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
//Clock config.
|
||||||
|
static const cfg_op_t _display_config_1[4] = {
|
||||||
|
{0x4E, 0x40000000}, //CLK_RST_CONTROLLER_CLK_SOURCE_DISP1
|
||||||
|
{0x34, 0x4830A001}, //CLK_RST_CONTROLLER_PLLD_BASE
|
||||||
|
{0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1
|
||||||
|
{0x37, 0x2D0AAA} //CLK_RST_CONTROLLER_PLLD_MISC
|
||||||
|
};
|
||||||
|
|
||||||
|
//Display A config.
|
||||||
|
static const cfg_op_t _display_config_2[94] = {
|
||||||
|
{DC_CMD_STATE_ACCESS, 0},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||||
|
{DC_CMD_REG_ACT_CONTROL, 0x54},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||||
|
{DC_DISP_DC_MCCIF_FIFOCTRL, 0},
|
||||||
|
{DC_DISP_DISP_MEM_HIGH_PRIORITY, 0},
|
||||||
|
{DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0},
|
||||||
|
{DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE},
|
||||||
|
{DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL},
|
||||||
|
{DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, // 9: SYNCPT
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
|
||||||
|
{DC_CMD_STATE_ACCESS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||||
|
{DC_WIN_DV_CONTROL, 0},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||||
|
/* Setup default YUV colorspace conversion coefficients */
|
||||||
|
{DC_WIN_CSC_YOF, 0xF0},
|
||||||
|
{DC_WIN_CSC_KYRGB, 0x12A},
|
||||||
|
{DC_WIN_CSC_KUR, 0},
|
||||||
|
{DC_WIN_CSC_KVR, 0x198},
|
||||||
|
{DC_WIN_CSC_KUG, 0x39B},
|
||||||
|
{DC_WIN_CSC_KVG, 0x32F},
|
||||||
|
{DC_WIN_CSC_KUB, 0x204},
|
||||||
|
{DC_WIN_CSC_KVB, 0},
|
||||||
|
/* End of color coefficients */
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||||
|
{DC_WIN_DV_CONTROL, 0},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||||
|
/* Setup default YUV colorspace conversion coefficients */
|
||||||
|
{DC_WIN_CSC_YOF, 0xF0},
|
||||||
|
{DC_WIN_CSC_KYRGB, 0x12A},
|
||||||
|
{DC_WIN_CSC_KUR, 0},
|
||||||
|
{DC_WIN_CSC_KVR, 0x198},
|
||||||
|
{DC_WIN_CSC_KUG, 0x39B},
|
||||||
|
{DC_WIN_CSC_KVG, 0x32F},
|
||||||
|
{DC_WIN_CSC_KUB, 0x204},
|
||||||
|
{DC_WIN_CSC_KVB, 0},
|
||||||
|
/* End of color coefficients */
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||||
|
{DC_WIN_DV_CONTROL, 0},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||||
|
/* Setup default YUV colorspace conversion coefficients */
|
||||||
|
{DC_WIN_CSC_YOF, 0xF0},
|
||||||
|
{DC_WIN_CSC_KYRGB, 0x12A},
|
||||||
|
{DC_WIN_CSC_KUR, 0},
|
||||||
|
{DC_WIN_CSC_KVR, 0x198},
|
||||||
|
{DC_WIN_CSC_KUG, 0x39B},
|
||||||
|
{DC_WIN_CSC_KVG, 0x32F},
|
||||||
|
{DC_WIN_CSC_KUB, 0x204},
|
||||||
|
{DC_WIN_CSC_KVB, 0},
|
||||||
|
/* End of color coefficients */
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
|
||||||
|
{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
|
||||||
|
{DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
|
||||||
|
{DC_COM_PIN_OUTPUT_POLARITY(3), 0},
|
||||||
|
{0x4E4, 0},
|
||||||
|
{DC_COM_CRC_CONTROL, 0},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||||
|
{0x716, 0x10000FF},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||||
|
{0x716, 0x10000FF},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||||
|
{0x716, 0x10000FF},
|
||||||
|
{DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_DISP_DISP_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_COMMAND, 0},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}
|
||||||
|
};
|
||||||
|
|
||||||
|
//DSI Init config.
|
||||||
|
static const cfg_op_t _display_config_3[61] = {
|
||||||
|
{DSI_WR_DATA, 0},
|
||||||
|
{DSI_INT_ENABLE, 0},
|
||||||
|
{DSI_INT_STATUS, 0},
|
||||||
|
{DSI_INT_MASK, 0},
|
||||||
|
{DSI_INIT_SEQ_DATA_0, 0},
|
||||||
|
{DSI_INIT_SEQ_DATA_1, 0},
|
||||||
|
{DSI_INIT_SEQ_DATA_2, 0},
|
||||||
|
{DSI_INIT_SEQ_DATA_3, 0},
|
||||||
|
{DSI_INIT_SEQ_DATA_15, 0},
|
||||||
|
{DSI_DCS_CMDS, 0},
|
||||||
|
{DSI_PKT_SEQ_0_LO, 0},
|
||||||
|
{DSI_PKT_SEQ_1_LO, 0},
|
||||||
|
{DSI_PKT_SEQ_2_LO, 0},
|
||||||
|
{DSI_PKT_SEQ_3_LO, 0},
|
||||||
|
{DSI_PKT_SEQ_4_LO, 0},
|
||||||
|
{DSI_PKT_SEQ_5_LO, 0},
|
||||||
|
{DSI_PKT_SEQ_0_HI, 0},
|
||||||
|
{DSI_PKT_SEQ_1_HI, 0},
|
||||||
|
{DSI_PKT_SEQ_2_HI, 0},
|
||||||
|
{DSI_PKT_SEQ_3_HI, 0},
|
||||||
|
{DSI_PKT_SEQ_4_HI, 0},
|
||||||
|
{DSI_PKT_SEQ_5_HI, 0},
|
||||||
|
{DSI_CONTROL, 0},
|
||||||
|
{DSI_PAD_CONTROL_CD, 0},
|
||||||
|
{DSI_SOL_DELAY, 0x18},
|
||||||
|
{DSI_MAX_THRESHOLD, 0x1E0},
|
||||||
|
{DSI_TRIGGER, 0},
|
||||||
|
{DSI_INIT_SEQ_CONTROL, 0},
|
||||||
|
{DSI_PKT_LEN_0_1, 0},
|
||||||
|
{DSI_PKT_LEN_2_3, 0},
|
||||||
|
{DSI_PKT_LEN_4_5, 0},
|
||||||
|
{DSI_PKT_LEN_6_7, 0},
|
||||||
|
{DSI_PAD_CONTROL_1, 0},
|
||||||
|
{DSI_PHY_TIMING_0, 0x6070601},
|
||||||
|
{DSI_PHY_TIMING_1, 0x40A0E05},
|
||||||
|
{DSI_PHY_TIMING_2, 0x30109},
|
||||||
|
{DSI_BTA_TIMING, 0x190A14},
|
||||||
|
{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
|
||||||
|
{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)},
|
||||||
|
{DSI_TO_TALLY, 0},
|
||||||
|
{DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, // Enable
|
||||||
|
{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
|
||||||
|
{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
|
||||||
|
{DSI_POWER_CONTROL, 0},
|
||||||
|
{DSI_POWER_CONTROL, 0},
|
||||||
|
{DSI_PAD_CONTROL_1, 0},
|
||||||
|
{DSI_PHY_TIMING_0, 0x6070601},
|
||||||
|
{DSI_PHY_TIMING_1, 0x40A0E05},
|
||||||
|
{DSI_PHY_TIMING_2, 0x30118},
|
||||||
|
{DSI_BTA_TIMING, 0x190A14},
|
||||||
|
{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
|
||||||
|
{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)},
|
||||||
|
{DSI_TO_TALLY, 0},
|
||||||
|
{DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
|
||||||
|
{DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
|
||||||
|
{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
|
||||||
|
{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
|
||||||
|
{DSI_MAX_THRESHOLD, 0x40},
|
||||||
|
{DSI_TRIGGER, 0},
|
||||||
|
{DSI_TX_CRC, 0},
|
||||||
|
{DSI_INIT_SEQ_CONTROL, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
//DSI config (if ver == 0x10).
|
||||||
|
static const cfg_op_t _display_config_4[43] = {
|
||||||
|
{DSI_WR_DATA, 0x439},
|
||||||
|
{DSI_WR_DATA, 0x9483FFB9},
|
||||||
|
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||||
|
{DSI_WR_DATA, 0xBD15},
|
||||||
|
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||||
|
{DSI_WR_DATA, 0x1939},
|
||||||
|
{DSI_WR_DATA, 0xAAAAAAD8},
|
||||||
|
{DSI_WR_DATA, 0xAAAAAAEB},
|
||||||
|
{DSI_WR_DATA, 0xAAEBAAAA},
|
||||||
|
{DSI_WR_DATA, 0xAAAAAAAA},
|
||||||
|
{DSI_WR_DATA, 0xAAAAAAEB},
|
||||||
|
{DSI_WR_DATA, 0xAAEBAAAA},
|
||||||
|
{DSI_WR_DATA, 0xAA},
|
||||||
|
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||||
|
{DSI_WR_DATA, 0x1BD15},
|
||||||
|
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||||
|
{DSI_WR_DATA, 0x2739},
|
||||||
|
{DSI_WR_DATA, 0xFFFFFFD8},
|
||||||
|
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||||
|
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||||
|
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||||
|
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||||
|
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||||
|
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||||
|
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||||
|
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||||
|
{DSI_WR_DATA, 0xFFFFFF},
|
||||||
|
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||||
|
{DSI_WR_DATA, 0x2BD15},
|
||||||
|
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||||
|
{DSI_WR_DATA, 0xF39},
|
||||||
|
{DSI_WR_DATA, 0xFFFFFFD8},
|
||||||
|
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||||
|
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||||
|
{DSI_WR_DATA, 0xFFFFFF},
|
||||||
|
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||||
|
{DSI_WR_DATA, 0xBD15},
|
||||||
|
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||||
|
{DSI_WR_DATA, 0x6D915},
|
||||||
|
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||||
|
{DSI_WR_DATA, 0x439},
|
||||||
|
{DSI_WR_DATA, 0xB9},
|
||||||
|
{DSI_TRIGGER, DSI_TRIGGER_HOST}
|
||||||
|
};
|
||||||
|
|
||||||
|
//DSI config.
|
||||||
|
static const cfg_op_t _display_config_5[21] = {
|
||||||
|
{DSI_PAD_CONTROL_1, 0},
|
||||||
|
{DSI_PHY_TIMING_0, 0x6070601},
|
||||||
|
{DSI_PHY_TIMING_1, 0x40A0E05},
|
||||||
|
{DSI_PHY_TIMING_2, 0x30172},
|
||||||
|
{DSI_BTA_TIMING, 0x190A14},
|
||||||
|
{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)},
|
||||||
|
{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)},
|
||||||
|
{DSI_TO_TALLY, 0},
|
||||||
|
{DSI_PKT_SEQ_0_LO, 0x40000208},
|
||||||
|
{DSI_PKT_SEQ_2_LO, 0x40000308},
|
||||||
|
{DSI_PKT_SEQ_4_LO, 0x40000308},
|
||||||
|
{DSI_PKT_SEQ_1_LO, 0x40000308},
|
||||||
|
{DSI_PKT_SEQ_3_LO, 0x3F3B2B08},
|
||||||
|
{DSI_PKT_SEQ_3_HI, 0x2CC},
|
||||||
|
{DSI_PKT_SEQ_5_LO, 0x3F3B2B08},
|
||||||
|
{DSI_PKT_SEQ_5_HI, 0x2CC},
|
||||||
|
{DSI_PKT_LEN_0_1, 0xCE0000},
|
||||||
|
{DSI_PKT_LEN_2_3, 0x87001A2},
|
||||||
|
{DSI_PKT_LEN_4_5, 0x190},
|
||||||
|
{DSI_PKT_LEN_6_7, 0x190},
|
||||||
|
{DSI_HOST_CONTROL, 0},
|
||||||
|
};
|
||||||
|
|
||||||
|
//Clock config.
|
||||||
|
static const cfg_op_t _display_config_6[3] = {
|
||||||
|
{0x34, 0x4810C001}, //CLK_RST_CONTROLLER_PLLD_BASE
|
||||||
|
{0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1
|
||||||
|
{0x37, 0x2DFC00} //CLK_RST_CONTROLLER_PLLD_MISC
|
||||||
|
};
|
||||||
|
|
||||||
|
//DSI config.
|
||||||
|
static const cfg_op_t _display_config_7[10] = {
|
||||||
|
{DSI_TRIGGER, 0},
|
||||||
|
{DSI_CONTROL, 0},
|
||||||
|
{DSI_SOL_DELAY, 6},
|
||||||
|
{DSI_MAX_THRESHOLD, 0x1E0},
|
||||||
|
{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
|
||||||
|
{DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
|
||||||
|
{DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
|
||||||
|
{DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
|
||||||
|
{DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
|
||||||
|
{DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}
|
||||||
|
};
|
||||||
|
|
||||||
|
//MIPI CAL config.
|
||||||
|
static const cfg_op_t _display_config_8[6] = {
|
||||||
|
{0x18, 0}, // MIPI_CAL_MIPI_BIAS_PAD_CFG2
|
||||||
|
{0x02, 0xF3F10000}, // MIPI_CAL_CIL_MIPI_CAL_STATUS
|
||||||
|
{0x16, 0}, // MIPI_CAL_MIPI_BIAS_PAD_CFG0
|
||||||
|
{0x18, 0}, // MIPI_CAL_MIPI_BIAS_PAD_CFG2
|
||||||
|
{0x18, 0x10010}, // MIPI_CAL_MIPI_BIAS_PAD_CFG2
|
||||||
|
{0x17, 0x300} // MIPI_CAL_MIPI_BIAS_PAD_CFG1
|
||||||
|
};
|
||||||
|
|
||||||
|
//DSI config.
|
||||||
|
static const cfg_op_t _display_config_9[4] = {
|
||||||
|
{DSI_PAD_CONTROL_1, 0},
|
||||||
|
{DSI_PAD_CONTROL_2, 0},
|
||||||
|
{DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)},
|
||||||
|
{DSI_PAD_CONTROL_4, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
//MIPI CAL config.
|
||||||
|
static const cfg_op_t _display_config_10[16] = {
|
||||||
|
{0x0E, 0x200200}, // MIPI_CAL_DSIA_MIPI_CAL_CONFIG
|
||||||
|
{0x0F, 0x200200}, // MIPI_CAL_DSIB_MIPI_CAL_CONFIG
|
||||||
|
{0x19, 0x200002}, // MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2
|
||||||
|
{0x1A, 0x200002}, // MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2
|
||||||
|
{0x05, 0}, // MIPI_CAL_CILA_MIPI_CAL_CONFIG
|
||||||
|
{0x06, 0}, // MIPI_CAL_CILB_MIPI_CAL_CONFIG
|
||||||
|
{0x07, 0}, // MIPI_CAL_CILC_MIPI_CAL_CONFIG
|
||||||
|
{0x08, 0}, // MIPI_CAL_CILD_MIPI_CAL_CONFIG
|
||||||
|
{0x09, 0}, // MIPI_CAL_CILE_MIPI_CAL_CONFIG
|
||||||
|
{0x0A, 0}, // MIPI_CAL_CILF_MIPI_CAL_CONFIG
|
||||||
|
{0x10, 0}, // MIPI_CAL_DSIC_MIPI_CAL_CONFIG
|
||||||
|
{0x11, 0}, // MIPI_CAL_DSID_MIPI_CAL_CONFIG
|
||||||
|
{0x1A, 0}, // MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2
|
||||||
|
{0x1C, 0}, // MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2
|
||||||
|
{0x1D, 0}, // MIPI_CAL_DSID_MIPI_CAL_CONFIG_2
|
||||||
|
{0, 0x2A000001} // MIPI_CAL_DSIA_MIPI_CAL_CONFIG
|
||||||
|
};
|
||||||
|
|
||||||
|
//Display A config.
|
||||||
|
static const cfg_op_t _display_config_11[113] = {
|
||||||
|
{DC_CMD_STATE_ACCESS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||||
|
{DC_WIN_DV_CONTROL, 0},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||||
|
/* Setup default YUV colorspace conversion coefficients */
|
||||||
|
{DC_WIN_CSC_YOF, 0xF0},
|
||||||
|
{DC_WIN_CSC_KYRGB, 0x12A},
|
||||||
|
{DC_WIN_CSC_KUR, 0},
|
||||||
|
{DC_WIN_CSC_KVR, 0x198},
|
||||||
|
{DC_WIN_CSC_KUG, 0x39B},
|
||||||
|
{DC_WIN_CSC_KVG, 0x32F},
|
||||||
|
{DC_WIN_CSC_KUB, 0x204},
|
||||||
|
{DC_WIN_CSC_KVB, 0},
|
||||||
|
/* End of color coefficients */
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||||
|
{DC_WIN_DV_CONTROL, 0},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||||
|
/* Setup default YUV colorspace conversion coefficients */
|
||||||
|
{DC_WIN_CSC_YOF, 0xF0},
|
||||||
|
{DC_WIN_CSC_KYRGB, 0x12A},
|
||||||
|
{DC_WIN_CSC_KUR, 0},
|
||||||
|
{DC_WIN_CSC_KVR, 0x198},
|
||||||
|
{DC_WIN_CSC_KUG, 0x39B},
|
||||||
|
{DC_WIN_CSC_KVG, 0x32F},
|
||||||
|
{DC_WIN_CSC_KUB, 0x204},
|
||||||
|
{DC_WIN_CSC_KVB, 0},
|
||||||
|
/* End of color coefficients */
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||||
|
{DC_WIN_DV_CONTROL, 0},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||||
|
/* Setup default YUV colorspace conversion coefficients */
|
||||||
|
{DC_WIN_CSC_YOF, 0xF0},
|
||||||
|
{DC_WIN_CSC_KYRGB, 0x12A},
|
||||||
|
{DC_WIN_CSC_KUR, 0},
|
||||||
|
{DC_WIN_CSC_KVR, 0x198},
|
||||||
|
{DC_WIN_CSC_KUG, 0x39B},
|
||||||
|
{DC_WIN_CSC_KVG, 0x32F},
|
||||||
|
{DC_WIN_CSC_KUB, 0x204},
|
||||||
|
{DC_WIN_CSC_KVB, 0},
|
||||||
|
/* End of color coefficients */
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
|
||||||
|
{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
|
||||||
|
{DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
|
||||||
|
{DC_COM_PIN_OUTPUT_POLARITY(3), 0},
|
||||||
|
{0x4E4, 0},
|
||||||
|
{DC_COM_CRC_CONTROL, 0},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||||
|
{0x716, 0x10000FF},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||||
|
{0x716, 0x10000FF},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||||
|
{0x716, 0x10000FF},
|
||||||
|
{DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_DISP_DISP_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_COMMAND, 0},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
|
||||||
|
{DC_CMD_STATE_ACCESS, 0},
|
||||||
|
/* Set Display timings */
|
||||||
|
{DC_DISP_DISP_TIMING_OPTIONS, 0},
|
||||||
|
{DC_DISP_REF_TO_SYNC, (1 << 16)}, // h_ref_to_sync = 0, v_ref_to_sync = 1.
|
||||||
|
{DC_DISP_SYNC_WIDTH, 0x10048},
|
||||||
|
{DC_DISP_BACK_PORCH, 0x90048},
|
||||||
|
{DC_DISP_ACTIVE, 0x50002D0},
|
||||||
|
{DC_DISP_FRONT_PORCH, 0xA0088}, // Sources say that this should be above the DC_DISP_ACTIVE cmd.
|
||||||
|
/* End of Display timings */
|
||||||
|
{DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE},
|
||||||
|
{DC_COM_PIN_OUTPUT_ENABLE(1), 0},
|
||||||
|
{DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL},
|
||||||
|
{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
|
||||||
|
{DC_DISP_DISP_CLOCK_CONTROL, 0},
|
||||||
|
{DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_DISP_DISP_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||||
|
{DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX},
|
||||||
|
{DC_DISP_FRONT_PORCH, 0xA0088},
|
||||||
|
{DC_CMD_STATE_ACCESS, 0},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||||
|
{DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
|
||||||
|
{DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||||
|
{DC_CMD_STATE_ACCESS, 0},
|
||||||
|
{DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)},
|
||||||
|
{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
|
||||||
|
{DC_CMD_DISPLAY_COMMAND_OPTION0, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
////Display A config.
|
||||||
|
static const cfg_op_t _display_config_12[17] = {
|
||||||
|
{DC_DISP_FRONT_PORCH, 0xA0088},
|
||||||
|
{DC_CMD_INT_MASK, 0},
|
||||||
|
{DC_CMD_STATE_ACCESS, 0},
|
||||||
|
{DC_CMD_INT_ENABLE, 0},
|
||||||
|
{DC_CMD_CONT_SYNCPT_VSYNC, 0},
|
||||||
|
{DC_CMD_DISPLAY_COMMAND, 0},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||||
|
{DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
|
||||||
|
{DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||||
|
{DC_CMD_DISPLAY_POWER_CONTROL, 0},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||||
|
};
|
||||||
|
|
||||||
|
//DSI config.
|
||||||
|
static const cfg_op_t _display_config_13[16] = {
|
||||||
|
{DSI_POWER_CONTROL, 0},
|
||||||
|
{DSI_PAD_CONTROL_1, 0},
|
||||||
|
{DSI_PHY_TIMING_0, 0x6070601},
|
||||||
|
{DSI_PHY_TIMING_1, 0x40A0E05},
|
||||||
|
{DSI_PHY_TIMING_2, 0x30118},
|
||||||
|
{DSI_BTA_TIMING, 0x190A14},
|
||||||
|
{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) },
|
||||||
|
{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)},
|
||||||
|
{DSI_TO_TALLY, 0},
|
||||||
|
{DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
|
||||||
|
{DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
|
||||||
|
{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
|
||||||
|
{DSI_MAX_THRESHOLD, 0x40},
|
||||||
|
{DSI_TRIGGER, 0},
|
||||||
|
{DSI_TX_CRC, 0},
|
||||||
|
{DSI_INIT_SEQ_CONTROL, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
//DSI config (if ver == 0x10).
|
||||||
|
static const cfg_op_t _display_config_14[22] = {
|
||||||
|
{DSI_WR_DATA, 0x439},
|
||||||
|
{DSI_WR_DATA, 0x9483FFB9},
|
||||||
|
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||||
|
{DSI_WR_DATA, 0x2139},
|
||||||
|
{DSI_WR_DATA, 0x191919D5},
|
||||||
|
{DSI_WR_DATA, 0x19191919},
|
||||||
|
{DSI_WR_DATA, 0x19191919},
|
||||||
|
{DSI_WR_DATA, 0x19191919},
|
||||||
|
{DSI_WR_DATA, 0x19191919},
|
||||||
|
{DSI_WR_DATA, 0x19191919},
|
||||||
|
{DSI_WR_DATA, 0x19191919},
|
||||||
|
{DSI_WR_DATA, 0x19191919},
|
||||||
|
{DSI_WR_DATA, 0x19},
|
||||||
|
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||||
|
{DSI_WR_DATA, 0xB39},
|
||||||
|
{DSI_WR_DATA, 0x4F0F41B1},
|
||||||
|
{DSI_WR_DATA, 0xF179A433},
|
||||||
|
{DSI_WR_DATA, 0x2D81},
|
||||||
|
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||||
|
{DSI_WR_DATA, 0x439},
|
||||||
|
{DSI_WR_DATA, 0xB9},
|
||||||
|
{DSI_TRIGGER, DSI_TRIGGER_HOST}
|
||||||
|
};
|
||||||
|
|
||||||
|
//Display A config.
|
||||||
|
static const cfg_op_t cfg_display_one_color[8] = {
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A.
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B.
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C.
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
|
||||||
|
{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} //DISPLAY_CTRL_MODE: continuous display.
|
||||||
|
};
|
||||||
|
|
||||||
|
//Display A config.
|
||||||
|
static const cfg_op_t cfg_display_framebuffer[32] = {
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C.
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B.
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A.
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
|
||||||
|
{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, //T_A8R8G8B8 //NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_WIN_POSITION, 0}, //(0,0)
|
||||||
|
{DC_WIN_H_INITIAL_DDA, 0},
|
||||||
|
{DC_WIN_V_INITIAL_DDA, 0},
|
||||||
|
{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes.
|
||||||
|
{DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)},
|
||||||
|
{DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels.
|
||||||
|
{DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
|
||||||
|
{DC_WIN_BUFFER_CONTROL, 0},
|
||||||
|
{DC_WINBUF_SURFACE_KIND, 0}, //Regular surface.
|
||||||
|
{DC_WINBUF_START_ADDR, 0xC0000000}, //Framebuffer address.
|
||||||
|
{DC_WINBUF_ADDR_H_OFFSET, 0},
|
||||||
|
{DC_WINBUF_ADDR_V_OFFSET, 0},
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
|
||||||
|
{DC_WIN_WIN_OPTIONS, 0},
|
||||||
|
{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
|
||||||
|
{DC_WIN_WIN_OPTIONS, WIN_ENABLE}, //Enable window AD.
|
||||||
|
{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, //DISPLAY_CTRL_MODE: continuous display.
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, //General update; window A update.
|
||||||
|
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} //General activation request; window A activation request.
|
||||||
|
};
|
533
source/gfx/gfx.c
Normal file
533
source/gfx/gfx.c
Normal file
@ -0,0 +1,533 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (C) 2018 CTCaer
|
||||||
|
* Copyright (c) 2019 shchmue
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdarg.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include "gfx.h"
|
||||||
|
|
||||||
|
static const u8 _gfx_font[] = {
|
||||||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Char 032 ( )
|
||||||
|
0x00, 0x30, 0x30, 0x18, 0x18, 0x00, 0x0C, 0x00, // Char 033 (!)
|
||||||
|
0x00, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, // Char 034 (")
|
||||||
|
0x00, 0x66, 0x66, 0xFF, 0x66, 0xFF, 0x66, 0x66, // Char 035 (#)
|
||||||
|
0x00, 0x18, 0x7C, 0x06, 0x3C, 0x60, 0x3E, 0x18, // Char 036 ($)
|
||||||
|
0x00, 0x46, 0x66, 0x30, 0x18, 0x0C, 0x66, 0x62, // Char 037 (%)
|
||||||
|
0x00, 0x3C, 0x66, 0x3C, 0x1C, 0xE6, 0x66, 0xFC, // Char 038 (&)
|
||||||
|
0x00, 0x18, 0x0C, 0x06, 0x00, 0x00, 0x00, 0x00, // Char 039 (')
|
||||||
|
0x00, 0x30, 0x18, 0x0C, 0x0C, 0x18, 0x30, 0x00, // Char 040 (()
|
||||||
|
0x00, 0x0C, 0x18, 0x30, 0x30, 0x18, 0x0C, 0x00, // Char 041 ())
|
||||||
|
0x00, 0x66, 0x3C, 0xFF, 0x3C, 0x66, 0x00, 0x00, // Char 042 (*)
|
||||||
|
0x00, 0x18, 0x18, 0x7E, 0x18, 0x18, 0x00, 0x00, // Char 043 (+)
|
||||||
|
0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x0C, 0x00, // Char 044 (,)
|
||||||
|
0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, // Char 045 (-)
|
||||||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, // Char 046 (.)
|
||||||
|
0x00, 0x40, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x00, // Char 047 (/)
|
||||||
|
0x00, 0x3C, 0x66, 0x76, 0x6E, 0x66, 0x3C, 0x00, // Char 048 (0)
|
||||||
|
0x00, 0x18, 0x1C, 0x18, 0x18, 0x18, 0x7E, 0x00, // Char 049 (1)
|
||||||
|
0x00, 0x3C, 0x62, 0x30, 0x0C, 0x06, 0x7E, 0x00, // Char 050 (2)
|
||||||
|
0x00, 0x3C, 0x62, 0x38, 0x60, 0x66, 0x3C, 0x00, // Char 051 (3)
|
||||||
|
0x00, 0x6C, 0x6C, 0x66, 0xFE, 0x60, 0x60, 0x00, // Char 052 (4)
|
||||||
|
0x00, 0x7E, 0x06, 0x7E, 0x60, 0x66, 0x3C, 0x00, // Char 053 (5)
|
||||||
|
0x00, 0x3C, 0x06, 0x3E, 0x66, 0x66, 0x3C, 0x00, // Char 054 (6)
|
||||||
|
0x00, 0x7E, 0x30, 0x30, 0x18, 0x18, 0x18, 0x00, // Char 055 (7)
|
||||||
|
0x00, 0x3C, 0x66, 0x3C, 0x66, 0x66, 0x3C, 0x00, // Char 056 (8)
|
||||||
|
0x00, 0x3C, 0x66, 0x7C, 0x60, 0x66, 0x3C, 0x00, // Char 057 (9)
|
||||||
|
0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, // Char 058 (:)
|
||||||
|
0x00, 0x00, 0x18, 0x00, 0x18, 0x18, 0x0C, 0x00, // Char 059 (;)
|
||||||
|
0x00, 0x70, 0x1C, 0x06, 0x06, 0x1C, 0x70, 0x00, // Char 060 (<)
|
||||||
|
0x00, 0x00, 0x3E, 0x00, 0x3E, 0x00, 0x00, 0x00, // Char 061 (=)
|
||||||
|
0x00, 0x0E, 0x38, 0x60, 0x60, 0x38, 0x0E, 0x00, // Char 062 (>)
|
||||||
|
0x00, 0x3C, 0x66, 0x30, 0x18, 0x00, 0x18, 0x00, // Char 063 (?)
|
||||||
|
0x00, 0x3C, 0x66, 0x76, 0x76, 0x06, 0x46, 0x3C, // Char 064 (@)
|
||||||
|
0x00, 0x3C, 0x66, 0x7E, 0x66, 0x66, 0x66, 0x00, // Char 065 (A)
|
||||||
|
0x00, 0x3E, 0x66, 0x3E, 0x66, 0x66, 0x3E, 0x00, // Char 066 (B)
|
||||||
|
0x00, 0x3C, 0x66, 0x06, 0x06, 0x66, 0x3C, 0x00, // Char 067 (C)
|
||||||
|
0x00, 0x1E, 0x36, 0x66, 0x66, 0x36, 0x1E, 0x00, // Char 068 (D)
|
||||||
|
0x00, 0x7E, 0x06, 0x1E, 0x06, 0x06, 0x7E, 0x00, // Char 069 (E)
|
||||||
|
0x00, 0x3E, 0x06, 0x1E, 0x06, 0x06, 0x06, 0x00, // Char 070 (F)
|
||||||
|
0x00, 0x3C, 0x66, 0x06, 0x76, 0x66, 0x3C, 0x00, // Char 071 (G)
|
||||||
|
0x00, 0x66, 0x66, 0x7E, 0x66, 0x66, 0x66, 0x00, // Char 072 (H)
|
||||||
|
0x00, 0x3C, 0x18, 0x18, 0x18, 0x18, 0x3C, 0x00, // Char 073 (I)
|
||||||
|
0x00, 0x78, 0x30, 0x30, 0x30, 0x36, 0x1C, 0x00, // Char 074 (J)
|
||||||
|
0x00, 0x66, 0x36, 0x1E, 0x1E, 0x36, 0x66, 0x00, // Char 075 (K)
|
||||||
|
0x00, 0x06, 0x06, 0x06, 0x06, 0x06, 0x7E, 0x00, // Char 076 (L)
|
||||||
|
0x00, 0x46, 0x6E, 0x7E, 0x56, 0x46, 0x46, 0x00, // Char 077 (M)
|
||||||
|
0x00, 0x66, 0x6E, 0x7E, 0x76, 0x66, 0x66, 0x00, // Char 078 (N)
|
||||||
|
0x00, 0x3C, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x00, // Char 079 (O)
|
||||||
|
0x00, 0x3E, 0x66, 0x3E, 0x06, 0x06, 0x06, 0x00, // Char 080 (P)
|
||||||
|
0x00, 0x3C, 0x66, 0x66, 0x66, 0x3C, 0x70, 0x00, // Char 081 (Q)
|
||||||
|
0x00, 0x3E, 0x66, 0x3E, 0x1E, 0x36, 0x66, 0x00, // Char 082 (R)
|
||||||
|
0x00, 0x3C, 0x66, 0x0C, 0x30, 0x66, 0x3C, 0x00, // Char 083 (S)
|
||||||
|
0x00, 0x7E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, // Char 084 (T)
|
||||||
|
0x00, 0x66, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x00, // Char 085 (U)
|
||||||
|
0x00, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x18, 0x00, // Char 086 (V)
|
||||||
|
0x00, 0x46, 0x46, 0x56, 0x7E, 0x6E, 0x46, 0x00, // Char 087 (W)
|
||||||
|
0x00, 0x66, 0x3C, 0x18, 0x3C, 0x66, 0x66, 0x00, // Char 088 (X)
|
||||||
|
0x00, 0x66, 0x66, 0x3C, 0x18, 0x18, 0x18, 0x00, // Char 089 (Y)
|
||||||
|
0x00, 0x7E, 0x30, 0x18, 0x0C, 0x06, 0x7E, 0x00, // Char 090 (Z)
|
||||||
|
0x00, 0x3C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x3C, // Char 091 ([)
|
||||||
|
0x00, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x40, 0x00, // Char 092 (\)
|
||||||
|
0x00, 0x3C, 0x30, 0x30, 0x30, 0x30, 0x30, 0x3C, // Char 093 (])
|
||||||
|
0x00, 0x18, 0x3C, 0x66, 0x00, 0x00, 0x00, 0x00, // Char 094 (^)
|
||||||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, // Char 095 (_)
|
||||||
|
0x00, 0x0C, 0x18, 0x30, 0x00, 0x00, 0x00, 0x00, // Char 096 (`)
|
||||||
|
0x00, 0x00, 0x3C, 0x60, 0x7C, 0x66, 0x7C, 0x00, // Char 097 (a)
|
||||||
|
0x00, 0x06, 0x06, 0x3E, 0x66, 0x66, 0x3E, 0x00, // Char 098 (b)
|
||||||
|
0x00, 0x00, 0x3C, 0x06, 0x06, 0x06, 0x3C, 0x00, // Char 099 (c)
|
||||||
|
0x00, 0x60, 0x60, 0x7C, 0x66, 0x66, 0x7C, 0x00, // Char 100 (d)
|
||||||
|
0x00, 0x00, 0x3C, 0x66, 0x7E, 0x06, 0x3C, 0x00, // Char 101 (e)
|
||||||
|
0x00, 0x38, 0x0C, 0x3E, 0x0C, 0x0C, 0x0C, 0x00, // Char 102 (f)
|
||||||
|
0x00, 0x00, 0x7C, 0x66, 0x7C, 0x40, 0x3C, 0x00, // Char 103 (g)
|
||||||
|
0x00, 0x06, 0x06, 0x3E, 0x66, 0x66, 0x66, 0x00, // Char 104 (h)
|
||||||
|
0x00, 0x18, 0x00, 0x1C, 0x18, 0x18, 0x3C, 0x00, // Char 105 (i)
|
||||||
|
0x00, 0x30, 0x00, 0x30, 0x30, 0x30, 0x1E, 0x00, // Char 106 (j)
|
||||||
|
0x00, 0x06, 0x06, 0x36, 0x1E, 0x36, 0x66, 0x00, // Char 107 (k)
|
||||||
|
0x00, 0x1C, 0x18, 0x18, 0x18, 0x18, 0x3C, 0x00, // Char 108 (l)
|
||||||
|
0x00, 0x00, 0x66, 0xFE, 0xFE, 0xD6, 0xC6, 0x00, // Char 109 (m)
|
||||||
|
0x00, 0x00, 0x3E, 0x66, 0x66, 0x66, 0x66, 0x00, // Char 110 (n)
|
||||||
|
0x00, 0x00, 0x3C, 0x66, 0x66, 0x66, 0x3C, 0x00, // Char 111 (o)
|
||||||
|
0x00, 0x00, 0x3E, 0x66, 0x66, 0x3E, 0x06, 0x00, // Char 112 (p)
|
||||||
|
0x00, 0x00, 0x7C, 0x66, 0x66, 0x7C, 0x60, 0x00, // Char 113 (q)
|
||||||
|
0x00, 0x00, 0x3E, 0x66, 0x06, 0x06, 0x06, 0x00, // Char 114 (r)
|
||||||
|
0x00, 0x00, 0x7C, 0x06, 0x3C, 0x60, 0x3E, 0x00, // Char 115 (s)
|
||||||
|
0x00, 0x18, 0x7E, 0x18, 0x18, 0x18, 0x70, 0x00, // Char 116 (t)
|
||||||
|
0x00, 0x00, 0x66, 0x66, 0x66, 0x66, 0x7C, 0x00, // Char 117 (u)
|
||||||
|
0x00, 0x00, 0x66, 0x66, 0x66, 0x3C, 0x18, 0x00, // Char 118 (v)
|
||||||
|
0x00, 0x00, 0xC6, 0xD6, 0xFE, 0x7C, 0x6C, 0x00, // Char 119 (w)
|
||||||
|
0x00, 0x00, 0x66, 0x3C, 0x18, 0x3C, 0x66, 0x00, // Char 120 (x)
|
||||||
|
0x00, 0x00, 0x66, 0x66, 0x7C, 0x60, 0x3C, 0x00, // Char 121 (y)
|
||||||
|
0x00, 0x00, 0x7E, 0x30, 0x18, 0x0C, 0x7E, 0x00, // Char 122 (z)
|
||||||
|
0x00, 0x18, 0x08, 0x08, 0x04, 0x08, 0x08, 0x18, // Char 123 ({)
|
||||||
|
0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, // Char 124 (|)
|
||||||
|
0x00, 0x0C, 0x08, 0x08, 0x10, 0x08, 0x08, 0x0C, // Char 125 (})
|
||||||
|
0x00, 0x00, 0x00, 0x4C, 0x32, 0x00, 0x00, 0x00 // Char 126 (~)
|
||||||
|
};
|
||||||
|
|
||||||
|
void gfx_init_ctxt(gfx_ctxt_t *ctxt, u32 *fb, u32 width, u32 height, u32 stride)
|
||||||
|
{
|
||||||
|
ctxt->fb = fb;
|
||||||
|
ctxt->width = width;
|
||||||
|
ctxt->height = height;
|
||||||
|
ctxt->stride = stride;
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_clear_grey(gfx_ctxt_t *ctxt, u8 color)
|
||||||
|
{
|
||||||
|
memset(ctxt->fb, color, 0x3C0000);
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_clear_color(gfx_ctxt_t *ctxt, u32 color)
|
||||||
|
{
|
||||||
|
for (u32 i = 0; i < ctxt->height * ctxt->stride; i++)
|
||||||
|
ctxt->fb[i] = color;
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_clear_partial_grey(gfx_ctxt_t *ctxt, u8 color, u32 pos_x, u32 height)
|
||||||
|
{
|
||||||
|
memset(ctxt->fb + pos_x * ctxt->stride, color, height * 4 * ctxt->stride);
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_con_init(gfx_con_t *con, gfx_ctxt_t *ctxt)
|
||||||
|
{
|
||||||
|
con->gfx_ctxt = ctxt;
|
||||||
|
con->fntsz = 16;
|
||||||
|
con->x = 0;
|
||||||
|
con->y = 0;
|
||||||
|
con->savedx = 0;
|
||||||
|
con->savedy = 0;
|
||||||
|
con->fgcol = 0xFFCCCCCC;
|
||||||
|
con->fillbg = 0;
|
||||||
|
con->bgcol = 0xFF1B1B1B;
|
||||||
|
con->mute = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_con_setcol(gfx_con_t *con, u32 fgcol, int fillbg, u32 bgcol)
|
||||||
|
{
|
||||||
|
con->fgcol = fgcol;
|
||||||
|
con->fillbg = fillbg;
|
||||||
|
con->bgcol = bgcol;
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_con_getpos(gfx_con_t *con, u32 *x, u32 *y)
|
||||||
|
{
|
||||||
|
*x = con->x;
|
||||||
|
*y = con->y;
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_con_setpos(gfx_con_t *con, u32 x, u32 y)
|
||||||
|
{
|
||||||
|
con->x = x;
|
||||||
|
con->y = y;
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_putc(gfx_con_t *con, char c)
|
||||||
|
{
|
||||||
|
// Duplicate code for performance reasons.
|
||||||
|
switch (con->fntsz)
|
||||||
|
{
|
||||||
|
case 16:
|
||||||
|
if (c >= 32 && c <= 126)
|
||||||
|
{
|
||||||
|
u8 *cbuf = (u8 *)&_gfx_font[8 * (c - 32)];
|
||||||
|
u32 *fb = con->gfx_ctxt->fb + con->x + con->y * con->gfx_ctxt->stride;
|
||||||
|
|
||||||
|
for (u32 i = 0; i < 16; i+=2)
|
||||||
|
{
|
||||||
|
u8 v = *cbuf++;
|
||||||
|
for (u32 k = 0; k < 2; k++)
|
||||||
|
{
|
||||||
|
for (u32 j = 0; j < 8; j++)
|
||||||
|
{
|
||||||
|
if (v & 1)
|
||||||
|
{
|
||||||
|
*fb = con->fgcol;
|
||||||
|
fb++;
|
||||||
|
*fb = con->fgcol;
|
||||||
|
}
|
||||||
|
else if (con->fillbg)
|
||||||
|
{
|
||||||
|
*fb = con->bgcol;
|
||||||
|
fb++;
|
||||||
|
*fb = con->bgcol;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
fb++;
|
||||||
|
v >>= 1;
|
||||||
|
fb++;
|
||||||
|
}
|
||||||
|
fb += con->gfx_ctxt->stride - 16;
|
||||||
|
v = *cbuf;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
con->x += 16;
|
||||||
|
if (con->x >= con->gfx_ctxt->width - 16) {
|
||||||
|
con->x = 0;
|
||||||
|
con->y += 16;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else if (c == '\n')
|
||||||
|
{
|
||||||
|
con->x = 0;
|
||||||
|
con->y += 16;
|
||||||
|
if (con->y > con->gfx_ctxt->height - 16)
|
||||||
|
con->y = 0;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case 8:
|
||||||
|
default:
|
||||||
|
if (c >= 32 && c <= 126)
|
||||||
|
{
|
||||||
|
u8 *cbuf = (u8 *)&_gfx_font[8 * (c - 32)];
|
||||||
|
u32 *fb = con->gfx_ctxt->fb + con->x + con->y * con->gfx_ctxt->stride;
|
||||||
|
for (u32 i = 0; i < 8; i++)
|
||||||
|
{
|
||||||
|
u8 v = *cbuf++;
|
||||||
|
for (u32 j = 0; j < 8; j++)
|
||||||
|
{
|
||||||
|
if (v & 1)
|
||||||
|
*fb = con->fgcol;
|
||||||
|
else if (con->fillbg)
|
||||||
|
*fb = con->bgcol;
|
||||||
|
v >>= 1;
|
||||||
|
fb++;
|
||||||
|
}
|
||||||
|
fb += con->gfx_ctxt->stride - 8;
|
||||||
|
}
|
||||||
|
con->x += 8;
|
||||||
|
if (con->x >= con->gfx_ctxt->width - 8) {
|
||||||
|
con->x = 0;
|
||||||
|
con->y += 8;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else if (c == '\n')
|
||||||
|
{
|
||||||
|
con->x = 0;
|
||||||
|
con->y += 8;
|
||||||
|
if (con->y > con->gfx_ctxt->height - 8)
|
||||||
|
con->y = 0;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_puts(gfx_con_t *con, const char *s)
|
||||||
|
{
|
||||||
|
if (!s || con->mute)
|
||||||
|
return;
|
||||||
|
|
||||||
|
for (; *s; s++)
|
||||||
|
gfx_putc(con, *s);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _gfx_putn(gfx_con_t *con, u32 v, int base, char fill, int fcnt)
|
||||||
|
{
|
||||||
|
char buf[65];
|
||||||
|
static const char digits[] = "0123456789ABCDEFghijklmnopqrstuvwxyz";
|
||||||
|
char *p;
|
||||||
|
int c = fcnt;
|
||||||
|
|
||||||
|
if (base > 36)
|
||||||
|
return;
|
||||||
|
|
||||||
|
p = buf + 64;
|
||||||
|
*p = 0;
|
||||||
|
do
|
||||||
|
{
|
||||||
|
c--;
|
||||||
|
*--p = digits[v % base];
|
||||||
|
v /= base;
|
||||||
|
} while (v);
|
||||||
|
|
||||||
|
if (fill != 0)
|
||||||
|
{
|
||||||
|
while (c > 0)
|
||||||
|
{
|
||||||
|
*--p = fill;
|
||||||
|
c--;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
gfx_puts(con, p);
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_put_small_sep(gfx_con_t *con)
|
||||||
|
{
|
||||||
|
u8 prevFontSize = con->fntsz;
|
||||||
|
con->fntsz = 8;
|
||||||
|
gfx_putc(con, '\n');
|
||||||
|
con->fntsz = prevFontSize;
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_put_big_sep(gfx_con_t *con)
|
||||||
|
{
|
||||||
|
u8 prevFontSize = con->fntsz;
|
||||||
|
con->fntsz = 16;
|
||||||
|
gfx_putc(con, '\n');
|
||||||
|
con->fntsz = prevFontSize;
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_printf(gfx_con_t *con, const char *fmt, ...)
|
||||||
|
{
|
||||||
|
if (con->mute)
|
||||||
|
return;
|
||||||
|
|
||||||
|
va_list ap;
|
||||||
|
int fill, fcnt;
|
||||||
|
|
||||||
|
va_start(ap, fmt);
|
||||||
|
while(*fmt)
|
||||||
|
{
|
||||||
|
if(*fmt == '%')
|
||||||
|
{
|
||||||
|
fmt++;
|
||||||
|
fill = 0;
|
||||||
|
fcnt = 0;
|
||||||
|
if ((*fmt >= '0' && *fmt <= '9') || *fmt == ' ')
|
||||||
|
{
|
||||||
|
fcnt = *fmt;
|
||||||
|
fmt++;
|
||||||
|
if (*fmt >= '0' && *fmt <= '9')
|
||||||
|
{
|
||||||
|
fill = fcnt;
|
||||||
|
fcnt = *fmt - '0';
|
||||||
|
fmt++;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
fill = ' ';
|
||||||
|
fcnt -= '0';
|
||||||
|
}
|
||||||
|
}
|
||||||
|
switch(*fmt)
|
||||||
|
{
|
||||||
|
case 'c':
|
||||||
|
gfx_putc(con, va_arg(ap, u32));
|
||||||
|
break;
|
||||||
|
case 's':
|
||||||
|
gfx_puts(con, va_arg(ap, char *));
|
||||||
|
break;
|
||||||
|
case 'd':
|
||||||
|
_gfx_putn(con, va_arg(ap, u32), 10, fill, fcnt);
|
||||||
|
break;
|
||||||
|
case 'p':
|
||||||
|
case 'P':
|
||||||
|
case 'x':
|
||||||
|
case 'X':
|
||||||
|
_gfx_putn(con, va_arg(ap, u32), 16, fill, fcnt);
|
||||||
|
break;
|
||||||
|
case 'k':
|
||||||
|
con->fgcol = va_arg(ap, u32);
|
||||||
|
break;
|
||||||
|
case 'K':
|
||||||
|
con->bgcol = va_arg(ap, u32);
|
||||||
|
con->fillbg = 1;
|
||||||
|
break;
|
||||||
|
case '%':
|
||||||
|
gfx_putc(con, '%');
|
||||||
|
break;
|
||||||
|
case '\0':
|
||||||
|
goto out;
|
||||||
|
default:
|
||||||
|
gfx_putc(con, '%');
|
||||||
|
gfx_putc(con, *fmt);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
gfx_putc(con, *fmt);
|
||||||
|
fmt++;
|
||||||
|
}
|
||||||
|
|
||||||
|
out:
|
||||||
|
va_end(ap);
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_hexdump(gfx_con_t *con, u32 base, const u8 *buf, u32 len)
|
||||||
|
{
|
||||||
|
if (con->mute)
|
||||||
|
return;
|
||||||
|
|
||||||
|
u8 prevFontSize = con->fntsz;
|
||||||
|
con->fntsz = 8;
|
||||||
|
for(u32 i = 0; i < len; i++)
|
||||||
|
{
|
||||||
|
if(i % 0x10 == 0)
|
||||||
|
{
|
||||||
|
if(i != 0)
|
||||||
|
{
|
||||||
|
gfx_puts(con, "| ");
|
||||||
|
for(u32 j = 0; j < 0x10; j++)
|
||||||
|
{
|
||||||
|
u8 c = buf[i - 0x10 + j];
|
||||||
|
if(c >= 32 && c <= 126)
|
||||||
|
gfx_putc(con, c);
|
||||||
|
else
|
||||||
|
gfx_putc(con, '.');
|
||||||
|
}
|
||||||
|
gfx_putc(con, '\n');
|
||||||
|
}
|
||||||
|
gfx_printf(con, "%08x: ", base + i);
|
||||||
|
}
|
||||||
|
gfx_printf(con, "%02x ", buf[i]);
|
||||||
|
if (i == len - 1)
|
||||||
|
{
|
||||||
|
int ln = len % 0x10 != 0;
|
||||||
|
u32 k = 0x10 - 1;
|
||||||
|
if (ln)
|
||||||
|
{
|
||||||
|
k = (len & 0xF) - 1;
|
||||||
|
for (u32 j = 0; j < 0x10 - k; j++)
|
||||||
|
gfx_puts(con, " ");
|
||||||
|
}
|
||||||
|
gfx_puts(con, "| ");
|
||||||
|
for(u32 j = 0; j < (ln ? k : k + 1); j++)
|
||||||
|
{
|
||||||
|
u8 c = buf[i - k + j];
|
||||||
|
if(c >= 32 && c <= 126)
|
||||||
|
gfx_putc(con, c);
|
||||||
|
else
|
||||||
|
gfx_putc(con, '.');
|
||||||
|
}
|
||||||
|
gfx_putc(con, '\n');
|
||||||
|
}
|
||||||
|
}
|
||||||
|
gfx_putc(con, '\n');
|
||||||
|
con->fntsz = prevFontSize;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int abs(int x)
|
||||||
|
{
|
||||||
|
if (x < 0)
|
||||||
|
return -x;
|
||||||
|
return x;
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_set_pixel(gfx_ctxt_t *ctxt, u32 x, u32 y, u32 color)
|
||||||
|
{
|
||||||
|
ctxt->fb[x + y * ctxt->stride] = color;
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_line(gfx_ctxt_t *ctxt, int x0, int y0, int x1, int y1, u32 color)
|
||||||
|
{
|
||||||
|
int dx = abs(x1 - x0), sx = x0 < x1 ? 1 : -1;
|
||||||
|
int dy = abs(y1 - y0), sy = y0 < y1 ? 1 : -1;
|
||||||
|
int err = (dx > dy ? dx : -dy) / 2, e2;
|
||||||
|
|
||||||
|
while (1)
|
||||||
|
{
|
||||||
|
gfx_set_pixel(ctxt, x0, y0, color);
|
||||||
|
if (x0 == x1 && y0 == y1)
|
||||||
|
break;
|
||||||
|
e2 = err;
|
||||||
|
if (e2 >-dx)
|
||||||
|
{
|
||||||
|
err -= dy;
|
||||||
|
x0 += sx;
|
||||||
|
}
|
||||||
|
if (e2 < dy)
|
||||||
|
{
|
||||||
|
err += dx;
|
||||||
|
y0 += sy;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_set_rect_grey(gfx_ctxt_t *ctxt, const u8 *buf, u32 size_x, u32 size_y, u32 pos_x, u32 pos_y)
|
||||||
|
{
|
||||||
|
u32 pos = 0;
|
||||||
|
for (u32 y = pos_y; y < (pos_y + size_y); y++)
|
||||||
|
{
|
||||||
|
for (u32 x = pos_x; x < (pos_x + size_x); x++)
|
||||||
|
{
|
||||||
|
memset(&ctxt->fb[x + y*ctxt->stride], buf[pos], 4);
|
||||||
|
pos++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void gfx_set_rect_rgb(gfx_ctxt_t *ctxt, const u8 *buf, u32 size_x, u32 size_y, u32 pos_x, u32 pos_y)
|
||||||
|
{
|
||||||
|
u32 pos = 0;
|
||||||
|
for (u32 y = pos_y; y < (pos_y + size_y); y++)
|
||||||
|
{
|
||||||
|
for (u32 x = pos_x; x < (pos_x + size_x); x++)
|
||||||
|
{
|
||||||
|
ctxt->fb[x + y*ctxt->stride] = buf[pos + 2] | (buf[pos + 1] << 8) | (buf[pos] << 16);
|
||||||
|
pos+=3;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_set_rect_argb(gfx_ctxt_t *ctxt, const u32 *buf, u32 size_x, u32 size_y, u32 pos_x, u32 pos_y)
|
||||||
|
{
|
||||||
|
u32 *ptr = (u32 *)buf;
|
||||||
|
for (u32 y = pos_y; y < (pos_y + size_y); y++)
|
||||||
|
for (u32 x = pos_x; x < (pos_x + size_x); x++)
|
||||||
|
ctxt->fb[x + y * ctxt->stride] = *ptr++;
|
||||||
|
}
|
||||||
|
|
||||||
|
void gfx_render_bmp_argb(gfx_ctxt_t *ctxt, const u32 *buf, u32 size_x, u32 size_y, u32 pos_x, u32 pos_y)
|
||||||
|
{
|
||||||
|
for (u32 y = pos_y; y < (pos_y + size_y); y++)
|
||||||
|
{
|
||||||
|
for (u32 x = pos_x; x < (pos_x + size_x); x++)
|
||||||
|
ctxt->fb[x + y * ctxt->stride] = buf[(size_y + pos_y - 1 - y ) * size_x + x - pos_x];
|
||||||
|
}
|
||||||
|
}
|
46
source/gfx/gfx.h
Normal file
46
source/gfx/gfx.h
Normal file
@ -0,0 +1,46 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (C) 2018 CTCaer
|
||||||
|
* Copyright (C) 2018 M4xw
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _GFX_H_
|
||||||
|
#define _GFX_H_
|
||||||
|
|
||||||
|
#include "../../common/common_gfx.h"
|
||||||
|
|
||||||
|
void gfx_init_ctxt(gfx_ctxt_t *ctxt, u32 *fb, u32 width, u32 height, u32 stride);
|
||||||
|
void gfx_clear_grey(gfx_ctxt_t *ctxt, u8 color);
|
||||||
|
void gfx_clear_partial_grey(gfx_ctxt_t *ctxt, u8 color, u32 pos_x, u32 height);
|
||||||
|
void gfx_clear_color(gfx_ctxt_t *ctxt, u32 color);
|
||||||
|
void gfx_con_init(gfx_con_t *con, gfx_ctxt_t *ctxt);
|
||||||
|
void gfx_con_setcol(gfx_con_t *con, u32 fgcol, int fillbg, u32 bgcol);
|
||||||
|
void gfx_con_getpos(gfx_con_t *con, u32 *x, u32 *y);
|
||||||
|
void gfx_con_setpos(gfx_con_t *con, u32 x, u32 y);
|
||||||
|
void gfx_putc(gfx_con_t *con, char c);
|
||||||
|
void gfx_puts(gfx_con_t *con, const char *s);
|
||||||
|
void gfx_printf(gfx_con_t *con, const char *fmt, ...);
|
||||||
|
void gfx_hexdump(gfx_con_t *con, u32 base, const u8 *buf, u32 len);
|
||||||
|
|
||||||
|
void gfx_set_pixel(gfx_ctxt_t *ctxt, u32 x, u32 y, u32 color);
|
||||||
|
void gfx_line(gfx_ctxt_t *ctxt, int x0, int y0, int x1, int y1, u32 color);
|
||||||
|
void gfx_put_small_sep(gfx_con_t *con);
|
||||||
|
void gfx_put_big_sep(gfx_con_t *con);
|
||||||
|
void gfx_set_rect_grey(gfx_ctxt_t *ctxt, const u8 *buf, u32 size_x, u32 size_y, u32 pos_x, u32 pos_y);
|
||||||
|
void gfx_set_rect_rgb(gfx_ctxt_t *ctxt, const u8 *buf, u32 size_x, u32 size_y, u32 pos_x, u32 pos_y);
|
||||||
|
void gfx_set_rect_argb(gfx_ctxt_t *ctxt, const u32 *buf, u32 size_x, u32 size_y, u32 pos_x, u32 pos_y);
|
||||||
|
void gfx_render_bmp_argb(gfx_ctxt_t *ctxt, const u32 *buf, u32 size_x, u32 size_y, u32 pos_x, u32 pos_y);
|
||||||
|
|
||||||
|
#endif
|
61
source/hos/pkg1.c
Normal file
61
source/hos/pkg1.c
Normal file
@ -0,0 +1,61 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (c) 2018 st4rk
|
||||||
|
* Copyright (c) 2018-2019 CTCaer
|
||||||
|
* Copyright (c) 2018 balika011
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include "pkg1.h"
|
||||||
|
#include "../sec/se.h"
|
||||||
|
|
||||||
|
#define SM_100_ADR 0x4002B020
|
||||||
|
|
||||||
|
/*
|
||||||
|
* package1.1 header: <wb, ldr, sm>
|
||||||
|
* package1.1 layout:
|
||||||
|
* 1.0: {sm, ldr, wb} { 2, 1, 0 }
|
||||||
|
* 2.0: {wb, ldr, sm} { 0, 1, 2 }
|
||||||
|
* 3.0: {wb, ldr, sm} { 0, 1, 2 }
|
||||||
|
* 3.1: {wb, ldr, sm} { 0, 1, 2 }
|
||||||
|
* 4.0: {ldr, sm, wb} { 1, 2, 0 }
|
||||||
|
* 5.0: {ldr, sm, wb} { 1, 2, 0 }
|
||||||
|
* 6.0: {ldr, sm, wb} { 1, 2, 0 }
|
||||||
|
* 6.2: {ldr, sm, wb} { 1, 2, 0 }
|
||||||
|
* 7.0: {ldr, sm, wb} { 1, 2, 0 }
|
||||||
|
*/
|
||||||
|
|
||||||
|
static const pkg1_id_t _pkg1_ids[] = {
|
||||||
|
{ "20161121183008", 0, 0x1900, 0x3FE0, { 2, 1, 0 }, SM_100_ADR, 0x8000D000, true, NULL, NULL }, //1.0.0 (Patched relocator)
|
||||||
|
{ "20170210155124", 0, 0x1900, 0x3FE0, { 0, 1, 2 }, 0x4002D000, 0x8000D000, true, NULL, NULL }, //2.0.0 - 2.3.0
|
||||||
|
{ "20170519101410", 1, 0x1A00, 0x3FE0, { 0, 1, 2 }, 0x4002D000, 0x8000D000, true, NULL, NULL }, //3.0.0
|
||||||
|
{ "20170710161758", 2, 0x1A00, 0x3FE0, { 0, 1, 2 }, 0x4002D000, 0x8000D000, true, NULL, NULL }, //3.0.1 - 3.0.2
|
||||||
|
{ "20170921172629", 3, 0x1800, 0x3FE0, { 1, 2, 0 }, 0x4002B000, 0x4003B000, false, NULL, NULL }, //4.0.0 - 4.1.0
|
||||||
|
{ "20180220163747", 4, 0x1900, 0x3FE0, { 1, 2, 0 }, 0x4002B000, 0x4003B000, false, NULL, NULL }, //5.0.0 - 5.1.0
|
||||||
|
{ "20180802162753", 5, 0x1900, 0x3FE0, { 1, 2, 0 }, 0x4002B000, 0x4003D800, false, NULL, NULL }, //6.0.0 - 6.1.0
|
||||||
|
{ "20181107105733", 6, 0x0E00, 0x6FE0, { 1, 2, 0 }, 0x4002B000, 0x4003D800, false, NULL, NULL }, //6.2.0
|
||||||
|
{ "20181218175730", 7, 0x0F00, 0x6FE0, { 1, 2, 0 }, 0x40030000, 0x4003E000, false, NULL, NULL }, //7.0.0
|
||||||
|
{ "20190208150037", 7, 0x0F00, 0x6FE0, { 1, 2, 0 }, 0x40030000, 0x4003E000, false, NULL, NULL }, //7.0.1
|
||||||
|
{ NULL } //End.
|
||||||
|
};
|
||||||
|
|
||||||
|
const pkg1_id_t *pkg1_identify(u8 *pkg1)
|
||||||
|
{
|
||||||
|
for (u32 i = 0; _pkg1_ids[i].id; i++)
|
||||||
|
if (!memcmp(pkg1 + 0x10, _pkg1_ids[i].id, 12))
|
||||||
|
return &_pkg1_ids[i];
|
||||||
|
return NULL;
|
||||||
|
}
|
38
source/hos/pkg1.h
Normal file
38
source/hos/pkg1.h
Normal file
@ -0,0 +1,38 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _PKG1_H_
|
||||||
|
#define _PKG1_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
typedef struct _pkg1_id_t
|
||||||
|
{
|
||||||
|
const char *id;
|
||||||
|
u32 kb;
|
||||||
|
u32 tsec_off;
|
||||||
|
u32 pkg11_off;
|
||||||
|
u32 sec_map[3];
|
||||||
|
u32 secmon_base;
|
||||||
|
u32 warmboot_base;
|
||||||
|
bool set_warmboot;
|
||||||
|
u32 *secmon_patchset;
|
||||||
|
u32 *warmboot_patchset;
|
||||||
|
} pkg1_id_t;
|
||||||
|
|
||||||
|
const pkg1_id_t *pkg1_identify(u8 *pkg1);
|
||||||
|
|
||||||
|
#endif
|
168
source/hos/pkg2.c
Normal file
168
source/hos/pkg2.c
Normal file
@ -0,0 +1,168 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (c) 2018-2019 CTCaer
|
||||||
|
* Copyright (c) 2018 Atmosphère-NX
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include "pkg2.h"
|
||||||
|
#include "../utils/aarch64_util.h"
|
||||||
|
#include "../mem/heap.h"
|
||||||
|
#include "../sec/se.h"
|
||||||
|
#include "../libs/compr/blz.h"
|
||||||
|
|
||||||
|
#include "../gfx/gfx.h"
|
||||||
|
|
||||||
|
#pragma GCC push_options
|
||||||
|
#pragma GCC optimize ("Os")
|
||||||
|
|
||||||
|
extern gfx_con_t gfx_con;
|
||||||
|
|
||||||
|
/*#include "util.h"
|
||||||
|
#define DPRINTF(...) gfx_printf(&gfx_con, __VA_ARGS__)
|
||||||
|
#define DEBUG_PRINTING*/
|
||||||
|
#define DPRINTF(...)
|
||||||
|
|
||||||
|
static u32 _pkg2_calc_kip1_size(pkg2_kip1_t *kip1)
|
||||||
|
{
|
||||||
|
u32 size = sizeof(pkg2_kip1_t);
|
||||||
|
for (u32 j = 0; j < KIP1_NUM_SECTIONS; j++)
|
||||||
|
size += kip1->sections[j].size_comp;
|
||||||
|
return size;
|
||||||
|
}
|
||||||
|
|
||||||
|
void pkg2_parse_kips(link_t *info, pkg2_hdr_t *pkg2)
|
||||||
|
{
|
||||||
|
u8 *ptr = pkg2->data + pkg2->sec_size[PKG2_SEC_KERNEL];
|
||||||
|
pkg2_ini1_t *ini1 = (pkg2_ini1_t *)ptr;
|
||||||
|
ptr += sizeof(pkg2_ini1_t);
|
||||||
|
|
||||||
|
for (u32 i = 0; i < ini1->num_procs; i++)
|
||||||
|
{
|
||||||
|
pkg2_kip1_t *kip1 = (pkg2_kip1_t *)ptr;
|
||||||
|
pkg2_kip1_info_t *ki = (pkg2_kip1_info_t *)malloc(sizeof(pkg2_kip1_info_t));
|
||||||
|
ki->kip1 = kip1;
|
||||||
|
ki->size = _pkg2_calc_kip1_size(kip1);
|
||||||
|
list_append(info, &ki->link);
|
||||||
|
ptr += ki->size;
|
||||||
|
DPRINTF(" kip1 %d:%s @ %08X (%08X)\n", i, kip1->name, (u32)kip1, ki->size);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
int pkg2_decompress_kip(pkg2_kip1_info_t* ki, u32 sectsToDecomp)
|
||||||
|
{
|
||||||
|
u32 compClearMask = ~sectsToDecomp;
|
||||||
|
if ((ki->kip1->flags & compClearMask) == ki->kip1->flags)
|
||||||
|
return 0; // Already decompressed, nothing to do.
|
||||||
|
|
||||||
|
pkg2_kip1_t hdr;
|
||||||
|
memcpy(&hdr, ki->kip1, sizeof(hdr));
|
||||||
|
|
||||||
|
unsigned int newKipSize = sizeof(hdr);
|
||||||
|
for (u32 sectIdx = 0; sectIdx < KIP1_NUM_SECTIONS; sectIdx++)
|
||||||
|
{
|
||||||
|
u32 sectCompBit = 1u << sectIdx;
|
||||||
|
// For compressed, cant get actual decompressed size without doing it, so use safe "output size".
|
||||||
|
if (sectIdx < 3 && (sectsToDecomp & sectCompBit) && (hdr.flags & sectCompBit))
|
||||||
|
newKipSize += hdr.sections[sectIdx].size_decomp;
|
||||||
|
else
|
||||||
|
newKipSize += hdr.sections[sectIdx].size_comp;
|
||||||
|
}
|
||||||
|
|
||||||
|
pkg2_kip1_t* newKip = malloc(newKipSize);
|
||||||
|
unsigned char* dstDataPtr = newKip->data;
|
||||||
|
const unsigned char* srcDataPtr = ki->kip1->data;
|
||||||
|
for (u32 sectIdx = 0; sectIdx < KIP1_NUM_SECTIONS; sectIdx++)
|
||||||
|
{
|
||||||
|
u32 sectCompBit = 1u << sectIdx;
|
||||||
|
// Easy copy path for uncompressed or ones we dont want to uncompress.
|
||||||
|
if (sectIdx >= 3 || !(sectsToDecomp & sectCompBit) || !(hdr.flags & sectCompBit))
|
||||||
|
{
|
||||||
|
unsigned int dataSize = hdr.sections[sectIdx].size_comp;
|
||||||
|
if (dataSize == 0)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
memcpy(dstDataPtr, srcDataPtr, dataSize);
|
||||||
|
srcDataPtr += dataSize;
|
||||||
|
dstDataPtr += dataSize;
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned int compSize = hdr.sections[sectIdx].size_comp;
|
||||||
|
unsigned int outputSize = hdr.sections[sectIdx].size_decomp;
|
||||||
|
//gfx_printf(&gfx_con, "Decomping %s KIP1 sect %d of size %d...\n", (const char*)hdr.name, sectIdx, compSize);
|
||||||
|
if (blz_uncompress_srcdest(srcDataPtr, compSize, dstDataPtr, outputSize) == 0)
|
||||||
|
{
|
||||||
|
gfx_printf(&gfx_con, "%kERROR decomping sect %d of %s KIP!%k\n", 0xFFFF0000, sectIdx, (char*)hdr.name, 0xFFCCCCCC);
|
||||||
|
free(newKip);
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DPRINTF("Done! Decompressed size is %d!\n", outputSize);
|
||||||
|
}
|
||||||
|
hdr.sections[sectIdx].size_comp = outputSize;
|
||||||
|
srcDataPtr += compSize;
|
||||||
|
dstDataPtr += outputSize;
|
||||||
|
}
|
||||||
|
|
||||||
|
hdr.flags &= compClearMask;
|
||||||
|
memcpy(newKip, &hdr, sizeof(hdr));
|
||||||
|
newKipSize = dstDataPtr-(unsigned char*)(newKip);
|
||||||
|
|
||||||
|
free(ki->kip1);
|
||||||
|
ki->kip1 = newKip;
|
||||||
|
ki->size = newKipSize;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
pkg2_hdr_t *pkg2_decrypt(void *data)
|
||||||
|
{
|
||||||
|
u8 *pdata = (u8 *)data;
|
||||||
|
|
||||||
|
// Skip signature.
|
||||||
|
pdata += 0x100;
|
||||||
|
|
||||||
|
pkg2_hdr_t *hdr = (pkg2_hdr_t *)pdata;
|
||||||
|
|
||||||
|
// Skip header.
|
||||||
|
pdata += sizeof(pkg2_hdr_t);
|
||||||
|
|
||||||
|
// Decrypt header.
|
||||||
|
se_aes_crypt_ctr(8, hdr, sizeof(pkg2_hdr_t), hdr, sizeof(pkg2_hdr_t), hdr);
|
||||||
|
//gfx_hexdump(&gfx_con, (u32)hdr, hdr, 0x100);
|
||||||
|
|
||||||
|
if (hdr->magic != PKG2_MAGIC)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
for (u32 i = 0; i < 4; i++)
|
||||||
|
{
|
||||||
|
DPRINTF("sec %d has size %08X\n", i, hdr->sec_size[i]);
|
||||||
|
if (!hdr->sec_size[i])
|
||||||
|
continue;
|
||||||
|
|
||||||
|
se_aes_crypt_ctr(8, pdata, hdr->sec_size[i], pdata, hdr->sec_size[i], &hdr->sec_ctr[i * 0x10]);
|
||||||
|
//gfx_hexdump(&gfx_con, (u32)pdata, pdata, 0x100);
|
||||||
|
|
||||||
|
pdata += hdr->sec_size[i];
|
||||||
|
}
|
||||||
|
|
||||||
|
return hdr;
|
||||||
|
}
|
||||||
|
|
||||||
|
#pragma GCC pop_options
|
102
source/hos/pkg2.h
Normal file
102
source/hos/pkg2.h
Normal file
@ -0,0 +1,102 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (C) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _PKG2_H_
|
||||||
|
#define _PKG2_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
#include "../utils/list.h"
|
||||||
|
|
||||||
|
#define PKG2_MAGIC 0x31324B50
|
||||||
|
#define PKG2_SEC_BASE 0x80000000
|
||||||
|
#define PKG2_SEC_KERNEL 0
|
||||||
|
#define PKG2_SEC_INI1 1
|
||||||
|
|
||||||
|
#define INI1_MAGIC 0x31494E49
|
||||||
|
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
// Always applied.
|
||||||
|
SVC_GENERIC = 0,
|
||||||
|
// Generic instruction patches.
|
||||||
|
SVC_VERIFY_DS = 0x10,
|
||||||
|
DEBUG_MODE_EN,
|
||||||
|
ATM_GEN_PATCH,
|
||||||
|
// >4 bytes patches. Value is a pointer of a u32 array.
|
||||||
|
ATM_ARR_PATCH,
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef struct _pkg2_hdr_t
|
||||||
|
{
|
||||||
|
u8 ctr[0x10];
|
||||||
|
u8 sec_ctr[0x40];
|
||||||
|
u32 magic;
|
||||||
|
u32 base;
|
||||||
|
u32 pad0;
|
||||||
|
u16 version;
|
||||||
|
u16 pad1;
|
||||||
|
u32 sec_size[4];
|
||||||
|
u32 sec_off[4];
|
||||||
|
u8 sec_sha256[0x80];
|
||||||
|
u8 data[];
|
||||||
|
} pkg2_hdr_t;
|
||||||
|
|
||||||
|
typedef struct _pkg2_ini1_t
|
||||||
|
{
|
||||||
|
u32 magic;
|
||||||
|
u32 size;
|
||||||
|
u32 num_procs;
|
||||||
|
u32 pad;
|
||||||
|
} pkg2_ini1_t;
|
||||||
|
|
||||||
|
typedef struct _pkg2_kip1_sec_t
|
||||||
|
{
|
||||||
|
u32 offset;
|
||||||
|
u32 size_decomp;
|
||||||
|
u32 size_comp;
|
||||||
|
u32 attrib;
|
||||||
|
} pkg2_kip1_sec_t;
|
||||||
|
|
||||||
|
#define KIP1_NUM_SECTIONS 6
|
||||||
|
|
||||||
|
typedef struct _pkg2_kip1_t
|
||||||
|
{
|
||||||
|
u32 magic;
|
||||||
|
u8 name[12];
|
||||||
|
u64 tid;
|
||||||
|
u32 proc_cat;
|
||||||
|
u8 main_thrd_prio;
|
||||||
|
u8 def_cpu_core;
|
||||||
|
u8 res;
|
||||||
|
u8 flags;
|
||||||
|
pkg2_kip1_sec_t sections[KIP1_NUM_SECTIONS];
|
||||||
|
u32 caps[0x20];
|
||||||
|
u8 data[];
|
||||||
|
} pkg2_kip1_t;
|
||||||
|
|
||||||
|
typedef struct _pkg2_kip1_info_t
|
||||||
|
{
|
||||||
|
pkg2_kip1_t *kip1;
|
||||||
|
u32 size;
|
||||||
|
link_t link;
|
||||||
|
} pkg2_kip1_info_t;
|
||||||
|
|
||||||
|
void pkg2_parse_kips(link_t *info, pkg2_hdr_t *pkg2);
|
||||||
|
int pkg2_decompress_kip(pkg2_kip1_info_t* ki, u32 sectsToDecomp);
|
||||||
|
pkg2_hdr_t *pkg2_decrypt(void *data);
|
||||||
|
|
||||||
|
#endif
|
140
source/hos/sept.c
Normal file
140
source/hos/sept.c
Normal file
@ -0,0 +1,140 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2019 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include "sept.h"
|
||||||
|
#include "../gfx/di.h"
|
||||||
|
#include "../libs/fatfs/ff.h"
|
||||||
|
#include "../mem/heap.h"
|
||||||
|
#include "../soc/pmc.h"
|
||||||
|
#include "../soc/t210.h"
|
||||||
|
#include "../storage/nx_emmc.h"
|
||||||
|
#include "../storage/sdmmc.h"
|
||||||
|
#include "../utils/btn.h"
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
#include "../gfx/gfx.h"
|
||||||
|
extern gfx_con_t gfx_con;
|
||||||
|
#define EPRINTF(text) gfx_printf(&gfx_con, "%k"text"%k\n", 0xFFFF0000, 0xFFCCCCCC)
|
||||||
|
#define EPRINTFARGS(text, args...) gfx_printf(&gfx_con, "%k"text"%k\n", 0xFFFF0000, args, 0xFFCCCCCC)
|
||||||
|
|
||||||
|
#define PATCHED_RELOC_SZ 0x94
|
||||||
|
|
||||||
|
#define WB_RST_ADDR 0x40010ED0
|
||||||
|
#define WB_RST_SIZE 0x30
|
||||||
|
|
||||||
|
u8 warmboot_reboot[] = {
|
||||||
|
0x14, 0x00, 0x9F, 0xE5, // LDR R0, =0x7000E450
|
||||||
|
0x01, 0x10, 0xB0, 0xE3, // MOVS R1, #1
|
||||||
|
0x00, 0x10, 0x80, 0xE5, // STR R1, [R0]
|
||||||
|
0x0C, 0x00, 0x9F, 0xE5, // LDR R0, =0x7000E400
|
||||||
|
0x10, 0x10, 0xB0, 0xE3, // MOVS R1, #0x10
|
||||||
|
0x00, 0x10, 0x80, 0xE5, // STR R1, [R0]
|
||||||
|
0xFE, 0xFF, 0xFF, 0xEA, // LOOP
|
||||||
|
0x50, 0xE4, 0x00, 0x70, // #0x7000E450
|
||||||
|
0x00, 0xE4, 0x00, 0x70 // #0x7000E400
|
||||||
|
};
|
||||||
|
|
||||||
|
#define SEPT_PRI_ADDR 0x4003F000
|
||||||
|
|
||||||
|
#define SEPT_PK1T_ADDR 0xC0400000
|
||||||
|
#define SEPT_PK1T_STACK 0x40008000
|
||||||
|
#define SEPT_TCSZ_ADDR (SEPT_PK1T_ADDR - 0x4)
|
||||||
|
#define SEPT_STG1_ADDR (SEPT_PK1T_ADDR + 0x2E100)
|
||||||
|
#define SEPT_STG2_ADDR (SEPT_PK1T_ADDR + 0x60E0)
|
||||||
|
#define SEPT_PKG_SZ (0x2F100 + WB_RST_SIZE)
|
||||||
|
|
||||||
|
extern boot_cfg_t *b_cfg;
|
||||||
|
extern void sd_unmount();
|
||||||
|
extern void reloc_patcher(u32 payload_dst, u32 payload_src, u32 payload_size);
|
||||||
|
|
||||||
|
int reboot_to_sept(const u8 *tsec_fw)
|
||||||
|
{
|
||||||
|
FIL fp;
|
||||||
|
|
||||||
|
// Copy warmboot reboot code and TSEC fw.
|
||||||
|
memcpy((u8 *)(SEPT_PK1T_ADDR - WB_RST_SIZE), (u8 *)warmboot_reboot, sizeof(warmboot_reboot));
|
||||||
|
memcpy((void *)SEPT_PK1T_ADDR, tsec_fw, 0x3000);
|
||||||
|
*(vu32 *)SEPT_TCSZ_ADDR = 0x3000;
|
||||||
|
|
||||||
|
// Copy sept-primary.
|
||||||
|
if (f_open(&fp, "sd:/sept/sept-primary.bin", FA_READ))
|
||||||
|
goto error;
|
||||||
|
|
||||||
|
if (f_read(&fp, (u8 *)SEPT_STG1_ADDR, f_size(&fp), NULL))
|
||||||
|
{
|
||||||
|
f_close(&fp);
|
||||||
|
goto error;
|
||||||
|
}
|
||||||
|
f_close(&fp);
|
||||||
|
|
||||||
|
// Copy sept-secondary.
|
||||||
|
if (f_open(&fp, "sd:/sept/sept-secondary.enc", FA_READ))
|
||||||
|
goto error;
|
||||||
|
|
||||||
|
if (f_read(&fp, (u8 *)SEPT_STG2_ADDR, f_size(&fp), NULL))
|
||||||
|
{
|
||||||
|
f_close(&fp);
|
||||||
|
goto error;
|
||||||
|
}
|
||||||
|
f_close(&fp);
|
||||||
|
|
||||||
|
// Save auto boot config to payload, if any.
|
||||||
|
boot_cfg_t *tmp_cfg = malloc(sizeof(boot_cfg_t));
|
||||||
|
memcpy(tmp_cfg, b_cfg, sizeof(boot_cfg_t));
|
||||||
|
|
||||||
|
tmp_cfg->boot_cfg |= BOOT_CFG_SEPT_RUN;
|
||||||
|
|
||||||
|
if (f_open(&fp, "sd:/sept/payload.bin", FA_READ | FA_WRITE))
|
||||||
|
goto error;
|
||||||
|
|
||||||
|
f_lseek(&fp, PATCHED_RELOC_SZ);
|
||||||
|
f_write(&fp, tmp_cfg, sizeof(boot_cfg_t), NULL);
|
||||||
|
|
||||||
|
f_close(&fp);
|
||||||
|
|
||||||
|
sd_unmount();
|
||||||
|
gfx_printf(&gfx_con, "\n%kPress Power or Vol +/-\n%k to Reboot to Sept...", COLOR_BLUE, COLOR_VIOLET);
|
||||||
|
btn_wait();
|
||||||
|
|
||||||
|
u32 pk1t_sept = SEPT_PK1T_ADDR - (ALIGN(PATCHED_RELOC_SZ, 0x10) + WB_RST_SIZE);
|
||||||
|
|
||||||
|
void (*sept)() = (void *)pk1t_sept;
|
||||||
|
|
||||||
|
reloc_patcher(WB_RST_ADDR, pk1t_sept, SEPT_PKG_SZ);
|
||||||
|
|
||||||
|
// Patch SDRAM init to perform an SVC immediately after second write.
|
||||||
|
PMC(APBDEV_PMC_SCRATCH45) = 0x2E38DFFF;
|
||||||
|
PMC(APBDEV_PMC_SCRATCH46) = 0x6001DC28;
|
||||||
|
// Set SVC handler to jump to sept-primary in IRAM.
|
||||||
|
PMC(APBDEV_PMC_SCRATCH33) = SEPT_PRI_ADDR;
|
||||||
|
PMC(APBDEV_PMC_SCRATCH40) = 0x6000F208;
|
||||||
|
|
||||||
|
display_end();
|
||||||
|
|
||||||
|
(*sept)();
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
error:
|
||||||
|
EPRINTF("Sept payloads not found in sd:/sept!\nPlace appropriate files and try again.");
|
||||||
|
display_backlight_brightness(100, 1000);
|
||||||
|
|
||||||
|
btn_wait();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
24
source/hos/sept.h
Normal file
24
source/hos/sept.h
Normal file
@ -0,0 +1,24 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2019 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _SEPT_H_
|
||||||
|
#define _SEPT_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
int reboot_to_sept(const u8 *tsec_fw);
|
||||||
|
|
||||||
|
#endif
|
1098
source/keys/keys.c
Normal file
1098
source/keys/keys.c
Normal file
File diff suppressed because it is too large
Load Diff
6
source/keys/keys.h
Normal file
6
source/keys/keys.h
Normal file
@ -0,0 +1,6 @@
|
|||||||
|
#ifndef _KEYS_H_
|
||||||
|
#define _KEYS_H_
|
||||||
|
|
||||||
|
void dump_keys();
|
||||||
|
|
||||||
|
#endif
|
97
source/libs/compr/blz.c
Normal file
97
source/libs/compr/blz.c
Normal file
@ -0,0 +1,97 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 rajkosto
|
||||||
|
* Copyright (c) 2018 SciresM
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include "blz.h"
|
||||||
|
|
||||||
|
const blz_footer *blz_get_footer(const unsigned char *compData, unsigned int compDataLen, blz_footer *outFooter)
|
||||||
|
{
|
||||||
|
if (compDataLen < sizeof(blz_footer))
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
const blz_footer *srcFooter = (const blz_footer*)&compData[compDataLen - sizeof(blz_footer)];
|
||||||
|
if (outFooter != NULL)
|
||||||
|
memcpy(outFooter, srcFooter, sizeof(blz_footer)); // Must be a memcpy because no umaligned accesses on ARMv4.
|
||||||
|
|
||||||
|
return srcFooter;
|
||||||
|
}
|
||||||
|
|
||||||
|
// From https://github.com/SciresM/hactool/blob/master/kip.c which is exactly how kernel does it, thanks SciresM!
|
||||||
|
int blz_uncompress_inplace(unsigned char *dataBuf, unsigned int compSize, const blz_footer *footer)
|
||||||
|
{
|
||||||
|
u32 addl_size = footer->addl_size;
|
||||||
|
u32 header_size = footer->header_size;
|
||||||
|
u32 cmp_and_hdr_size = footer->cmp_and_hdr_size;
|
||||||
|
|
||||||
|
unsigned char* cmp_start = &dataBuf[compSize] - cmp_and_hdr_size;
|
||||||
|
u32 cmp_ofs = cmp_and_hdr_size - header_size;
|
||||||
|
u32 out_ofs = cmp_and_hdr_size + addl_size;
|
||||||
|
|
||||||
|
while (out_ofs)
|
||||||
|
{
|
||||||
|
unsigned char control = cmp_start[--cmp_ofs];
|
||||||
|
for (unsigned int i=0; i<8; i++)
|
||||||
|
{
|
||||||
|
if (control & 0x80)
|
||||||
|
{
|
||||||
|
if (cmp_ofs < 2)
|
||||||
|
return 0; // Out of bounds.
|
||||||
|
|
||||||
|
cmp_ofs -= 2;
|
||||||
|
u16 seg_val = ((unsigned int)(cmp_start[cmp_ofs + 1]) << 8) | cmp_start[cmp_ofs];
|
||||||
|
u32 seg_size = ((seg_val >> 12) & 0xF) + 3;
|
||||||
|
u32 seg_ofs = (seg_val & 0x0FFF) + 3;
|
||||||
|
if (out_ofs < seg_size) // Kernel restricts segment copy to stay in bounds.
|
||||||
|
seg_size = out_ofs;
|
||||||
|
|
||||||
|
out_ofs -= seg_size;
|
||||||
|
|
||||||
|
for (unsigned int j = 0; j < seg_size; j++)
|
||||||
|
cmp_start[out_ofs + j] = cmp_start[out_ofs + j + seg_ofs];
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
// Copy directly.
|
||||||
|
if (cmp_ofs < 1)
|
||||||
|
return 0; //out of bounds
|
||||||
|
|
||||||
|
cmp_start[--out_ofs] = cmp_start[--cmp_ofs];
|
||||||
|
}
|
||||||
|
control <<= 1;
|
||||||
|
if (out_ofs == 0) // Blz works backwards, so if it reaches byte 0, it's done.
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int blz_uncompress_srcdest(const unsigned char *compData, unsigned int compDataLen, unsigned char *dstData, unsigned int dstSize)
|
||||||
|
{
|
||||||
|
blz_footer footer;
|
||||||
|
const blz_footer *compFooterPtr = blz_get_footer(compData, compDataLen, &footer);
|
||||||
|
if (compFooterPtr == NULL)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
// Decompression must be done in-place, so need to copy the relevant compressed data first.
|
||||||
|
unsigned int numCompBytes = (const unsigned char*)(compFooterPtr)-compData;
|
||||||
|
memcpy(dstData, compData, numCompBytes);
|
||||||
|
memset(&dstData[numCompBytes], 0, dstSize - numCompBytes);
|
||||||
|
|
||||||
|
return blz_uncompress_inplace(dstData, compDataLen, &footer);
|
||||||
|
}
|
36
source/libs/compr/blz.h
Normal file
36
source/libs/compr/blz.h
Normal file
@ -0,0 +1,36 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 rajkosto
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _BLZ_H_
|
||||||
|
#define _BLZ_H_
|
||||||
|
|
||||||
|
#include "../../utils/types.h"
|
||||||
|
|
||||||
|
typedef struct _blz_footer
|
||||||
|
{
|
||||||
|
u32 cmp_and_hdr_size;
|
||||||
|
u32 header_size;
|
||||||
|
u32 addl_size;
|
||||||
|
} blz_footer;
|
||||||
|
|
||||||
|
// Returns pointer to footer in compData if present, additionally copies it to outFooter if not NULL.
|
||||||
|
const blz_footer *blz_get_footer(const unsigned char *compData, unsigned int compDataLen, blz_footer *outFooter);
|
||||||
|
// Returns 0 on failure.
|
||||||
|
int blz_uncompress_inplace(unsigned char *dataBuf, unsigned int compSize, const blz_footer *footer);
|
||||||
|
// Returns 0 on failure.
|
||||||
|
int blz_uncompress_srcdest(const unsigned char *compData, unsigned int compDataLen, unsigned char *dstData, unsigned int dstSize);
|
||||||
|
|
||||||
|
#endif
|
179
source/libs/compr/lz.c
Normal file
179
source/libs/compr/lz.c
Normal file
@ -0,0 +1,179 @@
|
|||||||
|
/*************************************************************************
|
||||||
|
* Name: lz.c
|
||||||
|
* Author: Marcus Geelnard
|
||||||
|
* Description: LZ77 coder/decoder implementation.
|
||||||
|
* Reentrant: Yes
|
||||||
|
*
|
||||||
|
* The LZ77 compression scheme is a substitutional compression scheme
|
||||||
|
* proposed by Abraham Lempel and Jakob Ziv in 1977. It is very simple in
|
||||||
|
* its design, and uses no fancy bit level compression.
|
||||||
|
*
|
||||||
|
* This is my first attempt at an implementation of a LZ77 code/decoder.
|
||||||
|
*
|
||||||
|
* The principle of the LZ77 compression algorithm is to store repeated
|
||||||
|
* occurrences of strings as references to previous occurrences of the same
|
||||||
|
* string. The point is that the reference consumes less space than the
|
||||||
|
* string itself, provided that the string is long enough (in this
|
||||||
|
* implementation, the string has to be at least 4 bytes long, since the
|
||||||
|
* minimum coded reference is 3 bytes long). Also note that the term
|
||||||
|
* "string" refers to any kind of byte sequence (it does not have to be
|
||||||
|
* an ASCII string, for instance).
|
||||||
|
*
|
||||||
|
* The coder uses a brute force approach to finding string matches in the
|
||||||
|
* history buffer (or "sliding window", if you wish), which is very, very
|
||||||
|
* slow. I recon the complexity is somewhere between O(n^2) and O(n^3),
|
||||||
|
* depending on the input data.
|
||||||
|
*
|
||||||
|
* There is also a faster implementation that uses a large working buffer
|
||||||
|
* in which a "jump table" is stored, which is used to quickly find
|
||||||
|
* possible string matches (see the source code for LZ_CompressFast() for
|
||||||
|
* more information). The faster method is an order of magnitude faster,
|
||||||
|
* but still quite slow compared to other compression methods.
|
||||||
|
*
|
||||||
|
* The upside is that decompression is very fast, and the compression ratio
|
||||||
|
* is often very good.
|
||||||
|
*
|
||||||
|
* The reference to a string is coded as a (length,offset) pair, where the
|
||||||
|
* length indicates the length of the string, and the offset gives the
|
||||||
|
* offset from the current data position. To distinguish between string
|
||||||
|
* references and literal strings (uncompressed bytes), a string reference
|
||||||
|
* is preceded by a marker byte, which is chosen as the least common byte
|
||||||
|
* symbol in the input data stream (this marker byte is stored in the
|
||||||
|
* output stream as the first byte).
|
||||||
|
*
|
||||||
|
* Occurrences of the marker byte in the stream are encoded as the marker
|
||||||
|
* byte followed by a zero byte, which means that occurrences of the marker
|
||||||
|
* byte have to be coded with two bytes.
|
||||||
|
*
|
||||||
|
* The lengths and offsets are coded in a variable length fashion, allowing
|
||||||
|
* values of any magnitude (up to 4294967295 in this implementation).
|
||||||
|
*
|
||||||
|
* With this compression scheme, the worst case compression result is
|
||||||
|
* (257/256)*insize + 1.
|
||||||
|
*
|
||||||
|
*-------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2003-2006 Marcus Geelnard
|
||||||
|
*
|
||||||
|
* This software is provided 'as-is', without any express or implied
|
||||||
|
* warranty. In no event will the authors be held liable for any damages
|
||||||
|
* arising from the use of this software.
|
||||||
|
*
|
||||||
|
* Permission is granted to anyone to use this software for any purpose,
|
||||||
|
* including commercial applications, and to alter it and redistribute it
|
||||||
|
* freely, subject to the following restrictions:
|
||||||
|
*
|
||||||
|
* 1. The origin of this software must not be misrepresented; you must not
|
||||||
|
* claim that you wrote the original software. If you use this software
|
||||||
|
* in a product, an acknowledgment in the product documentation would
|
||||||
|
* be appreciated but is not required.
|
||||||
|
*
|
||||||
|
* 2. Altered source versions must be plainly marked as such, and must not
|
||||||
|
* be misrepresented as being the original software.
|
||||||
|
*
|
||||||
|
* 3. This notice may not be removed or altered from any source
|
||||||
|
* distribution.
|
||||||
|
*
|
||||||
|
* Marcus Geelnard
|
||||||
|
* marcus.geelnard at home.se
|
||||||
|
*************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
/*************************************************************************
|
||||||
|
* INTERNAL FUNCTIONS *
|
||||||
|
*************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
/*************************************************************************
|
||||||
|
* _LZ_ReadVarSize() - Read unsigned integer with variable number of
|
||||||
|
* bytes depending on value.
|
||||||
|
*************************************************************************/
|
||||||
|
|
||||||
|
static int _LZ_ReadVarSize( unsigned int * x, const unsigned char * buf )
|
||||||
|
{
|
||||||
|
unsigned int y, b, num_bytes;
|
||||||
|
|
||||||
|
/* Read complete value (stop when byte contains zero in 8:th bit) */
|
||||||
|
y = 0;
|
||||||
|
num_bytes = 0;
|
||||||
|
do
|
||||||
|
{
|
||||||
|
b = (unsigned int) (*buf ++);
|
||||||
|
y = (y << 7) | (b & 0x0000007f);
|
||||||
|
++ num_bytes;
|
||||||
|
}
|
||||||
|
while( b & 0x00000080 );
|
||||||
|
|
||||||
|
/* Store value in x */
|
||||||
|
*x = y;
|
||||||
|
|
||||||
|
/* Return number of bytes read */
|
||||||
|
return num_bytes;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*************************************************************************
|
||||||
|
* PUBLIC FUNCTIONS *
|
||||||
|
*************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
/*************************************************************************
|
||||||
|
* LZ_Uncompress() - Uncompress a block of data using an LZ77 decoder.
|
||||||
|
* in - Input (compressed) buffer.
|
||||||
|
* out - Output (uncompressed) buffer. This buffer must be large
|
||||||
|
* enough to hold the uncompressed data.
|
||||||
|
* insize - Number of input bytes.
|
||||||
|
*************************************************************************/
|
||||||
|
|
||||||
|
void LZ_Uncompress( const unsigned char *in, unsigned char *out,
|
||||||
|
unsigned int insize )
|
||||||
|
{
|
||||||
|
unsigned char marker, symbol;
|
||||||
|
unsigned int i, inpos, outpos, length, offset;
|
||||||
|
|
||||||
|
/* Do we have anything to uncompress? */
|
||||||
|
if( insize < 1 )
|
||||||
|
{
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get marker symbol from input stream */
|
||||||
|
marker = in[ 0 ];
|
||||||
|
inpos = 1;
|
||||||
|
|
||||||
|
/* Main decompression loop */
|
||||||
|
outpos = 0;
|
||||||
|
do
|
||||||
|
{
|
||||||
|
symbol = in[ inpos ++ ];
|
||||||
|
if( symbol == marker )
|
||||||
|
{
|
||||||
|
/* We had a marker byte */
|
||||||
|
if( in[ inpos ] == 0 )
|
||||||
|
{
|
||||||
|
/* It was a single occurrence of the marker byte */
|
||||||
|
out[ outpos ++ ] = marker;
|
||||||
|
++ inpos;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Extract true length and offset */
|
||||||
|
inpos += _LZ_ReadVarSize( &length, &in[ inpos ] );
|
||||||
|
inpos += _LZ_ReadVarSize( &offset, &in[ inpos ] );
|
||||||
|
|
||||||
|
/* Copy corresponding data from history window */
|
||||||
|
for( i = 0; i < length; ++ i )
|
||||||
|
{
|
||||||
|
out[ outpos ] = out[ outpos - offset ];
|
||||||
|
++ outpos;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* No marker, plain copy */
|
||||||
|
out[ outpos ++ ] = symbol;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
while( inpos < insize );
|
||||||
|
}
|
52
source/libs/compr/lz.h
Normal file
52
source/libs/compr/lz.h
Normal file
@ -0,0 +1,52 @@
|
|||||||
|
/*************************************************************************
|
||||||
|
* Name: lz.h
|
||||||
|
* Author: Marcus Geelnard
|
||||||
|
* Description: LZ77 coder/decoder interface.
|
||||||
|
* Reentrant: Yes
|
||||||
|
*-------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2003-2006 Marcus Geelnard
|
||||||
|
*
|
||||||
|
* This software is provided 'as-is', without any express or implied
|
||||||
|
* warranty. In no event will the authors be held liable for any damages
|
||||||
|
* arising from the use of this software.
|
||||||
|
*
|
||||||
|
* Permission is granted to anyone to use this software for any purpose,
|
||||||
|
* including commercial applications, and to alter it and redistribute it
|
||||||
|
* freely, subject to the following restrictions:
|
||||||
|
*
|
||||||
|
* 1. The origin of this software must not be misrepresented; you must not
|
||||||
|
* claim that you wrote the original software. If you use this software
|
||||||
|
* in a product, an acknowledgment in the product documentation would
|
||||||
|
* be appreciated but is not required.
|
||||||
|
*
|
||||||
|
* 2. Altered source versions must be plainly marked as such, and must not
|
||||||
|
* be misrepresented as being the original software.
|
||||||
|
*
|
||||||
|
* 3. This notice may not be removed or altered from any source
|
||||||
|
* distribution.
|
||||||
|
*
|
||||||
|
* Marcus Geelnard
|
||||||
|
* marcus.geelnard at home.se
|
||||||
|
*************************************************************************/
|
||||||
|
|
||||||
|
#ifndef _lz_h_
|
||||||
|
#define _lz_h_
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*************************************************************************
|
||||||
|
* Function prototypes
|
||||||
|
*************************************************************************/
|
||||||
|
|
||||||
|
void LZ_Uncompress( const unsigned char *in, unsigned char *out,
|
||||||
|
unsigned int insize );
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* _lz_h_ */
|
247
source/libs/fatfs/diskio.c
Normal file
247
source/libs/fatfs/diskio.c
Normal file
@ -0,0 +1,247 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2019 shchmue
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------*/
|
||||||
|
/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2016 */
|
||||||
|
/*-----------------------------------------------------------------------*/
|
||||||
|
/* If a working storage control module is available, it should be */
|
||||||
|
/* attached to the FatFs via a glue function rather than modifying it. */
|
||||||
|
/* This is an example of glue functions to attach various exsisting */
|
||||||
|
/* storage control modules to the FatFs module with a defined API. */
|
||||||
|
/*-----------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#include <string.h>
|
||||||
|
#include "diskio.h" /* FatFs lower layer API */
|
||||||
|
#include "../../gfx/gfx.h"
|
||||||
|
#include "../../mem/heap.h"
|
||||||
|
#include "../../sec/se.h"
|
||||||
|
#include "../../storage/nx_emmc.h"
|
||||||
|
#include "../../storage/sdmmc.h"
|
||||||
|
|
||||||
|
extern gfx_con_t gfx_con;
|
||||||
|
|
||||||
|
extern sdmmc_storage_t sd_storage;
|
||||||
|
extern sdmmc_storage_t storage;
|
||||||
|
extern emmc_part_t *system_part;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
u64 b, a;
|
||||||
|
} le128;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
u32 sector;
|
||||||
|
u32 visit_count;
|
||||||
|
u8 tweak[0x10];
|
||||||
|
u8 cached_sector[0x200];
|
||||||
|
} sector_cache_t;
|
||||||
|
|
||||||
|
#define MAX_SEC_CACHE_ENTRIES 100
|
||||||
|
static sector_cache_t *sector_cache = NULL;
|
||||||
|
static u32 secindex = 0;
|
||||||
|
|
||||||
|
DSTATUS disk_status (
|
||||||
|
BYTE pdrv /* Physical drive nmuber to identify the drive */
|
||||||
|
)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
DSTATUS disk_initialize (
|
||||||
|
BYTE pdrv /* Physical drive nmuber to identify the drive */
|
||||||
|
)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _gf256_mul_x_le(void *block) {
|
||||||
|
u8 *pdata = (u8 *)block;
|
||||||
|
u32 carry = 0;
|
||||||
|
|
||||||
|
for (u32 i = 0; i < 0x10; i++) {
|
||||||
|
u8 b = pdata[i];
|
||||||
|
pdata[i] = (b << 1) | carry;
|
||||||
|
carry = b >> 7;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (carry)
|
||||||
|
pdata[0x0] ^= 0x87;
|
||||||
|
}
|
||||||
|
|
||||||
|
//8378ms before doing the block op all at once, 2179ms after!
|
||||||
|
static inline int _emmc_xts(u32 ks1, u32 ks2, u32 enc, u8 *tweak, bool regen_tweak, u32 tweak_exp, u64 sec, void *dst, void *src, u32 secsize) {
|
||||||
|
int res = 0;
|
||||||
|
u8 *pdst = (u8 *)dst;
|
||||||
|
u8 *psrc = (u8 *)src;
|
||||||
|
|
||||||
|
if (regen_tweak) {
|
||||||
|
for (int i = 0xF; i >= 0; i--) {
|
||||||
|
tweak[i] = sec & 0xFF;
|
||||||
|
sec >>= 8;
|
||||||
|
}
|
||||||
|
if (!se_aes_crypt_block_ecb(ks1, 1, tweak, tweak))
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (u32 i = 0; i < tweak_exp * 0x20; i++)
|
||||||
|
_gf256_mul_x_le(tweak);
|
||||||
|
|
||||||
|
u8 temptweak[0x10];
|
||||||
|
memcpy(temptweak, tweak, 0x10);
|
||||||
|
|
||||||
|
//We are assuming a 0x10-aligned sector size in this implementation.
|
||||||
|
for (u32 i = 0; i < secsize / 0x10; i++) {
|
||||||
|
for (u32 j = 0; j < 0x10; j++)
|
||||||
|
pdst[j] = psrc[j] ^ tweak[j];
|
||||||
|
_gf256_mul_x_le(tweak);
|
||||||
|
psrc += 0x10;
|
||||||
|
pdst += 0x10;
|
||||||
|
}
|
||||||
|
|
||||||
|
se_aes_crypt_ecb(ks2, 0, dst, secsize, src, secsize);
|
||||||
|
|
||||||
|
pdst = (u8 *)dst;
|
||||||
|
|
||||||
|
memcpy(tweak, temptweak, 0x10);
|
||||||
|
for (u32 i = 0; i < secsize / 0x10; i++) {
|
||||||
|
for (u32 j = 0; j < 0x10; j++)
|
||||||
|
pdst[j] = pdst[j] ^ tweak[j];
|
||||||
|
_gf256_mul_x_le(tweak);
|
||||||
|
pdst += 0x10;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
res = 1;
|
||||||
|
|
||||||
|
out:;
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
DRESULT disk_read (
|
||||||
|
BYTE pdrv, /* Physical drive nmuber to identify the drive */
|
||||||
|
BYTE *buff, /* Data buffer to store read data */
|
||||||
|
DWORD sector, /* Start sector in LBA */
|
||||||
|
UINT count /* Number of sectors to read */
|
||||||
|
)
|
||||||
|
{
|
||||||
|
switch (pdrv)
|
||||||
|
{
|
||||||
|
case 0:
|
||||||
|
if ((u32)buff >= 0x90000000)
|
||||||
|
return sdmmc_storage_read(&sd_storage, sector, count, buff) ? RES_OK : RES_ERROR;
|
||||||
|
u8 *buf = (u8 *)0x98000000; //TODO: define this somewhere.
|
||||||
|
if (sdmmc_storage_read(&sd_storage, sector, count, buf))
|
||||||
|
{
|
||||||
|
memcpy(buff, buf, 512 * count);
|
||||||
|
return RES_OK;
|
||||||
|
}
|
||||||
|
return RES_ERROR;
|
||||||
|
case 1:
|
||||||
|
if (!sector_cache) // init sector cache
|
||||||
|
sector_cache = (sector_cache_t*)malloc(sizeof(sector_cache_t) * MAX_SEC_CACHE_ENTRIES);
|
||||||
|
|
||||||
|
static u8 tweak[0x10];
|
||||||
|
static u64 prev_cluster = -1;
|
||||||
|
static u32 prev_sector = 0;
|
||||||
|
u32 tweak_exp = 0;
|
||||||
|
bool regen_tweak = true, cache_sector = false;
|
||||||
|
|
||||||
|
u32 s = 0;
|
||||||
|
if (count == 1) {
|
||||||
|
for ( ; s < secindex; s++) {
|
||||||
|
if (sector_cache[s].sector == sector) {
|
||||||
|
sector_cache[s].visit_count++;
|
||||||
|
memcpy(buff, sector_cache[s].cached_sector, 0x200);
|
||||||
|
memcpy(tweak, sector_cache[s].tweak, 0x10);
|
||||||
|
prev_sector = sector;
|
||||||
|
prev_cluster = sector / 0x20;
|
||||||
|
//gfx_printf(&gfx_con, "addr %x sec %x count %x cached\n", sector * 0x200, sector, count);
|
||||||
|
return RES_OK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
// add to cache
|
||||||
|
if (s == secindex && s < MAX_SEC_CACHE_ENTRIES) {
|
||||||
|
sector_cache[s].sector = sector;
|
||||||
|
sector_cache[s].visit_count++;
|
||||||
|
cache_sector = true;
|
||||||
|
secindex++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if ((u32)buff >= 0x90000000) {
|
||||||
|
if (nx_emmc_part_read(&storage, system_part, sector, count, buff)) {
|
||||||
|
//gfx_hexdump(&gfx_con, 0, buff, 0x100);
|
||||||
|
if (prev_cluster != sector / 0x20) { // sector in different cluster than last read
|
||||||
|
prev_cluster = sector / 0x20;
|
||||||
|
tweak_exp = sector % 0x20;
|
||||||
|
} else if (sector > prev_sector) { // sector in same cluster and past last sector
|
||||||
|
tweak_exp = sector - prev_sector - 1;
|
||||||
|
regen_tweak = false;
|
||||||
|
} else { // sector in same cluster and before or same as last sector
|
||||||
|
tweak_exp = sector % 0x20;
|
||||||
|
}
|
||||||
|
|
||||||
|
// fatfs will never pull more than a cluster
|
||||||
|
//gfx_printf(&gfx_con, "sec %6x count %2x tweak %2x\n", sector, count, tweak_exp);
|
||||||
|
_emmc_xts(9, 8, 0, tweak, regen_tweak, tweak_exp, prev_cluster, buff, buff, count * 0x200);
|
||||||
|
if (cache_sector) {
|
||||||
|
memcpy(sector_cache[s].cached_sector, buff, 0x200);
|
||||||
|
memcpy(sector_cache[s].tweak, tweak, 0x10);
|
||||||
|
}
|
||||||
|
//gfx_hexdump(&gfx_con, 0, buff, 0x10);
|
||||||
|
prev_sector = sector + count - 1;
|
||||||
|
return RES_OK;
|
||||||
|
}
|
||||||
|
return RES_ERROR;
|
||||||
|
} else {
|
||||||
|
u8 *buf = (u8 *)0x98000000;
|
||||||
|
if (nx_emmc_part_read(&storage, system_part, sector, count, buf)) {
|
||||||
|
gfx_printf(&gfx_con, "sec %d count %d\n", sector, count);
|
||||||
|
// _emmc_xts(9, 8, 0, tweak, (sector + 0x20 - 1) / 0x20, buf, buf, count * 0x200);
|
||||||
|
//se_aes_xts_crypt(8, 9, 0, sector / 0x20, buf, buf, 0x200, (count + 0x20 - 1) / 0x20);
|
||||||
|
memcpy(buff, buf, 512 * count);
|
||||||
|
return RES_OK;
|
||||||
|
}
|
||||||
|
return RES_ERROR;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return RES_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
DRESULT disk_write (
|
||||||
|
BYTE pdrv, /* Physical drive nmuber to identify the drive */
|
||||||
|
const BYTE *buff, /* Data to be written */
|
||||||
|
DWORD sector, /* Start sector in LBA */
|
||||||
|
UINT count /* Number of sectors to write */
|
||||||
|
)
|
||||||
|
{
|
||||||
|
if (pdrv == 1)
|
||||||
|
return RES_WRPRT;
|
||||||
|
if ((u32)buff >= 0x90000000)
|
||||||
|
return sdmmc_storage_write(&sd_storage, sector, count, (void *)buff) ? RES_OK : RES_ERROR;
|
||||||
|
u8 *buf = (u8 *)0x98000000; //TODO: define this somewhere.
|
||||||
|
memcpy(buf, buff, 512 * count);
|
||||||
|
if (sdmmc_storage_write(&sd_storage, sector, count, buf))
|
||||||
|
return RES_OK;
|
||||||
|
return RES_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
DRESULT disk_ioctl (
|
||||||
|
BYTE pdrv, /* Physical drive nmuber (0..) */
|
||||||
|
BYTE cmd, /* Control code */
|
||||||
|
void *buff /* Buffer to send/receive control data */
|
||||||
|
)
|
||||||
|
{
|
||||||
|
return RES_OK;
|
||||||
|
}
|
80
source/libs/fatfs/diskio.h
Normal file
80
source/libs/fatfs/diskio.h
Normal file
@ -0,0 +1,80 @@
|
|||||||
|
/*-----------------------------------------------------------------------/
|
||||||
|
/ Low level disk interface modlue include file (C)ChaN, 2014 /
|
||||||
|
/-----------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#ifndef _DISKIO_DEFINED
|
||||||
|
#define _DISKIO_DEFINED
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "../../utils/types.h"
|
||||||
|
|
||||||
|
|
||||||
|
/* Status of Disk Functions */
|
||||||
|
typedef BYTE DSTATUS;
|
||||||
|
|
||||||
|
/* Results of Disk Functions */
|
||||||
|
typedef enum {
|
||||||
|
RES_OK = 0, /* 0: Successful */
|
||||||
|
RES_ERROR, /* 1: R/W Error */
|
||||||
|
RES_WRPRT, /* 2: Write Protected */
|
||||||
|
RES_NOTRDY, /* 3: Not Ready */
|
||||||
|
RES_PARERR /* 4: Invalid Parameter */
|
||||||
|
} DRESULT;
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------*/
|
||||||
|
/* Prototypes for disk control functions */
|
||||||
|
|
||||||
|
|
||||||
|
DSTATUS disk_initialize (BYTE pdrv);
|
||||||
|
DSTATUS disk_status (BYTE pdrv);
|
||||||
|
DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);
|
||||||
|
DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
|
||||||
|
DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
|
||||||
|
|
||||||
|
|
||||||
|
/* Disk Status Bits (DSTATUS) */
|
||||||
|
|
||||||
|
#define STA_NOINIT 0x01 /* Drive not initialized */
|
||||||
|
#define STA_NODISK 0x02 /* No medium in the drive */
|
||||||
|
#define STA_PROTECT 0x04 /* Write protected */
|
||||||
|
|
||||||
|
|
||||||
|
/* Command code for disk_ioctrl fucntion */
|
||||||
|
|
||||||
|
/* Generic command (Used by FatFs) */
|
||||||
|
#define CTRL_SYNC 0 /* Complete pending write process (needed at _FS_READONLY == 0) */
|
||||||
|
#define GET_SECTOR_COUNT 1 /* Get media size (needed at _USE_MKFS == 1) */
|
||||||
|
#define GET_SECTOR_SIZE 2 /* Get sector size (needed at _MAX_SS != _MIN_SS) */
|
||||||
|
#define GET_BLOCK_SIZE 3 /* Get erase block size (needed at _USE_MKFS == 1) */
|
||||||
|
#define CTRL_TRIM 4 /* Inform device that the data on the block of sectors is no longer used (needed at _USE_TRIM == 1) */
|
||||||
|
|
||||||
|
/* Generic command (Not used by FatFs) */
|
||||||
|
#define CTRL_POWER 5 /* Get/Set power status */
|
||||||
|
#define CTRL_LOCK 6 /* Lock/Unlock media removal */
|
||||||
|
#define CTRL_EJECT 7 /* Eject media */
|
||||||
|
#define CTRL_FORMAT 8 /* Create physical format on the media */
|
||||||
|
|
||||||
|
/* MMC/SDC specific ioctl command */
|
||||||
|
#define MMC_GET_TYPE 10 /* Get card type */
|
||||||
|
#define MMC_GET_CSD 11 /* Get CSD */
|
||||||
|
#define MMC_GET_CID 12 /* Get CID */
|
||||||
|
#define MMC_GET_OCR 13 /* Get OCR */
|
||||||
|
#define MMC_GET_SDSTAT 14 /* Get SD status */
|
||||||
|
#define ISDIO_READ 55 /* Read data form SD iSDIO register */
|
||||||
|
#define ISDIO_WRITE 56 /* Write data to SD iSDIO register */
|
||||||
|
#define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */
|
||||||
|
|
||||||
|
/* ATA/CF specific ioctl command */
|
||||||
|
#define ATA_GET_REV 20 /* Get F/W revision */
|
||||||
|
#define ATA_GET_MODEL 21 /* Get model name */
|
||||||
|
#define ATA_GET_SN 22 /* Get serial number */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
6637
source/libs/fatfs/ff.c
Normal file
6637
source/libs/fatfs/ff.c
Normal file
File diff suppressed because it is too large
Load Diff
376
source/libs/fatfs/ff.h
Normal file
376
source/libs/fatfs/ff.h
Normal file
@ -0,0 +1,376 @@
|
|||||||
|
/*----------------------------------------------------------------------------/
|
||||||
|
/ FatFs - Generic FAT Filesystem module R0.13b /
|
||||||
|
/-----------------------------------------------------------------------------/
|
||||||
|
/
|
||||||
|
/ Copyright (C) 2018, ChaN, all right reserved.
|
||||||
|
/
|
||||||
|
/ FatFs module is an open source software. Redistribution and use of FatFs in
|
||||||
|
/ source and binary forms, with or without modification, are permitted provided
|
||||||
|
/ that the following condition is met:
|
||||||
|
|
||||||
|
/ 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
/ this condition and the following disclaimer.
|
||||||
|
/
|
||||||
|
/ This software is provided by the copyright holder and contributors "AS IS"
|
||||||
|
/ and any warranties related to this software are DISCLAIMED.
|
||||||
|
/ The copyright owner or contributors be NOT LIABLE for any damages caused
|
||||||
|
/ by use of this software.
|
||||||
|
/
|
||||||
|
/----------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef FF_DEFINED
|
||||||
|
#define FF_DEFINED 63463 /* Revision ID */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "../../utils/types.h" /* Basic integer types */
|
||||||
|
#include "ffconf.h" /* FatFs configuration options */
|
||||||
|
|
||||||
|
#if FF_DEFINED != FFCONF_DEF
|
||||||
|
#error Wrong configuration file (ffconf.h).
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Definitions of volume management */
|
||||||
|
|
||||||
|
#if FF_MULTI_PARTITION /* Multiple partition configuration */
|
||||||
|
typedef struct {
|
||||||
|
BYTE pd; /* Physical drive number */
|
||||||
|
BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
|
||||||
|
} PARTITION;
|
||||||
|
extern PARTITION VolToPart[]; /* Volume - Partition resolution table */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if FF_STR_VOLUME_ID
|
||||||
|
#ifndef FF_VOLUME_STRS
|
||||||
|
extern const char* VolumeStr[FF_VOLUMES]; /* User defied volume ID */
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Type of path name strings on FatFs API */
|
||||||
|
|
||||||
|
#ifndef _INC_TCHAR
|
||||||
|
#define _INC_TCHAR
|
||||||
|
|
||||||
|
#if FF_USE_LFN && FF_LFN_UNICODE == 1 /* Unicode in UTF-16 encoding */
|
||||||
|
typedef WCHAR TCHAR;
|
||||||
|
#define _T(x) L ## x
|
||||||
|
#define _TEXT(x) L ## x
|
||||||
|
#elif FF_USE_LFN && FF_LFN_UNICODE == 2 /* Unicode in UTF-8 encoding */
|
||||||
|
typedef char TCHAR;
|
||||||
|
#define _T(x) u8 ## x
|
||||||
|
#define _TEXT(x) u8 ## x
|
||||||
|
#elif FF_USE_LFN && FF_LFN_UNICODE == 3 /* Unicode in UTF-32 encoding */
|
||||||
|
typedef DWORD TCHAR;
|
||||||
|
#define _T(x) U ## x
|
||||||
|
#define _TEXT(x) U ## x
|
||||||
|
#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3)
|
||||||
|
#error Wrong FF_LFN_UNICODE setting
|
||||||
|
#else /* ANSI/OEM code in SBCS/DBCS */
|
||||||
|
typedef char TCHAR;
|
||||||
|
#define _T(x) x
|
||||||
|
#define _TEXT(x) x
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Type of file size variables */
|
||||||
|
|
||||||
|
#if FF_FS_EXFAT
|
||||||
|
typedef QWORD FSIZE_t;
|
||||||
|
#else
|
||||||
|
typedef DWORD FSIZE_t;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Filesystem object structure (FATFS) */
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
BYTE fs_type; /* Filesystem type (0:N/A) */
|
||||||
|
BYTE pdrv; /* Physical drive number */
|
||||||
|
BYTE n_fats; /* Number of FATs (1 or 2) */
|
||||||
|
BYTE wflag; /* win[] flag (b0:dirty) */
|
||||||
|
BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */
|
||||||
|
WORD id; /* Volume mount ID */
|
||||||
|
WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
|
||||||
|
WORD csize; /* Cluster size [sectors] */
|
||||||
|
#if FF_MAX_SS != FF_MIN_SS
|
||||||
|
WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */
|
||||||
|
#endif
|
||||||
|
#if FF_USE_LFN
|
||||||
|
WCHAR* lfnbuf; /* LFN working buffer */
|
||||||
|
#endif
|
||||||
|
#if FF_FS_EXFAT
|
||||||
|
BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */
|
||||||
|
#endif
|
||||||
|
#if FF_FS_REENTRANT
|
||||||
|
FF_SYNC_t sobj; /* Identifier of sync object */
|
||||||
|
#endif
|
||||||
|
#if !FF_FS_READONLY
|
||||||
|
DWORD last_clst; /* Last allocated cluster */
|
||||||
|
DWORD free_clst; /* Number of free clusters */
|
||||||
|
#endif
|
||||||
|
#if FF_FS_RPATH
|
||||||
|
DWORD cdir; /* Current directory start cluster (0:root) */
|
||||||
|
#if FF_FS_EXFAT
|
||||||
|
DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */
|
||||||
|
DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */
|
||||||
|
DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */
|
||||||
|
DWORD fsize; /* Size of an FAT [sectors] */
|
||||||
|
DWORD volbase; /* Volume base sector */
|
||||||
|
DWORD fatbase; /* FAT base sector */
|
||||||
|
DWORD dirbase; /* Root directory base sector/cluster */
|
||||||
|
DWORD database; /* Data base sector */
|
||||||
|
DWORD winsect; /* Current sector appearing in the win[] */
|
||||||
|
BYTE win[FF_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */
|
||||||
|
} FATFS;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Object ID and allocation information (FFOBJID) */
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
FATFS* fs; /* Pointer to the hosting volume of this object */
|
||||||
|
WORD id; /* Hosting volume mount ID */
|
||||||
|
BYTE attr; /* Object attribute */
|
||||||
|
BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:flagmented in this session, b2:sub-directory stretched) */
|
||||||
|
DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */
|
||||||
|
FSIZE_t objsize; /* Object size (valid when sclust != 0) */
|
||||||
|
#if FF_FS_EXFAT
|
||||||
|
DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */
|
||||||
|
DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */
|
||||||
|
DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */
|
||||||
|
DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
|
||||||
|
DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */
|
||||||
|
#endif
|
||||||
|
#if FF_FS_LOCK
|
||||||
|
UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */
|
||||||
|
#endif
|
||||||
|
} FFOBJID;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* File object structure (FIL) */
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */
|
||||||
|
BYTE flag; /* File status flags */
|
||||||
|
BYTE err; /* Abort flag (error code) */
|
||||||
|
FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */
|
||||||
|
DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */
|
||||||
|
DWORD sect; /* Sector number appearing in buf[] (0:invalid) */
|
||||||
|
#if !FF_FS_READONLY
|
||||||
|
DWORD dir_sect; /* Sector number containing the directory entry (not used at exFAT) */
|
||||||
|
BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */
|
||||||
|
#endif
|
||||||
|
#if FF_USE_FASTSEEK
|
||||||
|
DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */
|
||||||
|
#endif
|
||||||
|
#if !FF_FS_TINY
|
||||||
|
BYTE buf[FF_MAX_SS]; /* File private data read/write window */
|
||||||
|
#endif
|
||||||
|
} FIL;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Directory object structure (DIR) */
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
FFOBJID obj; /* Object identifier */
|
||||||
|
DWORD dptr; /* Current read/write offset */
|
||||||
|
DWORD clust; /* Current cluster */
|
||||||
|
DWORD sect; /* Current sector (0:Read operation has terminated) */
|
||||||
|
BYTE* dir; /* Pointer to the directory item in the win[] */
|
||||||
|
BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */
|
||||||
|
#if FF_USE_LFN
|
||||||
|
DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
|
||||||
|
#endif
|
||||||
|
#if FF_USE_FIND
|
||||||
|
const TCHAR* pat; /* Pointer to the name matching pattern */
|
||||||
|
#endif
|
||||||
|
} DIR;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* File information structure (FILINFO) */
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
FSIZE_t fsize; /* File size */
|
||||||
|
WORD fdate; /* Modified date */
|
||||||
|
WORD ftime; /* Modified time */
|
||||||
|
BYTE fattrib; /* File attribute */
|
||||||
|
#if FF_USE_LFN
|
||||||
|
TCHAR altname[FF_SFN_BUF + 1];/* Altenative file name */
|
||||||
|
TCHAR fname[FF_LFN_BUF + 1]; /* Primary file name */
|
||||||
|
#else
|
||||||
|
TCHAR fname[12 + 1]; /* File name */
|
||||||
|
#endif
|
||||||
|
} FILINFO;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* File function return code (FRESULT) */
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
FR_OK = 0, /* (0) Succeeded */
|
||||||
|
FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
|
||||||
|
FR_INT_ERR, /* (2) Assertion failed */
|
||||||
|
FR_NOT_READY, /* (3) The physical drive cannot work */
|
||||||
|
FR_NO_FILE, /* (4) Could not find the file */
|
||||||
|
FR_NO_PATH, /* (5) Could not find the path */
|
||||||
|
FR_INVALID_NAME, /* (6) The path name format is invalid */
|
||||||
|
FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
|
||||||
|
FR_EXIST, /* (8) Access denied due to prohibited access */
|
||||||
|
FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
|
||||||
|
FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
|
||||||
|
FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
|
||||||
|
FR_NOT_ENABLED, /* (12) The volume has no work area */
|
||||||
|
FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
|
||||||
|
FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */
|
||||||
|
FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
|
||||||
|
FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
|
||||||
|
FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
|
||||||
|
FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > FF_FS_LOCK */
|
||||||
|
FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
|
||||||
|
} FRESULT;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*--------------------------------------------------------------*/
|
||||||
|
/* FatFs module application interface */
|
||||||
|
|
||||||
|
FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
|
||||||
|
FRESULT f_close (FIL* fp); /* Close an open file object */
|
||||||
|
FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */
|
||||||
|
FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */
|
||||||
|
FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */
|
||||||
|
FRESULT f_truncate (FIL* fp); /* Truncate the file */
|
||||||
|
FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */
|
||||||
|
FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */
|
||||||
|
FRESULT f_closedir (DIR* dp); /* Close an open directory */
|
||||||
|
FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */
|
||||||
|
FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */
|
||||||
|
FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */
|
||||||
|
FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */
|
||||||
|
FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */
|
||||||
|
FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */
|
||||||
|
FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */
|
||||||
|
FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */
|
||||||
|
FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */
|
||||||
|
FRESULT f_chdir (const TCHAR* path); /* Change current directory */
|
||||||
|
FRESULT f_chdrive (const TCHAR* path); /* Change current drive */
|
||||||
|
FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */
|
||||||
|
FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */
|
||||||
|
FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */
|
||||||
|
FRESULT f_setlabel (const TCHAR* label); /* Set volume label */
|
||||||
|
FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */
|
||||||
|
FRESULT f_expand (FIL* fp, FSIZE_t szf, BYTE opt); /* Allocate a contiguous block to the file */
|
||||||
|
FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */
|
||||||
|
FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len); /* Create a FAT volume */
|
||||||
|
FRESULT f_fdisk (BYTE pdrv, const DWORD* szt, void* work); /* Divide a physical drive into some partitions */
|
||||||
|
FRESULT f_setcp (WORD cp); /* Set current code page */
|
||||||
|
int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */
|
||||||
|
int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */
|
||||||
|
int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
|
||||||
|
TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */
|
||||||
|
|
||||||
|
#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
|
||||||
|
#define f_error(fp) ((fp)->err)
|
||||||
|
#define f_tell(fp) ((fp)->fptr)
|
||||||
|
#define f_size(fp) ((fp)->obj.objsize)
|
||||||
|
#define f_rewind(fp) f_lseek((fp), 0)
|
||||||
|
#define f_rewinddir(dp) f_readdir((dp), 0)
|
||||||
|
#define f_rmdir(path) f_unlink(path)
|
||||||
|
#define f_unmount(path) f_mount(0, path, 0)
|
||||||
|
|
||||||
|
#ifndef EOF
|
||||||
|
#define EOF (-1)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*--------------------------------------------------------------*/
|
||||||
|
/* Additional user defined functions */
|
||||||
|
|
||||||
|
/* RTC function */
|
||||||
|
#if !FF_FS_READONLY && !FF_FS_NORTC
|
||||||
|
DWORD get_fattime (void);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* LFN support functions */
|
||||||
|
#if FF_USE_LFN >= 1 /* Code conversion (defined in unicode.c) */
|
||||||
|
WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */
|
||||||
|
WCHAR ff_uni2oem (DWORD uni, WORD cp); /* Unicode to OEM code conversion */
|
||||||
|
DWORD ff_wtoupper (DWORD uni); /* Unicode upper-case conversion */
|
||||||
|
#endif
|
||||||
|
#if FF_USE_LFN == 3 /* Dynamic memory allocation */
|
||||||
|
void* ff_memalloc (UINT msize); /* Allocate memory block */
|
||||||
|
void ff_memfree (void* mblock); /* Free memory block */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Sync functions */
|
||||||
|
#if FF_FS_REENTRANT
|
||||||
|
int ff_cre_syncobj (BYTE vol, FF_SYNC_t* sobj); /* Create a sync object */
|
||||||
|
int ff_req_grant (FF_SYNC_t sobj); /* Lock sync object */
|
||||||
|
void ff_rel_grant (FF_SYNC_t sobj); /* Unlock sync object */
|
||||||
|
int ff_del_syncobj (FF_SYNC_t sobj); /* Delete a sync object */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*--------------------------------------------------------------*/
|
||||||
|
/* Flags and offset address */
|
||||||
|
|
||||||
|
|
||||||
|
/* File access mode and open method flags (3rd argument of f_open) */
|
||||||
|
#define FA_READ 0x01
|
||||||
|
#define FA_WRITE 0x02
|
||||||
|
#define FA_OPEN_EXISTING 0x00
|
||||||
|
#define FA_CREATE_NEW 0x04
|
||||||
|
#define FA_CREATE_ALWAYS 0x08
|
||||||
|
#define FA_OPEN_ALWAYS 0x10
|
||||||
|
#define FA_OPEN_APPEND 0x30
|
||||||
|
|
||||||
|
/* Fast seek controls (2nd argument of f_lseek) */
|
||||||
|
#define CREATE_LINKMAP ((FSIZE_t)0 - 1)
|
||||||
|
|
||||||
|
/* Format options (2nd argument of f_mkfs) */
|
||||||
|
#define FM_FAT 0x01
|
||||||
|
#define FM_FAT32 0x02
|
||||||
|
#define FM_EXFAT 0x04
|
||||||
|
#define FM_ANY 0x07
|
||||||
|
#define FM_SFD 0x08
|
||||||
|
|
||||||
|
/* Filesystem type (FATFS.fs_type) */
|
||||||
|
#define FS_FAT12 1
|
||||||
|
#define FS_FAT16 2
|
||||||
|
#define FS_FAT32 3
|
||||||
|
#define FS_EXFAT 4
|
||||||
|
|
||||||
|
/* File attribute bits for directory entry (FILINFO.fattrib) */
|
||||||
|
#define AM_RDO 0x01 /* Read only */
|
||||||
|
#define AM_HID 0x02 /* Hidden */
|
||||||
|
#define AM_SYS 0x04 /* System */
|
||||||
|
#define AM_DIR 0x10 /* Directory */
|
||||||
|
#define AM_ARC 0x20 /* Archive */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* FF_DEFINED */
|
289
source/libs/fatfs/ffconf.h
Normal file
289
source/libs/fatfs/ffconf.h
Normal file
@ -0,0 +1,289 @@
|
|||||||
|
/*---------------------------------------------------------------------------/
|
||||||
|
/ FatFs - Configuration file
|
||||||
|
/---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#define FFCONF_DEF 63463 /* Revision ID */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------/
|
||||||
|
/ Function Configurations
|
||||||
|
/---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#define FF_FS_READONLY 0
|
||||||
|
/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
|
||||||
|
/ Read-only configuration removes writing API functions, f_write(), f_sync(),
|
||||||
|
/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
|
||||||
|
/ and optional writing functions as well. */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_FS_MINIMIZE 0
|
||||||
|
/* This option defines minimization level to remove some basic API functions.
|
||||||
|
/
|
||||||
|
/ 0: Basic functions are fully enabled.
|
||||||
|
/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
|
||||||
|
/ are removed.
|
||||||
|
/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
|
||||||
|
/ 3: f_lseek() function is removed in addition to 2. */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_USE_STRFUNC 0
|
||||||
|
/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf().
|
||||||
|
/
|
||||||
|
/ 0: Disable string functions.
|
||||||
|
/ 1: Enable without LF-CRLF conversion.
|
||||||
|
/ 2: Enable with LF-CRLF conversion. */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_USE_FIND 0
|
||||||
|
/* This option switches filtered directory read functions, f_findfirst() and
|
||||||
|
/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_USE_MKFS 0
|
||||||
|
/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_USE_FASTSEEK 0
|
||||||
|
/* This option switches fast seek function. (0:Disable or 1:Enable) */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_USE_EXPAND 0
|
||||||
|
/* This option switches f_expand function. (0:Disable or 1:Enable) */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_USE_CHMOD 0
|
||||||
|
/* This option switches attribute manipulation functions, f_chmod() and f_utime().
|
||||||
|
/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_USE_LABEL 0
|
||||||
|
/* This option switches volume label functions, f_getlabel() and f_setlabel().
|
||||||
|
/ (0:Disable or 1:Enable) */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_USE_FORWARD 0
|
||||||
|
/* This option switches f_forward() function. (0:Disable or 1:Enable) */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------/
|
||||||
|
/ Locale and Namespace Configurations
|
||||||
|
/---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#define FF_CODE_PAGE 850
|
||||||
|
/* This option specifies the OEM code page to be used on the target system.
|
||||||
|
/ Incorrect code page setting can cause a file open failure.
|
||||||
|
/
|
||||||
|
/ 437 - U.S.
|
||||||
|
/ 720 - Arabic
|
||||||
|
/ 737 - Greek
|
||||||
|
/ 771 - KBL
|
||||||
|
/ 775 - Baltic
|
||||||
|
/ 850 - Latin 1
|
||||||
|
/ 852 - Latin 2
|
||||||
|
/ 855 - Cyrillic
|
||||||
|
/ 857 - Turkish
|
||||||
|
/ 860 - Portuguese
|
||||||
|
/ 861 - Icelandic
|
||||||
|
/ 862 - Hebrew
|
||||||
|
/ 863 - Canadian French
|
||||||
|
/ 864 - Arabic
|
||||||
|
/ 865 - Nordic
|
||||||
|
/ 866 - Russian
|
||||||
|
/ 869 - Greek 2
|
||||||
|
/ 932 - Japanese (DBCS)
|
||||||
|
/ 936 - Simplified Chinese (DBCS)
|
||||||
|
/ 949 - Korean (DBCS)
|
||||||
|
/ 950 - Traditional Chinese (DBCS)
|
||||||
|
/ 0 - Include all code pages above and configured by f_setcp()
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_USE_LFN 3
|
||||||
|
#define FF_MAX_LFN 255
|
||||||
|
/* The FF_USE_LFN switches the support for LFN (long file name).
|
||||||
|
/
|
||||||
|
/ 0: Disable LFN. FF_MAX_LFN has no effect.
|
||||||
|
/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
|
||||||
|
/ 2: Enable LFN with dynamic working buffer on the STACK.
|
||||||
|
/ 3: Enable LFN with dynamic working buffer on the HEAP.
|
||||||
|
/
|
||||||
|
/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
|
||||||
|
/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
|
||||||
|
/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
|
||||||
|
/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
|
||||||
|
/ be in range of 12 to 255. It is recommended to be set 255 to fully support LFN
|
||||||
|
/ specification.
|
||||||
|
/ When use stack for the working buffer, take care on stack overflow. When use heap
|
||||||
|
/ memory for the working buffer, memory management functions, ff_memalloc() and
|
||||||
|
/ ff_memfree() in ffsystem.c, need to be added to the project. */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_LFN_UNICODE 0
|
||||||
|
/* This option switches the character encoding on the API when LFN is enabled.
|
||||||
|
/
|
||||||
|
/ 0: ANSI/OEM in current CP (TCHAR = char)
|
||||||
|
/ 1: Unicode in UTF-16 (TCHAR = WCHAR)
|
||||||
|
/ 2: Unicode in UTF-8 (TCHAR = char)
|
||||||
|
/ 3: Unicode in UTF-32 (TCHAR = DWORD)
|
||||||
|
/
|
||||||
|
/ Also behavior of string I/O functions will be affected by this option.
|
||||||
|
/ When LFN is not enabled, this option has no effect. */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_LFN_BUF 255
|
||||||
|
#define FF_SFN_BUF 12
|
||||||
|
/* This set of options defines size of file name members in the FILINFO structure
|
||||||
|
/ which is used to read out directory items. These values should be suffcient for
|
||||||
|
/ the file names to read. The maximum possible length of the read file name depends
|
||||||
|
/ on character encoding. When LFN is not enabled, these options have no effect. */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_STRF_ENCODE 0
|
||||||
|
/* When FF_LFN_UNICODE >= 1 with LFN enabled, string I/O functions, f_gets(),
|
||||||
|
/ f_putc(), f_puts and f_printf() convert the character encoding in it.
|
||||||
|
/ This option selects assumption of character encoding ON THE FILE to be
|
||||||
|
/ read/written via those functions.
|
||||||
|
/
|
||||||
|
/ 0: ANSI/OEM in current CP
|
||||||
|
/ 1: Unicode in UTF-16LE
|
||||||
|
/ 2: Unicode in UTF-16BE
|
||||||
|
/ 3: Unicode in UTF-8
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_FS_RPATH 0
|
||||||
|
/* This option configures support for relative path.
|
||||||
|
/
|
||||||
|
/ 0: Disable relative path and remove related functions.
|
||||||
|
/ 1: Enable relative path. f_chdir() and f_chdrive() are available.
|
||||||
|
/ 2: f_getcwd() function is available in addition to 1.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------/
|
||||||
|
/ Drive/Volume Configurations
|
||||||
|
/---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#define FF_VOLUMES 2
|
||||||
|
/* Number of volumes (logical drives) to be used. (1-10) */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_STR_VOLUME_ID 1
|
||||||
|
#define FF_VOLUME_STRS "sd", "emmc"
|
||||||
|
/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
|
||||||
|
/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
|
||||||
|
/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
|
||||||
|
/ logical drives. Number of items must not be less than FF_VOLUMES. Valid
|
||||||
|
/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are
|
||||||
|
/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is
|
||||||
|
/ not defined, a user defined volume string table needs to be defined as:
|
||||||
|
/
|
||||||
|
/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",...
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_MULTI_PARTITION 0
|
||||||
|
/* This option switches support for multiple volumes on the physical drive.
|
||||||
|
/ By default (0), each logical drive number is bound to the same physical drive
|
||||||
|
/ number and only an FAT volume found on the physical drive will be mounted.
|
||||||
|
/ When this function is enabled (1), each logical drive number can be bound to
|
||||||
|
/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
|
||||||
|
/ funciton will be available. */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_MIN_SS 512
|
||||||
|
#define FF_MAX_SS 512
|
||||||
|
/* This set of options configures the range of sector size to be supported. (512,
|
||||||
|
/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
|
||||||
|
/ harddisk. But a larger value may be required for on-board flash memory and some
|
||||||
|
/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
|
||||||
|
/ for variable sector size mode and disk_ioctl() function needs to implement
|
||||||
|
/ GET_SECTOR_SIZE command. */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_USE_TRIM 0
|
||||||
|
/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
|
||||||
|
/ To enable Trim function, also CTRL_TRIM command should be implemented to the
|
||||||
|
/ disk_ioctl() function. */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_FS_NOFSINFO 1
|
||||||
|
/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
|
||||||
|
/ option, and f_getfree() function at first time after volume mount will force
|
||||||
|
/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
|
||||||
|
/
|
||||||
|
/ bit0=0: Use free cluster count in the FSINFO if available.
|
||||||
|
/ bit0=1: Do not trust free cluster count in the FSINFO.
|
||||||
|
/ bit1=0: Use last allocated cluster number in the FSINFO if available.
|
||||||
|
/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------/
|
||||||
|
/ System Configurations
|
||||||
|
/---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#define FF_FS_TINY 0
|
||||||
|
/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
|
||||||
|
/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes.
|
||||||
|
/ Instead of private sector buffer eliminated from the file object, common sector
|
||||||
|
/ buffer in the filesystem object (FATFS) is used for the file data transfer. */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_FS_EXFAT 1
|
||||||
|
/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
|
||||||
|
/ To enable exFAT, also LFN needs to be enabled.
|
||||||
|
/ Note that enabling exFAT discards ANSI C (C89) compatibility. */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_FS_NORTC 1
|
||||||
|
#define FF_NORTC_MON 1
|
||||||
|
#define FF_NORTC_MDAY 1
|
||||||
|
#define FF_NORTC_YEAR 2018
|
||||||
|
/* The option FF_FS_NORTC switches timestamp function. If the system does not have
|
||||||
|
/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
|
||||||
|
/ the timestamp function. Every object modified by FatFs will have a fixed timestamp
|
||||||
|
/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
|
||||||
|
/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
|
||||||
|
/ added to the project to read current time form real-time clock. FF_NORTC_MON,
|
||||||
|
/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
|
||||||
|
/ These options have no effect at read-only configuration (FF_FS_READONLY = 1). */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_FS_LOCK 0
|
||||||
|
/* The option FF_FS_LOCK switches file lock function to control duplicated file open
|
||||||
|
/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
|
||||||
|
/ is 1.
|
||||||
|
/
|
||||||
|
/ 0: Disable file lock function. To avoid volume corruption, application program
|
||||||
|
/ should avoid illegal open, remove and rename to the open objects.
|
||||||
|
/ >0: Enable file lock function. The value defines how many files/sub-directories
|
||||||
|
/ can be opened simultaneously under file lock control. Note that the file
|
||||||
|
/ lock control is independent of re-entrancy. */
|
||||||
|
|
||||||
|
|
||||||
|
#define FF_FS_REENTRANT 0
|
||||||
|
#define FF_FS_TIMEOUT 1000
|
||||||
|
#define FF_SYNC_t HANDLE
|
||||||
|
/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
|
||||||
|
/ module itself. Note that regardless of this option, file access to different
|
||||||
|
/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
|
||||||
|
/ and f_fdisk() function, are always not re-entrant. Only file/directory access
|
||||||
|
/ to the same volume is under control of this function.
|
||||||
|
/
|
||||||
|
/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect.
|
||||||
|
/ 1: Enable re-entrancy. Also user provided synchronization handlers,
|
||||||
|
/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
|
||||||
|
/ function, must be added to the project. Samples are available in
|
||||||
|
/ option/syscall.c.
|
||||||
|
/
|
||||||
|
/ The FF_FS_TIMEOUT defines timeout period in unit of time tick.
|
||||||
|
/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
|
||||||
|
/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be
|
||||||
|
/ included somewhere in the scope of ff.h. */
|
||||||
|
|
||||||
|
/* #include <windows.h> // O/S definitions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*--- End of configuration options ---*/
|
39
source/libs/fatfs/ffsystem.c
Normal file
39
source/libs/fatfs/ffsystem.c
Normal file
@ -0,0 +1,39 @@
|
|||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
/* Sample Code of OS Dependent Functions for FatFs */
|
||||||
|
/* (C) ChaN, 2017 */
|
||||||
|
/* (C) CTCaer, 2018 */
|
||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
#include "ff.h"
|
||||||
|
#include "../../mem/heap.h"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#if FF_USE_LFN == 3 /* Dynamic memory allocation */
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
/* Allocate a memory block */
|
||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
void* ff_memalloc ( /* Returns pointer to the allocated memory block (null on not enough core) */
|
||||||
|
UINT msize /* Number of bytes to allocate */
|
||||||
|
)
|
||||||
|
{
|
||||||
|
return malloc(msize); /* Allocate a new memory block with POSIX API */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
/* Free a memory block */
|
||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
void ff_memfree (
|
||||||
|
void* mblock /* Pointer to the memory block to free (nothing to do for null) */
|
||||||
|
)
|
||||||
|
{
|
||||||
|
free(mblock); /* Free the memory block with POSIX API */
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
627
source/libs/fatfs/ffunicode.c
Normal file
627
source/libs/fatfs/ffunicode.c
Normal file
@ -0,0 +1,627 @@
|
|||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
/* Unicode handling functions for FatFs R0.13a */
|
||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
/* This module will occupy a huge memory in the .const section when the /
|
||||||
|
/ FatFs is configured for LFN with DBCS. If the system has any Unicode /
|
||||||
|
/ utilitiy for the code conversion, this module should be modified to use /
|
||||||
|
/ that function to avoid silly memory consumption. /
|
||||||
|
/-------------------------------------------------------------------------*/
|
||||||
|
/*
|
||||||
|
/ Copyright (C) 2017, ChaN, all right reserved.
|
||||||
|
/
|
||||||
|
/ FatFs module is an open source software. Redistribution and use of FatFs in
|
||||||
|
/ source and binary forms, with or without modification, are permitted provided
|
||||||
|
/ that the following condition is met:
|
||||||
|
/
|
||||||
|
/ 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
/ this condition and the following disclaimer.
|
||||||
|
/
|
||||||
|
/ This software is provided by the copyright holder and contributors "AS IS"
|
||||||
|
/ and any warranties related to this software are DISCLAIMED.
|
||||||
|
/ The copyright owner or contributors be NOT LIABLE for any damages caused
|
||||||
|
/ by use of this software.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#include "ff.h"
|
||||||
|
|
||||||
|
#if FF_USE_LFN /* This module is blanked when non-LFN configuration */
|
||||||
|
|
||||||
|
#if FF_DEFINED != 63463 /* Revision ID */
|
||||||
|
#error Wrong include file (ff.h).
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define MERGE2(a, b) a ## b
|
||||||
|
#define CVTBL(tbl, cp) MERGE2(tbl, cp)
|
||||||
|
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
/* Code Conversion Tables */
|
||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#if FF_CODE_PAGE == 437 || FF_CODE_PAGE == 0
|
||||||
|
static const WCHAR uc437[] = { /* CP437(U.S.) to Unicode conversion table */
|
||||||
|
0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
|
||||||
|
0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
|
||||||
|
0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
|
||||||
|
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
|
||||||
|
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
|
||||||
|
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
|
||||||
|
0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
|
||||||
|
0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
#if FF_CODE_PAGE == 720 || FF_CODE_PAGE == 0
|
||||||
|
static const WCHAR uc720[] = { /* CP720(Arabic) to Unicode conversion table */
|
||||||
|
0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000,
|
||||||
|
0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627,
|
||||||
|
0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB,
|
||||||
|
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
|
||||||
|
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
|
||||||
|
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
|
||||||
|
0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A,
|
||||||
|
0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
#if FF_CODE_PAGE == 737 || FF_CODE_PAGE == 0
|
||||||
|
static const WCHAR uc737[] = { /* CP737(Greek) to Unicode conversion table */
|
||||||
|
0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0,
|
||||||
|
0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8,
|
||||||
|
0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8,
|
||||||
|
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
|
||||||
|
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
|
||||||
|
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
|
||||||
|
0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E,
|
||||||
|
0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
#if FF_CODE_PAGE == 771 || FF_CODE_PAGE == 0
|
||||||
|
static const WCHAR uc771[] = { /* CP771(KBL) to Unicode conversion table */
|
||||||
|
0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
|
||||||
|
0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
|
||||||
|
0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
|
||||||
|
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510,
|
||||||
|
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
|
||||||
|
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x0104, 0x0105, 0x010C, 0x010D,
|
||||||
|
0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F,
|
||||||
|
0x0118, 0x0119, 0x0116, 0x0117, 0x012E, 0x012F, 0x0160, 0x0161, 0x0172, 0x0173, 0x016A, 0x016B, 0x017D, 0x017E, 0x25A0, 0x00A0
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
#if FF_CODE_PAGE == 775 || FF_CODE_PAGE == 0
|
||||||
|
static const WCHAR uc775[] = { /* CP775(Baltic) to Unicode conversion table */
|
||||||
|
0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5,
|
||||||
|
0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4,
|
||||||
|
0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB,
|
||||||
|
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510,
|
||||||
|
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D,
|
||||||
|
0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
|
||||||
|
0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019,
|
||||||
|
0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
#if FF_CODE_PAGE == 850 || FF_CODE_PAGE == 0
|
||||||
|
static const WCHAR uc850[] = { /* CP850(Latin 1) to Unicode conversion table */
|
||||||
|
0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
|
||||||
|
0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
|
||||||
|
0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
|
||||||
|
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
|
||||||
|
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
|
||||||
|
0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
|
||||||
|
0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
|
||||||
|
0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
#if FF_CODE_PAGE == 852 || FF_CODE_PAGE == 0
|
||||||
|
static const WCHAR uc852[] = { /* CP852(Latin 2) to Unicode conversion table */
|
||||||
|
0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106,
|
||||||
|
0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D,
|
||||||
|
0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB,
|
||||||
|
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510,
|
||||||
|
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
|
||||||
|
0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580,
|
||||||
|
0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4,
|
||||||
|
0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
#if FF_CODE_PAGE == 855 || FF_CODE_PAGE == 0
|
||||||
|
static const WCHAR uc855[] = { /* CP855(Cyrillic) to Unicode conversion table */
|
||||||
|
0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408,
|
||||||
|
0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A,
|
||||||
|
0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB,
|
||||||
|
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510,
|
||||||
|
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
|
||||||
|
0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580,
|
||||||
|
0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116,
|
||||||
|
0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
#if FF_CODE_PAGE == 857 || FF_CODE_PAGE == 0
|
||||||
|
static const WCHAR uc857[] = { /* CP857(Turkish) to Unicode conversion table */
|
||||||
|
0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5,
|
||||||
|
0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F,
|
||||||
|
0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
|
||||||
|
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
|
||||||
|
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
|
||||||
|
0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
|
||||||
|
0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4,
|
||||||
|
0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
#if FF_CODE_PAGE == 860 || FF_CODE_PAGE == 0
|
||||||
|
static const WCHAR uc860[] = { /* CP860(Portuguese) to Unicode conversion table */
|
||||||
|
0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E3, 0x00E0, 0x00C1, 0x00E7, 0x00EA, 0x00CA, 0x00E8, 0x00CD, 0x00D4, 0x00EC, 0x00C3, 0x00C2,
|
||||||
|
0x00C9, 0x00C0, 0x00C8, 0x00F4, 0x00F5, 0x00F2, 0x00DA, 0x00F9, 0x00CC, 0x00D5, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x20A7, 0x00D3,
|
||||||
|
0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00D2, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
|
||||||
|
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510,
|
||||||
|
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
|
||||||
|
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
|
||||||
|
0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
|
||||||
|
0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
#if FF_CODE_PAGE == 861 || FF_CODE_PAGE == 0
|
||||||
|
static const WCHAR uc861[] = { /* CP861(Icelandic) to Unicode conversion table */
|
||||||
|
0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00D0, 0x00F0, 0x00DE, 0x00C4, 0x00C5,
|
||||||
|
0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00FE, 0x00FB, 0x00DD, 0x00FD, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192,
|
||||||
|
0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00C1, 0x00CD, 0x00D3, 0x00DA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
|
||||||
|
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
|
||||||
|
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
|
||||||
|
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
|
||||||
|
0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
|
||||||
|
0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
#if FF_CODE_PAGE == 862 || FF_CODE_PAGE == 0
|
||||||
|
static const WCHAR uc862[] = { /* CP862(Hebrew) to Unicode conversion table */
|
||||||
|
0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
|
||||||
|
0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
|
||||||
|
0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
|
||||||
|
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
|
||||||
|
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
|
||||||
|
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
|
||||||
|
0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
|
||||||
|
0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
#if FF_CODE_PAGE == 863 || FF_CODE_PAGE == 0
|
||||||
|
static const WCHAR uc863[] = { /* CP863(Canadian French) to Unicode conversion table */
|
||||||
|
0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00C2, 0x00E0, 0x00B6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x2017, 0x00C0,
|
||||||
|
0x00C9, 0x00C8, 0x00CA, 0x00F4, 0x00CB, 0x00CF, 0x00FB, 0x00F9, 0x00A4, 0x00D4, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x00DB, 0x0192,
|
||||||
|
0x00A6, 0x00B4, 0x00F3, 0x00FA, 0x00A8, 0x00BB, 0x00B3, 0x00AF, 0x00CE, 0x3210, 0x00AC, 0x00BD, 0x00BC, 0x00BE, 0x00AB, 0x00BB,
|
||||||
|
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
|
||||||
|
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
|
||||||
|
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
|
||||||
|
0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2219,
|
||||||
|
0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
#if FF_CODE_PAGE == 864 || FF_CODE_PAGE == 0
|
||||||
|
static const WCHAR uc864[] = { /* CP864(Arabic) to Unicode conversion table */
|
||||||
|
0x00B0, 0x00B7, 0x2219, 0x221A, 0x2592, 0x2500, 0x2502, 0x253C, 0x2524, 0x252C, 0x251C, 0x2534, 0x2510, 0x250C, 0x2514, 0x2518,
|
||||||
|
0x03B2, 0x221E, 0x03C6, 0x00B1, 0x00BD, 0x00BC, 0x2248, 0x00AB, 0x00BB, 0xFEF7, 0xFEF8, 0x0000, 0x0000, 0xFEFB, 0xFEFC, 0x0000,
|
||||||
|
0x00A0, 0x00AD, 0xFE82, 0x00A3, 0x00A4, 0xFE84, 0x0000, 0x20AC, 0xFE8E, 0xFE8F, 0xFE95, 0xFE99, 0x060C, 0xFE9D, 0xFEA1, 0xFEA5,
|
||||||
|
0x0660, 0x0661, 0x0662, 0x0663, 0x0664, 0x0665, 0x0666, 0x0667, 0x0668, 0x0669, 0xFED1, 0x061B, 0xFEB1, 0xFEB5, 0xFEB9, 0x061F,
|
||||||
|
0x00A2, 0xFE80, 0xFE81, 0xFE83, 0xFE85, 0xFECA, 0xFE8B, 0xFE8D, 0xFE91, 0xFE93, 0xFE97, 0xFE9B, 0xFE9F, 0xFEA3, 0xFEA7, 0xFEA9,
|
||||||
|
0xFEAB, 0xFEAD, 0xFEAF, 0xFEB3, 0xFEB7, 0xFEBB, 0xFEBF, 0xFEC1, 0xFEC5, 0xFECB, 0xFECF, 0x00A6, 0x00AC, 0x00F7, 0x00D7, 0xFEC9,
|
||||||
|
0x0640, 0xFED3, 0xFED7, 0xFEDB, 0xFEDF, 0xFEE3, 0xFEE7, 0xFEEB, 0xFEED, 0xFEEF, 0xFEF3, 0xFEBD, 0xFECC, 0xFECE, 0xFECD, 0xFEE1,
|
||||||
|
0xFE7D, 0x0651, 0xFEE5, 0xFEE9, 0xFEEC, 0xFEF0, 0xFEF2, 0xFED0, 0xFED5, 0xFEF5, 0xFEF6, 0xFEDD, 0xFED9, 0xFEF1, 0x25A0, 0x0000
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
#if FF_CODE_PAGE == 865 || FF_CODE_PAGE == 0
|
||||||
|
static const WCHAR uc865[] = { /* CP865(Nordic) to Unicode conversion table */
|
||||||
|
0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
|
||||||
|
0x00C5, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192,
|
||||||
|
0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00A4,
|
||||||
|
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510,
|
||||||
|
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
|
||||||
|
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
|
||||||
|
0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
|
||||||
|
0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
#if FF_CODE_PAGE == 866 || FF_CODE_PAGE == 0
|
||||||
|
static const WCHAR uc866[] = { /* CP866(Russian) to Unicode conversion table */
|
||||||
|
0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
|
||||||
|
0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
|
||||||
|
0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
|
||||||
|
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
|
||||||
|
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
|
||||||
|
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
|
||||||
|
0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F,
|
||||||
|
0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
#if FF_CODE_PAGE == 869 || FF_CODE_PAGE == 0
|
||||||
|
static const WCHAR uc869[] = { /* CP869(Greek 2) to Unicode conversion table */
|
||||||
|
0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x0386, 0x00B7, 0x00B7, 0x00AC, 0x00A6, 0x2018, 0x2019, 0x0388, 0x2015, 0x0389,
|
||||||
|
0x038A, 0x03AA, 0x038C, 0x00B7, 0x00B7, 0x038E, 0x03AB, 0x00A9, 0x038F, 0x00B2, 0x00B3, 0x03AC, 0x00A3, 0x03AD, 0x03AE, 0x03AF,
|
||||||
|
0x03CA, 0x0390, 0x03CC, 0x03CD, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x00BD, 0x0398, 0x0399, 0x00AB, 0x00BB,
|
||||||
|
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x039A, 0x039B, 0x039C, 0x039D, 0x2563, 0x2551, 0x2557, 0x255D, 0x039E, 0x039F, 0x2510,
|
||||||
|
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0A30, 0x03A1, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x03A3,
|
||||||
|
0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x2518, 0x250C, 0x2588, 0x2584, 0x03B4, 0x03B5, 0x2580,
|
||||||
|
0x03B6, 0x03B7, 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x0384,
|
||||||
|
0x00AD, 0x00B1, 0x03C5, 0x03C6, 0x03C7, 0x00A7, 0x03C8, 0x0385, 0x00B0, 0x00A8, 0x03C9, 0x03CB, 0x03B0, 0x03CE, 0x25A0, 0x00A0
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
/* OEM <==> Unicode conversions for static code page configuration */
|
||||||
|
/* SBCS fixed code page */
|
||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#if FF_CODE_PAGE != 0 && FF_CODE_PAGE < 900
|
||||||
|
WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */
|
||||||
|
DWORD uni, /* UTF-16 encoded character to be converted */
|
||||||
|
WORD cp /* Code page for the conversion */
|
||||||
|
)
|
||||||
|
{
|
||||||
|
WCHAR c = 0;
|
||||||
|
const WCHAR *p = CVTBL(uc, FF_CODE_PAGE);
|
||||||
|
|
||||||
|
|
||||||
|
if (uni < 0x80) { /* ASCII? */
|
||||||
|
c = (WCHAR)uni;
|
||||||
|
|
||||||
|
} else { /* Non-ASCII */
|
||||||
|
if (uni < 0x10000 && cp == FF_CODE_PAGE) { /* Is it in BMP and valid code page? */
|
||||||
|
for (c = 0; c < 0x80 && uni != p[c]; c++) ;
|
||||||
|
c = (c + 0x80) & 0xFF;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return c;
|
||||||
|
}
|
||||||
|
|
||||||
|
WCHAR ff_oem2uni ( /* Returns Unicode character, zero on error */
|
||||||
|
WCHAR oem, /* OEM code to be converted */
|
||||||
|
WORD cp /* Code page for the conversion */
|
||||||
|
)
|
||||||
|
{
|
||||||
|
WCHAR c = 0;
|
||||||
|
const WCHAR *p = CVTBL(uc, FF_CODE_PAGE);
|
||||||
|
|
||||||
|
|
||||||
|
if (oem < 0x80) { /* ASCII? */
|
||||||
|
c = oem;
|
||||||
|
|
||||||
|
} else { /* Extended char */
|
||||||
|
if (cp == FF_CODE_PAGE) { /* Is it a valid code page? */
|
||||||
|
if (oem < 0x100) c = p[oem - 0x80];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return c;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
/* OEM <==> Unicode conversions for static code page configuration */
|
||||||
|
/* DBCS fixed code page */
|
||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#if FF_CODE_PAGE >= 900
|
||||||
|
WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */
|
||||||
|
DWORD uni, /* UTF-16 encoded character to be converted */
|
||||||
|
WORD cp /* Code page for the conversion */
|
||||||
|
)
|
||||||
|
{
|
||||||
|
const WCHAR *p;
|
||||||
|
WCHAR c = 0, uc;
|
||||||
|
UINT i = 0, n, li, hi;
|
||||||
|
|
||||||
|
|
||||||
|
if (uni < 0x80) { /* ASCII? */
|
||||||
|
c = (WCHAR)uni;
|
||||||
|
|
||||||
|
} else { /* Non-ASCII */
|
||||||
|
if (uni < 0x10000 && cp == FF_CODE_PAGE) { /* Is it in BMP and valid code page? */
|
||||||
|
uc = (WCHAR)uni;
|
||||||
|
p = CVTBL(uni2oem, FF_CODE_PAGE);
|
||||||
|
hi = sizeof CVTBL(uni2oem, FF_CODE_PAGE) / 4 - 1;
|
||||||
|
li = 0;
|
||||||
|
for (n = 16; n; n--) {
|
||||||
|
i = li + (hi - li) / 2;
|
||||||
|
if (uc == p[i * 2]) break;
|
||||||
|
if (uc > p[i * 2]) {
|
||||||
|
li = i;
|
||||||
|
} else {
|
||||||
|
hi = i;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (n != 0) c = p[i * 2 + 1];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return c;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
WCHAR ff_oem2uni ( /* Returns Unicode character, zero on error */
|
||||||
|
WCHAR oem, /* OEM code to be converted */
|
||||||
|
WORD cp /* Code page for the conversion */
|
||||||
|
)
|
||||||
|
{
|
||||||
|
const WCHAR *p;
|
||||||
|
WCHAR c = 0;
|
||||||
|
UINT i = 0, n, li, hi;
|
||||||
|
|
||||||
|
|
||||||
|
if (oem < 0x80) { /* ASCII? */
|
||||||
|
c = oem;
|
||||||
|
|
||||||
|
} else { /* Extended char */
|
||||||
|
if (cp == FF_CODE_PAGE) { /* Is it valid code page? */
|
||||||
|
p = CVTBL(oem2uni, FF_CODE_PAGE);
|
||||||
|
hi = sizeof CVTBL(oem2uni, FF_CODE_PAGE) / 4 - 1;
|
||||||
|
li = 0;
|
||||||
|
for (n = 16; n; n--) {
|
||||||
|
i = li + (hi - li) / 2;
|
||||||
|
if (oem == p[i * 2]) break;
|
||||||
|
if (oem > p[i * 2]) {
|
||||||
|
li = i;
|
||||||
|
} else {
|
||||||
|
hi = i;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (n != 0) c = p[i * 2 + 1];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return c;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
/* OEM <==> Unicode conversions for dynamic code page configuration */
|
||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#if FF_CODE_PAGE == 0
|
||||||
|
|
||||||
|
static const WORD cp_code[] = { 437, 720, 737, 771, 775, 850, 852, 855, 857, 860, 861, 862, 863, 864, 865, 866, 869, 0};
|
||||||
|
static const WCHAR* const cp_table[] = {uc437, uc720, uc737, uc771, uc775, uc850, uc852, uc855, uc857, uc860, uc861, uc862, uc863, uc864, uc865, uc866, uc869, 0};
|
||||||
|
|
||||||
|
|
||||||
|
WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */
|
||||||
|
DWORD uni, /* UTF-16 encoded character to be converted */
|
||||||
|
WORD cp /* Code page for the conversion */
|
||||||
|
)
|
||||||
|
{
|
||||||
|
const WCHAR *p;
|
||||||
|
WCHAR c = 0, uc;
|
||||||
|
UINT i, n, li, hi;
|
||||||
|
|
||||||
|
|
||||||
|
if (uni < 0x80) { /* ASCII? */
|
||||||
|
c = (WCHAR)uni;
|
||||||
|
|
||||||
|
} else { /* Non-ASCII */
|
||||||
|
if (uni < 0x10000) { /* Is it in BMP? */
|
||||||
|
uc = (WCHAR)uni;
|
||||||
|
p = 0;
|
||||||
|
if (cp < 900) { /* SBCS */
|
||||||
|
for (i = 0; cp_code[i] != 0 && cp_code[i] != cp; i++) ; /* Get conversion table */
|
||||||
|
p = cp_table[i];
|
||||||
|
if (p) { /* Is it valid code page ? */
|
||||||
|
for (c = 0; c < 0x80 && uc != p[c]; c++) ; /* Find OEM code in the table */
|
||||||
|
c = (c + 0x80) & 0xFF;
|
||||||
|
}
|
||||||
|
} else { /* DBCS */
|
||||||
|
switch (cp) { /* Get conversion table */
|
||||||
|
case 932 : p = uni2oem932; hi = sizeof uni2oem932 / 4 - 1; break;
|
||||||
|
case 936 : p = uni2oem936; hi = sizeof uni2oem936 / 4 - 1; break;
|
||||||
|
case 949 : p = uni2oem949; hi = sizeof uni2oem949 / 4 - 1; break;
|
||||||
|
case 950 : p = uni2oem950; hi = sizeof uni2oem950 / 4 - 1; break;
|
||||||
|
}
|
||||||
|
if (p) { /* Is it valid code page? */
|
||||||
|
li = 0;
|
||||||
|
for (n = 16; n; n--) { /* Find OEM code */
|
||||||
|
i = li + (hi - li) / 2;
|
||||||
|
if (uc == p[i * 2]) break;
|
||||||
|
if (uc > p[i * 2]) {
|
||||||
|
li = i;
|
||||||
|
} else {
|
||||||
|
hi = i;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (n != 0) c = p[i * 2 + 1];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return c;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
WCHAR ff_oem2uni ( /* Returns Unicode character, zero on error */
|
||||||
|
WCHAR oem, /* OEM code to be converted (DBC if >=0x100) */
|
||||||
|
WORD cp /* Code page for the conversion */
|
||||||
|
)
|
||||||
|
{
|
||||||
|
const WCHAR *p;
|
||||||
|
WCHAR c = 0;
|
||||||
|
UINT i, n, li, hi;
|
||||||
|
|
||||||
|
|
||||||
|
if (oem < 0x80) { /* ASCII? */
|
||||||
|
c = oem;
|
||||||
|
|
||||||
|
} else { /* Extended char */
|
||||||
|
p = 0;
|
||||||
|
if (cp < 900) { /* SBCS */
|
||||||
|
for (i = 0; cp_code[i] != 0 && cp_code[i] != cp; i++) ; /* Get table */
|
||||||
|
p = cp_table[i];
|
||||||
|
if (p) { /* Is it a valid CP ? */
|
||||||
|
if (oem < 0x100) c = p[oem - 0x80];
|
||||||
|
}
|
||||||
|
} else { /* DBCS */
|
||||||
|
switch (cp) {
|
||||||
|
case 932 : p = oem2uni932; hi = sizeof oem2uni932 / 4 - 1; break;
|
||||||
|
case 936 : p = oem2uni936; hi = sizeof oem2uni936 / 4 - 1; break;
|
||||||
|
case 949 : p = oem2uni949; hi = sizeof oem2uni949 / 4 - 1; break;
|
||||||
|
case 950 : p = oem2uni950; hi = sizeof oem2uni950 / 4 - 1; break;
|
||||||
|
}
|
||||||
|
if (p) {
|
||||||
|
li = 0;
|
||||||
|
for (n = 16; n; n--) {
|
||||||
|
i = li + (hi - li) / 2;
|
||||||
|
if (oem == p[i * 2]) break;
|
||||||
|
if (oem > p[i * 2]) {
|
||||||
|
li = i;
|
||||||
|
} else {
|
||||||
|
hi = i;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (n != 0) c = p[i * 2 + 1];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return c;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
/* Unicode up-case conversion */
|
||||||
|
/*------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
DWORD ff_wtoupper ( /* Returns up-converted code point */
|
||||||
|
DWORD uni /* Unicode code point to be up-converted */
|
||||||
|
)
|
||||||
|
{
|
||||||
|
const WORD *p;
|
||||||
|
WORD uc, bc, nc, cmd;
|
||||||
|
static const WORD cvt1[] = { /* Compressed up conversion table for U+0000 - U+0FFF */
|
||||||
|
/* Basic Latin */
|
||||||
|
0x0061,0x031A,
|
||||||
|
/* Latin-1 Supplement */
|
||||||
|
0x00E0,0x0317,
|
||||||
|
0x00F8,0x0307,
|
||||||
|
0x00FF,0x0001,0x0178,
|
||||||
|
/* Latin Extended-A */
|
||||||
|
0x0100,0x0130,
|
||||||
|
0x0132,0x0106,
|
||||||
|
0x0139,0x0110,
|
||||||
|
0x014A,0x012E,
|
||||||
|
0x0179,0x0106,
|
||||||
|
/* Latin Extended-B */
|
||||||
|
0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA,
|
||||||
|
0x01CD,0x0110,
|
||||||
|
0x01DD,0x0001,0x018E,
|
||||||
|
0x01DE,0x0112,
|
||||||
|
0x01F3,0x0003,0x01F1,0x01F4,0x01F4,
|
||||||
|
0x01F8,0x0128,
|
||||||
|
0x0222,0x0112,
|
||||||
|
0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241,
|
||||||
|
0x0246,0x010A,
|
||||||
|
/* IPA Extensions */
|
||||||
|
0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7,
|
||||||
|
/* Greek, Coptic */
|
||||||
|
0x037B,0x0003,0x03FD,0x03FE,0x03FF,
|
||||||
|
0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A,
|
||||||
|
0x03B1,0x0311,
|
||||||
|
0x03C2,0x0002,0x03A3,0x03A3,
|
||||||
|
0x03C4,0x0308,
|
||||||
|
0x03CC,0x0003,0x038C,0x038E,0x038F,
|
||||||
|
0x03D8,0x0118,
|
||||||
|
0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA,
|
||||||
|
/* Cyrillic */
|
||||||
|
0x0430,0x0320,
|
||||||
|
0x0450,0x0710,
|
||||||
|
0x0460,0x0122,
|
||||||
|
0x048A,0x0136,
|
||||||
|
0x04C1,0x010E,
|
||||||
|
0x04CF,0x0001,0x04C0,
|
||||||
|
0x04D0,0x0144,
|
||||||
|
/* Armenian */
|
||||||
|
0x0561,0x0426,
|
||||||
|
|
||||||
|
0x0000 /* EOT */
|
||||||
|
};
|
||||||
|
static const WORD cvt2[] = { /* Compressed up conversion table for U+1000 - U+FFFF */
|
||||||
|
/* Phonetic Extensions */
|
||||||
|
0x1D7D,0x0001,0x2C63,
|
||||||
|
/* Latin Extended Additional */
|
||||||
|
0x1E00,0x0196,
|
||||||
|
0x1EA0,0x015A,
|
||||||
|
/* Greek Extended */
|
||||||
|
0x1F00,0x0608,
|
||||||
|
0x1F10,0x0606,
|
||||||
|
0x1F20,0x0608,
|
||||||
|
0x1F30,0x0608,
|
||||||
|
0x1F40,0x0606,
|
||||||
|
0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F,
|
||||||
|
0x1F60,0x0608,
|
||||||
|
0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB,
|
||||||
|
0x1F80,0x0608,
|
||||||
|
0x1F90,0x0608,
|
||||||
|
0x1FA0,0x0608,
|
||||||
|
0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC,
|
||||||
|
0x1FCC,0x0001,0x1FC3,
|
||||||
|
0x1FD0,0x0602,
|
||||||
|
0x1FE0,0x0602,
|
||||||
|
0x1FE5,0x0001,0x1FEC,
|
||||||
|
0x1FF3,0x0001,0x1FFC,
|
||||||
|
/* Letterlike Symbols */
|
||||||
|
0x214E,0x0001,0x2132,
|
||||||
|
/* Number forms */
|
||||||
|
0x2170,0x0210,
|
||||||
|
0x2184,0x0001,0x2183,
|
||||||
|
/* Enclosed Alphanumerics */
|
||||||
|
0x24D0,0x051A,
|
||||||
|
0x2C30,0x042F,
|
||||||
|
/* Latin Extended-C */
|
||||||
|
0x2C60,0x0102,
|
||||||
|
0x2C67,0x0106, 0x2C75,0x0102,
|
||||||
|
/* Coptic */
|
||||||
|
0x2C80,0x0164,
|
||||||
|
/* Georgian Supplement */
|
||||||
|
0x2D00,0x0826,
|
||||||
|
/* Full-width */
|
||||||
|
0xFF41,0x031A,
|
||||||
|
|
||||||
|
0x0000 /* EOT */
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
if (uni < 0x10000) { /* Is it in BMP? */
|
||||||
|
uc = (WORD)uni;
|
||||||
|
p = uc < 0x1000 ? cvt1 : cvt2;
|
||||||
|
for (;;) {
|
||||||
|
bc = *p++; /* Get the block base */
|
||||||
|
if (bc == 0 || uc < bc) break; /* Not matched? */
|
||||||
|
nc = *p++; cmd = nc >> 8; nc &= 0xFF; /* Get processing command and block size */
|
||||||
|
if (uc < bc + nc) { /* In the block? */
|
||||||
|
switch (cmd) {
|
||||||
|
case 0: uc = p[uc - bc]; break; /* Table conversion */
|
||||||
|
case 1: uc -= (uc - bc) & 1; break; /* Case pairs */
|
||||||
|
case 2: uc -= 16; break; /* Shift -16 */
|
||||||
|
case 3: uc -= 32; break; /* Shift -32 */
|
||||||
|
case 4: uc -= 48; break; /* Shift -48 */
|
||||||
|
case 5: uc -= 26; break; /* Shift -26 */
|
||||||
|
case 6: uc += 8; break; /* Shift +8 */
|
||||||
|
case 7: uc -= 80; break; /* Shift -80 */
|
||||||
|
case 8: uc -= 0x1C60; break; /* Shift -0x1C60 */
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
if (cmd == 0) p += nc; /* Skip table if needed */
|
||||||
|
}
|
||||||
|
uni = uc;
|
||||||
|
}
|
||||||
|
|
||||||
|
return uni;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* #if FF_USE_LFN */
|
23
source/link.ld
Normal file
23
source/link.ld
Normal file
@ -0,0 +1,23 @@
|
|||||||
|
ENTRY(_start)
|
||||||
|
|
||||||
|
SECTIONS {
|
||||||
|
PROVIDE(__ipl_start = IPL_LOAD_ADDR);
|
||||||
|
. = __ipl_start;
|
||||||
|
.text : {
|
||||||
|
*(.text._start);
|
||||||
|
. = . + 36;
|
||||||
|
*(.text*);
|
||||||
|
}
|
||||||
|
.data : {
|
||||||
|
*(.data*);
|
||||||
|
*(.rodata*);
|
||||||
|
}
|
||||||
|
. = ALIGN(0x10);
|
||||||
|
__ipl_end = .;
|
||||||
|
.bss : {
|
||||||
|
__bss_start = .;
|
||||||
|
*(COMMON)
|
||||||
|
*(.bss*)
|
||||||
|
__bss_end = .;
|
||||||
|
}
|
||||||
|
}
|
220
source/main.c
Normal file
220
source/main.c
Normal file
@ -0,0 +1,220 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include "gfx/di.h"
|
||||||
|
#include "gfx/gfx.h"
|
||||||
|
#include "libs/fatfs/ff.h"
|
||||||
|
#include "mem/heap.h"
|
||||||
|
#include "power/max77620.h"
|
||||||
|
#include "rtc/max77620-rtc.h"
|
||||||
|
#include "soc/hw_init.h"
|
||||||
|
#include "soc/i2c.h"
|
||||||
|
#include "soc/pmc.h"
|
||||||
|
#include "soc/t210.h"
|
||||||
|
#include "storage/sdmmc.h"
|
||||||
|
#include "utils/btn.h"
|
||||||
|
#include "utils/util.h"
|
||||||
|
|
||||||
|
#include "keys/keys.h"
|
||||||
|
|
||||||
|
gfx_ctxt_t gfx_ctxt;
|
||||||
|
gfx_con_t gfx_con;
|
||||||
|
|
||||||
|
#define EPRINTF(text) gfx_printf(&gfx_con, "%k"text"%k\n", 0xFFFF0000, 0xFFCCCCCC)
|
||||||
|
#define EPRINTFARGS(text, args...) gfx_printf(&gfx_con, "%k"text"%k\n", 0xFFFF0000, args, 0xFFCCCCCC)
|
||||||
|
|
||||||
|
sdmmc_t sd_sdmmc;
|
||||||
|
sdmmc_storage_t sd_storage;
|
||||||
|
FATFS sd_fs;
|
||||||
|
static bool sd_mounted;
|
||||||
|
|
||||||
|
boot_cfg_t *b_cfg;
|
||||||
|
|
||||||
|
bool sd_mount()
|
||||||
|
{
|
||||||
|
if (sd_mounted)
|
||||||
|
return true;
|
||||||
|
|
||||||
|
if (!sdmmc_storage_init_sd(&sd_storage, &sd_sdmmc, SDMMC_1, SDMMC_BUS_WIDTH_4, 11))
|
||||||
|
{
|
||||||
|
EPRINTF("Failed to init SD card.\nMake sure that it is inserted.\nOr that SD reader is properly seated!");
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
int res = 0;
|
||||||
|
res = f_mount(&sd_fs, "", 1);
|
||||||
|
if (res == FR_OK)
|
||||||
|
{
|
||||||
|
sd_mounted = 1;
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
EPRINTFARGS("Failed to mount SD card (FatFS Error %d).\nMake sure that a FAT partition exists..", res);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
void sd_unmount()
|
||||||
|
{
|
||||||
|
if (sd_mounted)
|
||||||
|
{
|
||||||
|
f_mount(NULL, "", 1);
|
||||||
|
sdmmc_storage_end(&sd_storage);
|
||||||
|
sd_mounted = false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void *sd_file_read(char *path)
|
||||||
|
{
|
||||||
|
FIL fp;
|
||||||
|
if (f_open(&fp, path, FA_READ) != FR_OK)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
u32 size = f_size(&fp);
|
||||||
|
void *buf = malloc(size);
|
||||||
|
|
||||||
|
u8 *ptr = buf;
|
||||||
|
while (size > 0)
|
||||||
|
{
|
||||||
|
u32 rsize = MIN(size, 512 * 512);
|
||||||
|
if (f_read(&fp, ptr, rsize, NULL) != FR_OK)
|
||||||
|
{
|
||||||
|
free(buf);
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
ptr += rsize;
|
||||||
|
size -= rsize;
|
||||||
|
}
|
||||||
|
|
||||||
|
f_close(&fp);
|
||||||
|
|
||||||
|
return buf;
|
||||||
|
}
|
||||||
|
|
||||||
|
int sd_save_to_file(void *buf, u32 size, const char *filename)
|
||||||
|
{
|
||||||
|
FIL fp;
|
||||||
|
u32 res = 0;
|
||||||
|
res = f_open(&fp, filename, FA_CREATE_ALWAYS | FA_WRITE);
|
||||||
|
if (res)
|
||||||
|
{
|
||||||
|
EPRINTFARGS("Error (%d) creating file\n%s.\n", res, filename);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
f_sync(&fp);
|
||||||
|
f_write(&fp, buf, size, NULL);
|
||||||
|
f_close(&fp);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void panic(u32 val)
|
||||||
|
{
|
||||||
|
// Set panic code.
|
||||||
|
PMC(APBDEV_PMC_SCRATCH200) = val;
|
||||||
|
//PMC(APBDEV_PMC_CRYPTO_OP) = 1; // Disable SE.
|
||||||
|
TMR(TIMER_WDT4_UNLOCK_PATTERN) = TIMER_MAGIC_PTRN;
|
||||||
|
TMR(TIMER_TMR9_TMR_PTV) = TIMER_EN | TIMER_PER_EN;
|
||||||
|
TMR(TIMER_WDT4_CONFIG) = TIMER_SRC(9) | TIMER_PER(1) | TIMER_PMCRESET_EN;
|
||||||
|
TMR(TIMER_WDT4_COMMAND) = TIMER_START_CNT;
|
||||||
|
while (1)
|
||||||
|
;
|
||||||
|
}
|
||||||
|
|
||||||
|
void reboot_normal()
|
||||||
|
{
|
||||||
|
sd_unmount();
|
||||||
|
display_end();
|
||||||
|
panic(0x21); // Bypass fuse programming in package1.
|
||||||
|
}
|
||||||
|
|
||||||
|
void reboot_rcm()
|
||||||
|
{
|
||||||
|
sd_unmount();
|
||||||
|
display_end();
|
||||||
|
PMC(APBDEV_PMC_SCRATCH0) = 2; // Reboot into rcm.
|
||||||
|
PMC(APBDEV_PMC_CNTRL) |= PMC_CNTRL_MAIN_RST;
|
||||||
|
while (true)
|
||||||
|
usleep(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
void power_off()
|
||||||
|
{
|
||||||
|
sd_unmount();
|
||||||
|
max77620_rtc_stop_alarm();
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, MAX77620_ONOFFCNFG1_PWR_OFF);
|
||||||
|
}
|
||||||
|
|
||||||
|
// This is a safe and unused DRAM region for our payloads.
|
||||||
|
// IPL_LOAD_ADDR is defined in makefile.
|
||||||
|
#define EXT_PAYLOAD_ADDR 0xC03C0000
|
||||||
|
#define PATCHED_RELOC_SZ 0x94
|
||||||
|
#define RCM_PAYLOAD_ADDR (EXT_PAYLOAD_ADDR + ALIGN(PATCHED_RELOC_SZ, 0x10))
|
||||||
|
#define PAYLOAD_ENTRY 0x40010000
|
||||||
|
#define CBFS_SDRAM_EN_ADDR 0x4003e000
|
||||||
|
#define COREBOOT_ADDR (0xD0000000 - 0x100000)
|
||||||
|
|
||||||
|
void (*ext_payload_ptr)() = (void *)EXT_PAYLOAD_ADDR;
|
||||||
|
void (*update_ptr)() = (void *)RCM_PAYLOAD_ADDR;
|
||||||
|
|
||||||
|
void reloc_patcher(u32 payload_dst, u32 payload_src, u32 payload_size)
|
||||||
|
{
|
||||||
|
static const u32 START_OFF = 0x7C;
|
||||||
|
static const u32 STACK_OFF = 0x80;
|
||||||
|
static const u32 PAYLOAD_END_OFF = 0x84;
|
||||||
|
static const u32 IPL_START_OFF = 0x88;
|
||||||
|
|
||||||
|
memcpy((u8 *)payload_src, (u8 *)IPL_LOAD_ADDR, PATCHED_RELOC_SZ);
|
||||||
|
|
||||||
|
*(vu32 *)(payload_src + START_OFF) = payload_dst - ALIGN(PATCHED_RELOC_SZ, 0x10);
|
||||||
|
*(vu32 *)(payload_src + PAYLOAD_END_OFF) = payload_dst + payload_size;
|
||||||
|
*(vu32 *)(payload_src + STACK_OFF) = 0x40008000;
|
||||||
|
*(vu32 *)(payload_src + IPL_START_OFF) = payload_dst;
|
||||||
|
|
||||||
|
if (payload_size == 0x7000)
|
||||||
|
{
|
||||||
|
memcpy((u8 *)(payload_src + ALIGN(PATCHED_RELOC_SZ, 0x10)), (u8 *)COREBOOT_ADDR, 0x7000); //Bootblock
|
||||||
|
*(vu32 *)CBFS_SDRAM_EN_ADDR = 0x4452414D;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
extern void pivot_stack(u32 stack_top);
|
||||||
|
|
||||||
|
void ipl_main() {
|
||||||
|
b_cfg = (boot_cfg_t *)(IPL_LOAD_ADDR + PATCHED_RELOC_SZ);
|
||||||
|
|
||||||
|
config_hw();
|
||||||
|
pivot_stack(0x90010000);
|
||||||
|
heap_init(0x90020000);
|
||||||
|
|
||||||
|
display_init();
|
||||||
|
u32 *fb = display_init_framebuffer();
|
||||||
|
gfx_init_ctxt(&gfx_ctxt, fb, 720, 1280, 720);
|
||||||
|
gfx_con_init(&gfx_con, &gfx_ctxt);
|
||||||
|
display_backlight_pwm_init();
|
||||||
|
|
||||||
|
sd_mount();
|
||||||
|
dump_keys();
|
||||||
|
}
|
667
source/mem/emc.h
Normal file
667
source/mem/emc.h
Normal file
@ -0,0 +1,667 @@
|
|||||||
|
/*
|
||||||
|
* arch/arm/mach-tegra/tegra21_emc.h
|
||||||
|
*
|
||||||
|
* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License along
|
||||||
|
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _EMC_H_
|
||||||
|
#define _EMC_H_
|
||||||
|
|
||||||
|
#define EMC_DBG 0x8
|
||||||
|
#define EMC_CFG 0xC
|
||||||
|
#define EMC_CONFIG_SAMPLE_DELAY 0x5f0
|
||||||
|
#define EMC_CFG_UPDATE 0x5f4
|
||||||
|
#define EMC_ADR_CFG 0x10
|
||||||
|
#define EMC_REFCTRL 0x20
|
||||||
|
#define EMC_PIN 0x24
|
||||||
|
#define EMC_TIMING_CONTROL 0x28
|
||||||
|
#define EMC_RC 0x2c
|
||||||
|
#define EMC_RFC 0x30
|
||||||
|
#define EMC_RFCPB 0x590
|
||||||
|
#define EMC_RAS 0x34
|
||||||
|
#define EMC_RP 0x38
|
||||||
|
#define EMC_R2W 0x3c
|
||||||
|
#define EMC_W2R 0x40
|
||||||
|
#define EMC_R2P 0x44
|
||||||
|
#define EMC_W2P 0x48
|
||||||
|
#define EMC_CCDMW 0x5c0
|
||||||
|
#define EMC_RD_RCD 0x4c
|
||||||
|
#define EMC_WR_RCD 0x50
|
||||||
|
#define EMC_RRD 0x54
|
||||||
|
#define EMC_REXT 0x58
|
||||||
|
#define EMC_WDV 0x5c
|
||||||
|
#define EMC_QUSE 0x60
|
||||||
|
#define EMC_QRST 0x64
|
||||||
|
#define EMC_ISSUE_QRST 0x428
|
||||||
|
#define EMC_QSAFE 0x68
|
||||||
|
#define EMC_RDV 0x6c
|
||||||
|
#define EMC_REFRESH 0x70
|
||||||
|
#define EMC_BURST_REFRESH_NUM 0x74
|
||||||
|
#define EMC_PDEX2WR 0x78
|
||||||
|
#define EMC_PDEX2RD 0x7c
|
||||||
|
#define EMC_PDEX2CKE 0x118
|
||||||
|
#define EMC_PCHG2PDEN 0x80
|
||||||
|
#define EMC_ACT2PDEN 0x84
|
||||||
|
#define EMC_AR2PDEN 0x88
|
||||||
|
#define EMC_RW2PDEN 0x8c
|
||||||
|
#define EMC_CKE2PDEN 0x11c
|
||||||
|
#define EMC_TXSR 0x90
|
||||||
|
#define EMC_TCKE 0x94
|
||||||
|
#define EMC_TFAW 0x98
|
||||||
|
#define EMC_TRPAB 0x9c
|
||||||
|
#define EMC_TCLKSTABLE 0xa0
|
||||||
|
#define EMC_TCLKSTOP 0xa4
|
||||||
|
#define EMC_TREFBW 0xa8
|
||||||
|
#define EMC_TPPD 0xac
|
||||||
|
#define EMC_PDEX2MRR 0xb4
|
||||||
|
#define EMC_ODT_WRITE 0xb0
|
||||||
|
#define EMC_WEXT 0xb8
|
||||||
|
#define EMC_RFC_SLR 0xc0
|
||||||
|
#define EMC_MRS_WAIT_CNT2 0xc4
|
||||||
|
#define EMC_MRS_WAIT_CNT 0xc8
|
||||||
|
#define EMC_MRS 0xcc
|
||||||
|
#define EMC_EMRS 0xd0
|
||||||
|
#define EMC_REF 0xd4
|
||||||
|
#define EMC_PRE 0xd8
|
||||||
|
#define EMC_NOP 0xdc
|
||||||
|
#define EMC_SELF_REF 0xe0
|
||||||
|
#define EMC_DPD 0xe4
|
||||||
|
#define EMC_MRW 0xe8
|
||||||
|
#define EMC_MRR 0xec
|
||||||
|
#define EMC_CMDQ 0xf0
|
||||||
|
#define EMC_MC2EMCQ 0xf4
|
||||||
|
#define EMC_FBIO_SPARE 0x100
|
||||||
|
#define EMC_FBIO_CFG5 0x104
|
||||||
|
#define EMC_CFG_RSV 0x120
|
||||||
|
#define EMC_ACPD_CONTROL 0x124
|
||||||
|
#define EMC_MPC 0x128
|
||||||
|
#define EMC_EMRS2 0x12c
|
||||||
|
#define EMC_EMRS3 0x130
|
||||||
|
#define EMC_MRW2 0x134
|
||||||
|
#define EMC_MRW3 0x138
|
||||||
|
#define EMC_MRW4 0x13c
|
||||||
|
#define EMC_MRW5 0x4a0
|
||||||
|
#define EMC_MRW6 0x4a4
|
||||||
|
#define EMC_MRW7 0x4a8
|
||||||
|
#define EMC_MRW8 0x4ac
|
||||||
|
#define EMC_MRW9 0x4b0
|
||||||
|
#define EMC_MRW10 0x4b4
|
||||||
|
#define EMC_MRW11 0x4b8
|
||||||
|
#define EMC_MRW12 0x4bc
|
||||||
|
#define EMC_MRW13 0x4c0
|
||||||
|
#define EMC_MRW14 0x4c4
|
||||||
|
#define EMC_MRW15 0x4d0
|
||||||
|
#define EMC_CFG_SYNC 0x4d4
|
||||||
|
#define EMC_CLKEN_OVERRIDE 0x140
|
||||||
|
#define EMC_R2R 0x144
|
||||||
|
#define EMC_W2W 0x148
|
||||||
|
#define EMC_EINPUT 0x14c
|
||||||
|
#define EMC_EINPUT_DURATION 0x150
|
||||||
|
#define EMC_PUTERM_EXTRA 0x154
|
||||||
|
#define EMC_TCKESR 0x158
|
||||||
|
#define EMC_TPD 0x15c
|
||||||
|
#define EMC_STAT_CONTROL 0x160
|
||||||
|
#define EMC_STAT_STATUS 0x164
|
||||||
|
#define EMC_STAT_DRAM_CLOCK_LIMIT_LO 0x19c
|
||||||
|
#define EMC_STAT_DRAM_CLOCK_LIMIT_HI 0x1a0
|
||||||
|
#define EMC_STAT_DRAM_CLOCKS_LO 0x1a4
|
||||||
|
#define EMC_STAT_DRAM_CLOCKS_HI 0x1a8
|
||||||
|
#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO 0x1ac
|
||||||
|
#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI 0x1b0
|
||||||
|
#define EMC_STAT_DRAM_DEV0_READ_CNT_LO 0x1b4
|
||||||
|
#define EMC_STAT_DRAM_DEV0_READ_CNT_HI 0x1b8
|
||||||
|
#define EMC_STAT_DRAM_DEV0_READ8_CNT_LO 0x1bc
|
||||||
|
#define EMC_STAT_DRAM_DEV0_READ8_CNT_HI 0x1c0
|
||||||
|
#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO 0x1c4
|
||||||
|
#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI 0x1c8
|
||||||
|
#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_LO 0x1cc
|
||||||
|
#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_HI 0x1d0
|
||||||
|
#define EMC_STAT_DRAM_DEV0_REF_CNT_LO 0x1d4
|
||||||
|
#define EMC_STAT_DRAM_DEV0_REF_CNT_HI 0x1d8
|
||||||
|
#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1dc
|
||||||
|
#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1e0
|
||||||
|
#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1e4
|
||||||
|
#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1e8
|
||||||
|
#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1ec
|
||||||
|
#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1f0
|
||||||
|
#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1f4
|
||||||
|
#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1f8
|
||||||
|
#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x1fc
|
||||||
|
#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x200
|
||||||
|
#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x204
|
||||||
|
#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x208
|
||||||
|
#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x20c
|
||||||
|
#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x210
|
||||||
|
#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x214
|
||||||
|
#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x218
|
||||||
|
#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_LO 0x21c
|
||||||
|
#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_HI 0x220
|
||||||
|
#define EMC_STAT_DRAM_DEV0_DSR 0x224
|
||||||
|
#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO 0x228
|
||||||
|
#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI 0x22c
|
||||||
|
#define EMC_STAT_DRAM_DEV1_READ_CNT_LO 0x230
|
||||||
|
#define EMC_STAT_DRAM_DEV1_READ_CNT_HI 0x234
|
||||||
|
#define EMC_STAT_DRAM_DEV1_READ8_CNT_LO 0x238
|
||||||
|
#define EMC_STAT_DRAM_DEV1_READ8_CNT_HI 0x23c
|
||||||
|
#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO 0x240
|
||||||
|
#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI 0x244
|
||||||
|
#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_LO 0x248
|
||||||
|
#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_HI 0x24c
|
||||||
|
#define EMC_STAT_DRAM_DEV1_REF_CNT_LO 0x250
|
||||||
|
#define EMC_STAT_DRAM_DEV1_REF_CNT_HI 0x254
|
||||||
|
#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x258
|
||||||
|
#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x25c
|
||||||
|
#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x260
|
||||||
|
#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x264
|
||||||
|
#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x268
|
||||||
|
#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x26c
|
||||||
|
#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x270
|
||||||
|
#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x274
|
||||||
|
#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x278
|
||||||
|
#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x27c
|
||||||
|
#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x280
|
||||||
|
#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x284
|
||||||
|
#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x288
|
||||||
|
#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x28c
|
||||||
|
#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x290
|
||||||
|
#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x294
|
||||||
|
#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_LO 0x298
|
||||||
|
#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_HI 0x29c
|
||||||
|
#define EMC_STAT_DRAM_DEV1_DSR 0x2a0
|
||||||
|
#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xc8c
|
||||||
|
#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xc90
|
||||||
|
#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xc94
|
||||||
|
#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xc98
|
||||||
|
#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xc9c
|
||||||
|
#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xca0
|
||||||
|
#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xca4
|
||||||
|
#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xca8
|
||||||
|
#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xcac
|
||||||
|
#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xcb0
|
||||||
|
#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xcb4
|
||||||
|
#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xcb8
|
||||||
|
#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xcbc
|
||||||
|
#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xcc0
|
||||||
|
#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xcc4
|
||||||
|
#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xcc8
|
||||||
|
#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_LO 0xccc
|
||||||
|
#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_HI 0xcd0
|
||||||
|
#define EMC_STAT_DRAM_IO_DSR 0xcd4
|
||||||
|
#define EMC_AUTO_CAL_CONFIG 0x2a4
|
||||||
|
#define EMC_AUTO_CAL_CONFIG2 0x458
|
||||||
|
#define EMC_AUTO_CAL_CONFIG3 0x45c
|
||||||
|
#define EMC_AUTO_CAL_CONFIG4 0x5b0
|
||||||
|
#define EMC_AUTO_CAL_CONFIG5 0x5b4
|
||||||
|
#define EMC_AUTO_CAL_CONFIG6 0x5cc
|
||||||
|
#define EMC_AUTO_CAL_CONFIG7 0x574
|
||||||
|
#define EMC_AUTO_CAL_CONFIG8 0x2dc
|
||||||
|
#define EMC_AUTO_CAL_VREF_SEL_0 0x2f8
|
||||||
|
#define EMC_AUTO_CAL_VREF_SEL_1 0x300
|
||||||
|
#define EMC_AUTO_CAL_INTERVAL 0x2a8
|
||||||
|
#define EMC_AUTO_CAL_STATUS 0x2ac
|
||||||
|
#define EMC_AUTO_CAL_STATUS2 0x3d4
|
||||||
|
#define EMC_AUTO_CAL_CHANNEL 0x464
|
||||||
|
#define EMC_PMACRO_RX_TERM 0xc48
|
||||||
|
#define EMC_PMACRO_DQ_TX_DRV 0xc70
|
||||||
|
#define EMC_PMACRO_CA_TX_DRV 0xc74
|
||||||
|
#define EMC_PMACRO_CMD_TX_DRV 0xc4c
|
||||||
|
#define EMC_PMACRO_AUTOCAL_CFG_0 0x700
|
||||||
|
#define EMC_PMACRO_AUTOCAL_CFG_1 0x704
|
||||||
|
#define EMC_PMACRO_AUTOCAL_CFG_2 0x708
|
||||||
|
#define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xc78
|
||||||
|
#define EMC_PMACRO_ZCTRL 0xc44
|
||||||
|
#define EMC_XM2COMPPADCTRL 0x30c
|
||||||
|
#define EMC_XM2COMPPADCTRL2 0x578
|
||||||
|
#define EMC_XM2COMPPADCTRL3 0x2f4
|
||||||
|
#define EMC_COMP_PAD_SW_CTRL 0x57c
|
||||||
|
#define EMC_REQ_CTRL 0x2b0
|
||||||
|
#define EMC_EMC_STATUS 0x2b4
|
||||||
|
#define EMC_CFG_2 0x2b8
|
||||||
|
#define EMC_CFG_DIG_DLL 0x2bc
|
||||||
|
#define EMC_CFG_DIG_DLL_PERIOD 0x2c0
|
||||||
|
#define EMC_DIG_DLL_STATUS 0x2c4
|
||||||
|
#define EMC_CFG_DIG_DLL_1 0x2c8
|
||||||
|
#define EMC_RDV_MASK 0x2cc
|
||||||
|
#define EMC_WDV_MASK 0x2d0
|
||||||
|
#define EMC_RDV_EARLY_MASK 0x2d4
|
||||||
|
#define EMC_RDV_EARLY 0x2d8
|
||||||
|
#define EMC_WDV_CHK 0x4e0
|
||||||
|
#define EMC_ZCAL_INTERVAL 0x2e0
|
||||||
|
#define EMC_ZCAL_WAIT_CNT 0x2e4
|
||||||
|
#define EMC_ZCAL_MRW_CMD 0x2e8
|
||||||
|
#define EMC_ZQ_CAL 0x2ec
|
||||||
|
#define EMC_SCRATCH0 0x324
|
||||||
|
#define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE 0x3c8
|
||||||
|
#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
|
||||||
|
#define EMC_UNSTALL_RW_AFTER_CLKCHANGE 0x3d0
|
||||||
|
#define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4d8
|
||||||
|
#define EMC_SEL_DPD_CTRL 0x3d8
|
||||||
|
#define EMC_FDPD_CTRL_DQ 0x310
|
||||||
|
#define EMC_FDPD_CTRL_CMD 0x314
|
||||||
|
#define EMC_PRE_REFRESH_REQ_CNT 0x3dc
|
||||||
|
#define EMC_REFCTRL2 0x580
|
||||||
|
#define EMC_FBIO_CFG7 0x584
|
||||||
|
#define EMC_DATA_BRLSHFT_0 0x588
|
||||||
|
#define EMC_DATA_BRLSHFT_1 0x58c
|
||||||
|
#define EMC_DQS_BRLSHFT_0 0x594
|
||||||
|
#define EMC_DQS_BRLSHFT_1 0x598
|
||||||
|
#define EMC_CMD_BRLSHFT_0 0x59c
|
||||||
|
#define EMC_CMD_BRLSHFT_1 0x5a0
|
||||||
|
#define EMC_CMD_BRLSHFT_2 0x5a4
|
||||||
|
#define EMC_CMD_BRLSHFT_3 0x5a8
|
||||||
|
#define EMC_QUSE_BRLSHFT_0 0x5ac
|
||||||
|
#define EMC_QUSE_BRLSHFT_1 0x5b8
|
||||||
|
#define EMC_QUSE_BRLSHFT_2 0x5bc
|
||||||
|
#define EMC_QUSE_BRLSHFT_3 0x5c4
|
||||||
|
#define EMC_FBIO_CFG8 0x5c8
|
||||||
|
#define EMC_CMD_MAPPING_CMD0_0 0x380
|
||||||
|
#define EMC_CMD_MAPPING_CMD0_1 0x384
|
||||||
|
#define EMC_CMD_MAPPING_CMD0_2 0x388
|
||||||
|
#define EMC_CMD_MAPPING_CMD1_0 0x38c
|
||||||
|
#define EMC_CMD_MAPPING_CMD1_1 0x390
|
||||||
|
#define EMC_CMD_MAPPING_CMD1_2 0x394
|
||||||
|
#define EMC_CMD_MAPPING_CMD2_0 0x398
|
||||||
|
#define EMC_CMD_MAPPING_CMD2_1 0x39c
|
||||||
|
#define EMC_CMD_MAPPING_CMD2_2 0x3a0
|
||||||
|
#define EMC_CMD_MAPPING_CMD3_0 0x3a4
|
||||||
|
#define EMC_CMD_MAPPING_CMD3_1 0x3a8
|
||||||
|
#define EMC_CMD_MAPPING_CMD3_2 0x3ac
|
||||||
|
#define EMC_CMD_MAPPING_BYTE 0x3b0
|
||||||
|
#define EMC_DYN_SELF_REF_CONTROL 0x3e0
|
||||||
|
#define EMC_TXSRDLL 0x3e4
|
||||||
|
#define EMC_CCFIFO_ADDR 0x3e8
|
||||||
|
#define EMC_CCFIFO_DATA 0x3ec
|
||||||
|
#define EMC_CCFIFO_STATUS 0x3f0
|
||||||
|
#define EMC_SWIZZLE_RANK0_BYTE0 0x404
|
||||||
|
#define EMC_SWIZZLE_RANK0_BYTE1 0x408
|
||||||
|
#define EMC_SWIZZLE_RANK0_BYTE2 0x40c
|
||||||
|
#define EMC_SWIZZLE_RANK0_BYTE3 0x410
|
||||||
|
#define EMC_SWIZZLE_RANK1_BYTE0 0x418
|
||||||
|
#define EMC_SWIZZLE_RANK1_BYTE1 0x41c
|
||||||
|
#define EMC_SWIZZLE_RANK1_BYTE2 0x420
|
||||||
|
#define EMC_SWIZZLE_RANK1_BYTE3 0x424
|
||||||
|
#define EMC_TR_TIMING_0 0x3b4
|
||||||
|
#define EMC_TR_CTRL_0 0x3b8
|
||||||
|
#define EMC_TR_CTRL_1 0x3bc
|
||||||
|
#define EMC_TR_DVFS 0x460
|
||||||
|
#define EMC_SWITCH_BACK_CTRL 0x3c0
|
||||||
|
#define EMC_TR_RDV 0x3c4
|
||||||
|
#define EMC_TR_QPOP 0x3f4
|
||||||
|
#define EMC_TR_RDV_MASK 0x3f8
|
||||||
|
#define EMC_TR_QSAFE 0x3fc
|
||||||
|
#define EMC_TR_QRST 0x400
|
||||||
|
#define EMC_IBDLY 0x468
|
||||||
|
#define EMC_OBDLY 0x46c
|
||||||
|
#define EMC_TXDSRVTTGEN 0x480
|
||||||
|
#define EMC_WE_DURATION 0x48c
|
||||||
|
#define EMC_WS_DURATION 0x490
|
||||||
|
#define EMC_WEV 0x494
|
||||||
|
#define EMC_WSV 0x498
|
||||||
|
#define EMC_CFG_3 0x49c
|
||||||
|
#define EMC_CFG_PIPE_2 0x554
|
||||||
|
#define EMC_CFG_PIPE_CLK 0x558
|
||||||
|
#define EMC_CFG_PIPE_1 0x55c
|
||||||
|
#define EMC_CFG_PIPE 0x560
|
||||||
|
#define EMC_QPOP 0x564
|
||||||
|
#define EMC_QUSE_WIDTH 0x568
|
||||||
|
#define EMC_PUTERM_WIDTH 0x56c
|
||||||
|
#define EMC_PROTOBIST_CONFIG_ADR_1 0x5d0
|
||||||
|
#define EMC_PROTOBIST_CONFIG_ADR_2 0x5d4
|
||||||
|
#define EMC_PROTOBIST_MISC 0x5d8
|
||||||
|
#define EMC_PROTOBIST_WDATA_LOWER 0x5dc
|
||||||
|
#define EMC_PROTOBIST_WDATA_UPPER 0x5e0
|
||||||
|
#define EMC_PROTOBIST_RDATA 0x5ec
|
||||||
|
#define EMC_DLL_CFG_0 0x5e4
|
||||||
|
#define EMC_DLL_CFG_1 0x5e8
|
||||||
|
#define EMC_TRAINING_CMD 0xe00
|
||||||
|
#define EMC_TRAINING_CTRL 0xe04
|
||||||
|
#define EMC_TRAINING_STATUS 0xe08
|
||||||
|
#define EMC_TRAINING_QUSE_CORS_CTRL 0xe0c
|
||||||
|
#define EMC_TRAINING_QUSE_FINE_CTRL 0xe10
|
||||||
|
#define EMC_TRAINING_QUSE_CTRL_MISC 0xe14
|
||||||
|
#define EMC_TRAINING_WRITE_FINE_CTRL 0xe18
|
||||||
|
#define EMC_TRAINING_WRITE_CTRL_MISC 0xe1c
|
||||||
|
#define EMC_TRAINING_WRITE_VREF_CTRL 0xe20
|
||||||
|
#define EMC_TRAINING_READ_FINE_CTRL 0xe24
|
||||||
|
#define EMC_TRAINING_READ_CTRL_MISC 0xe28
|
||||||
|
#define EMC_TRAINING_READ_VREF_CTRL 0xe2c
|
||||||
|
#define EMC_TRAINING_CA_FINE_CTRL 0xe30
|
||||||
|
#define EMC_TRAINING_CA_CTRL_MISC 0xe34
|
||||||
|
#define EMC_TRAINING_CA_CTRL_MISC1 0xe38
|
||||||
|
#define EMC_TRAINING_CA_VREF_CTRL 0xe3c
|
||||||
|
#define EMC_TRAINING_CA_TADR_CTRL 0xe40
|
||||||
|
#define EMC_TRAINING_SETTLE 0xe44
|
||||||
|
#define EMC_TRAINING_DEBUG_CTRL 0xe48
|
||||||
|
#define EMC_TRAINING_DEBUG_DQ0 0xe4c
|
||||||
|
#define EMC_TRAINING_DEBUG_DQ1 0xe50
|
||||||
|
#define EMC_TRAINING_DEBUG_DQ2 0xe54
|
||||||
|
#define EMC_TRAINING_DEBUG_DQ3 0xe58
|
||||||
|
#define EMC_TRAINING_MPC 0xe5c
|
||||||
|
#define EMC_TRAINING_PATRAM_CTRL 0xe60
|
||||||
|
#define EMC_TRAINING_PATRAM_DQ 0xe64
|
||||||
|
#define EMC_TRAINING_PATRAM_DMI 0xe68
|
||||||
|
#define EMC_TRAINING_VREF_SETTLE 0xe6c
|
||||||
|
#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE0 0xe70
|
||||||
|
#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE1 0xe74
|
||||||
|
#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE2 0xe78
|
||||||
|
#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE3 0xe7c
|
||||||
|
#define EMC_TRAINING_RW_EYE_CENTER_IB_MISC 0xe80
|
||||||
|
#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE0 0xe84
|
||||||
|
#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE1 0xe88
|
||||||
|
#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE2 0xe8c
|
||||||
|
#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE3 0xe90
|
||||||
|
#define EMC_TRAINING_RW_EYE_CENTER_OB_MISC 0xe94
|
||||||
|
#define EMC_TRAINING_RW_OFFSET_IB_BYTE0 0xe98
|
||||||
|
#define EMC_TRAINING_RW_OFFSET_IB_BYTE1 0xe9c
|
||||||
|
#define EMC_TRAINING_RW_OFFSET_IB_BYTE2 0xea0
|
||||||
|
#define EMC_TRAINING_RW_OFFSET_IB_BYTE3 0xea4
|
||||||
|
#define EMC_TRAINING_RW_OFFSET_IB_MISC 0xea8
|
||||||
|
#define EMC_TRAINING_RW_OFFSET_OB_BYTE0 0xeac
|
||||||
|
#define EMC_TRAINING_RW_OFFSET_OB_BYTE1 0xeb0
|
||||||
|
#define EMC_TRAINING_RW_OFFSET_OB_BYTE2 0xeb4
|
||||||
|
#define EMC_TRAINING_RW_OFFSET_OB_BYTE3 0xeb8
|
||||||
|
#define EMC_TRAINING_RW_OFFSET_OB_MISC 0xebc
|
||||||
|
#define EMC_TRAINING_OPT_CA_VREF 0xec0
|
||||||
|
#define EMC_TRAINING_OPT_DQ_OB_VREF 0xec4
|
||||||
|
#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK0 0xec8
|
||||||
|
#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK1 0xecc
|
||||||
|
#define EMC_TRAINING_QUSE_VREF_CTRL 0xed0
|
||||||
|
#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xed4
|
||||||
|
#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xed8
|
||||||
|
#define EMC_TRAINING_DRAMC_TIMING 0xedc
|
||||||
|
#define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600
|
||||||
|
#define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604
|
||||||
|
#define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608
|
||||||
|
#define EMC_PMACRO_QUSE_DDLL_RANK0_3 0x60c
|
||||||
|
#define EMC_PMACRO_QUSE_DDLL_RANK0_4 0x610
|
||||||
|
#define EMC_PMACRO_QUSE_DDLL_RANK0_5 0x614
|
||||||
|
#define EMC_PMACRO_QUSE_DDLL_RANK1_0 0x620
|
||||||
|
#define EMC_PMACRO_QUSE_DDLL_RANK1_1 0x624
|
||||||
|
#define EMC_PMACRO_QUSE_DDLL_RANK1_2 0x628
|
||||||
|
#define EMC_PMACRO_QUSE_DDLL_RANK1_3 0x62c
|
||||||
|
#define EMC_PMACRO_QUSE_DDLL_RANK1_4 0x630
|
||||||
|
#define EMC_PMACRO_QUSE_DDLL_RANK1_5 0x634
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 0x670
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 0x674
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 0x680
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 0x684
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 0x688
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 0x68c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 0x690
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 0x694
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 0x6a0
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 0x6a4
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 0x6a8
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 0x6ac
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 0x6b0
|
||||||
|
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 0x6b4
|
||||||
|
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 0x6c0
|
||||||
|
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 0x6c4
|
||||||
|
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 0x6c8
|
||||||
|
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 0x6cc
|
||||||
|
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4 0x6d0
|
||||||
|
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5 0x6d4
|
||||||
|
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 0x6e0
|
||||||
|
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 0x6e4
|
||||||
|
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 0x6e8
|
||||||
|
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 0x6ec
|
||||||
|
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4 0x6f0
|
||||||
|
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5 0x6f4
|
||||||
|
#define EMC_PMACRO_TX_PWRD_0 0x720
|
||||||
|
#define EMC_PMACRO_TX_PWRD_1 0x724
|
||||||
|
#define EMC_PMACRO_TX_PWRD_2 0x728
|
||||||
|
#define EMC_PMACRO_TX_PWRD_3 0x72c
|
||||||
|
#define EMC_PMACRO_TX_PWRD_4 0x730
|
||||||
|
#define EMC_PMACRO_TX_PWRD_5 0x734
|
||||||
|
#define EMC_PMACRO_TX_SEL_CLK_SRC_0 0x740
|
||||||
|
#define EMC_PMACRO_TX_SEL_CLK_SRC_1 0x744
|
||||||
|
#define EMC_PMACRO_TX_SEL_CLK_SRC_3 0x74c
|
||||||
|
#define EMC_PMACRO_TX_SEL_CLK_SRC_2 0x748
|
||||||
|
#define EMC_PMACRO_TX_SEL_CLK_SRC_4 0x750
|
||||||
|
#define EMC_PMACRO_TX_SEL_CLK_SRC_5 0x754
|
||||||
|
#define EMC_PMACRO_DDLL_BYPASS 0x760
|
||||||
|
#define EMC_PMACRO_DDLL_PWRD_0 0x770
|
||||||
|
#define EMC_PMACRO_DDLL_PWRD_1 0x774
|
||||||
|
#define EMC_PMACRO_DDLL_PWRD_2 0x778
|
||||||
|
#define EMC_PMACRO_CMD_CTRL_0 0x780
|
||||||
|
#define EMC_PMACRO_CMD_CTRL_1 0x784
|
||||||
|
#define EMC_PMACRO_CMD_CTRL_2 0x788
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 0x80c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 0x81c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 0x82c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 0x83c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 0x84c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 0x85c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 0x86c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 0x87c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 0x880
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 0x884
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 0x888
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 0x88c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 0x890
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 0x894
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 0x898
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 0x89c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 0x8a0
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 0x8a4
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 0x8a8
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 0x8ac
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 0x8b0
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 0x8b4
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 0x8b8
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 0x8bc
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 0x90c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 0x91c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 0x92c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 0x93c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 0x94c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 0x95c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 0x96c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 0x97c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 0x980
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 0x984
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 0x988
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 0x98c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 0x990
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 0x994
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 0x998
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 0x99c
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 0x9a0
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 0x9a4
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 0x9a8
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 0x9ac
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 0x9b0
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 0x9b4
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 0x9b8
|
||||||
|
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 0x9bc
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xa00
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xa04
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xa08
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xa10
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xa14
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xa18
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xa20
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xa24
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xa28
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xa30
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xa34
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xa38
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xa40
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xa44
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xa48
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xa50
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xa54
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xa58
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xa60
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xa64
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xa68
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xa70
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xa74
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xa78
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0 0xa80
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1 0xa84
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2 0xa88
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0 0xa90
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1 0xa94
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2 0xa98
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0 0xaa0
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1 0xaa4
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2 0xaa8
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0 0xab0
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1 0xab4
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2 0xab8
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xb00
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xb04
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xb08
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xb10
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xb14
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xb18
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xb20
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xb24
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xb28
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xb30
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xb34
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xb38
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xb40
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xb44
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xb48
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xb50
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xb54
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xb58
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xb60
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xb64
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xb68
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xb70
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xb74
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xb78
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0 0xb80
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1 0xb84
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2 0xb88
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0 0xb90
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1 0xb94
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2 0xb98
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0 0xba0
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1 0xba4
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2 0xba8
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0 0xbb0
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1 0xbb4
|
||||||
|
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2 0xbb8
|
||||||
|
#define EMC_PMACRO_IB_VREF_DQ_0 0xbe0
|
||||||
|
#define EMC_PMACRO_IB_VREF_DQ_1 0xbe4
|
||||||
|
#define EMC_PMACRO_IB_VREF_DQ_2 0xbe8
|
||||||
|
#define EMC_PMACRO_IB_VREF_DQS_0 0xbf0
|
||||||
|
#define EMC_PMACRO_IB_VREF_DQS_1 0xbf4
|
||||||
|
#define EMC_PMACRO_IB_VREF_DQS_2 0xbf8
|
||||||
|
#define EMC_PMACRO_IB_RXRT 0xcf4
|
||||||
|
#define EMC_PMACRO_DDLL_LONG_CMD_0 0xc00
|
||||||
|
#define EMC_PMACRO_DDLL_LONG_CMD_1 0xc04
|
||||||
|
#define EMC_PMACRO_DDLL_LONG_CMD_2 0xc08
|
||||||
|
#define EMC_PMACRO_DDLL_LONG_CMD_3 0xc0c
|
||||||
|
#define EMC_PMACRO_DDLL_LONG_CMD_4 0xc10
|
||||||
|
#define EMC_PMACRO_DDLL_LONG_CMD_5 0xc14
|
||||||
|
#define EMC_PMACRO_DDLL_SHORT_CMD_0 0xc20
|
||||||
|
#define EMC_PMACRO_DDLL_SHORT_CMD_1 0xc24
|
||||||
|
#define EMC_PMACRO_DDLL_SHORT_CMD_2 0xc28
|
||||||
|
#define EMC_PMACRO_CFG_PM_GLOBAL_0 0xc30
|
||||||
|
#define EMC_PMACRO_VTTGEN_CTRL_0 0xc34
|
||||||
|
#define EMC_PMACRO_VTTGEN_CTRL_1 0xc38
|
||||||
|
#define EMC_PMACRO_VTTGEN_CTRL_2 0xcf0
|
||||||
|
#define EMC_PMACRO_BG_BIAS_CTRL_0 0xc3c
|
||||||
|
#define EMC_PMACRO_PAD_CFG_CTRL 0xc40
|
||||||
|
#define EMC_PMACRO_CMD_PAD_RX_CTRL 0xc50
|
||||||
|
#define EMC_PMACRO_DATA_PAD_RX_CTRL 0xc54
|
||||||
|
#define EMC_PMACRO_CMD_RX_TERM_MODE 0xc58
|
||||||
|
#define EMC_PMACRO_DATA_RX_TERM_MODE 0xc5c
|
||||||
|
#define EMC_PMACRO_CMD_PAD_TX_CTRL 0xc60
|
||||||
|
#define EMC_PMACRO_DATA_PAD_TX_CTRL 0xc64
|
||||||
|
#define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68
|
||||||
|
#define EMC_PMACRO_BRICK_MAPPING_0 0xc80
|
||||||
|
#define EMC_PMACRO_BRICK_MAPPING_1 0xc84
|
||||||
|
#define EMC_PMACRO_BRICK_MAPPING_2 0xc88
|
||||||
|
#define EMC_PMACRO_DDLLCAL_CAL 0xce0
|
||||||
|
#define EMC_PMACRO_DDLL_OFFSET 0xce4
|
||||||
|
#define EMC_PMACRO_DDLL_PERIODIC_OFFSET 0xce8
|
||||||
|
#define EMC_PMACRO_BRICK_CTRL_RFU1 0x330
|
||||||
|
#define EMC_PMACRO_BRICK_CTRL_RFU2 0x334
|
||||||
|
#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD 0x318
|
||||||
|
#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31c
|
||||||
|
#define EMC_PMACRO_TRAINING_CTRL_0 0xcf8
|
||||||
|
#define EMC_PMACRO_TRAINING_CTRL_1 0xcfc
|
||||||
|
#define EMC_PMC_SCRATCH1 0x440
|
||||||
|
#define EMC_PMC_SCRATCH2 0x444
|
||||||
|
#define EMC_PMC_SCRATCH3 0x448
|
||||||
|
|
||||||
|
#endif
|
129
source/mem/heap.c
Normal file
129
source/mem/heap.c
Normal file
@ -0,0 +1,129 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (c) 2018 M4xw
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <string.h>
|
||||||
|
#include "heap.h"
|
||||||
|
#include "../../common/common_heap.h"
|
||||||
|
|
||||||
|
static void _heap_create(heap_t *heap, u32 start)
|
||||||
|
{
|
||||||
|
heap->start = start;
|
||||||
|
heap->first = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static u32 _heap_alloc(heap_t *heap, u32 size, u32 alignment)
|
||||||
|
{
|
||||||
|
hnode_t *node, *new;
|
||||||
|
int search = 1;
|
||||||
|
|
||||||
|
size = ALIGN(size, alignment);
|
||||||
|
|
||||||
|
if (!heap->first)
|
||||||
|
{
|
||||||
|
node = (hnode_t *)heap->start;
|
||||||
|
node->used = 1;
|
||||||
|
node->size = size;
|
||||||
|
node->prev = NULL;
|
||||||
|
node->next = NULL;
|
||||||
|
heap->first = node;
|
||||||
|
|
||||||
|
return (u32)node + sizeof(hnode_t);
|
||||||
|
}
|
||||||
|
|
||||||
|
node = heap->first;
|
||||||
|
while (search)
|
||||||
|
{
|
||||||
|
if (!node->used && size + sizeof(hnode_t) < node->size)
|
||||||
|
{
|
||||||
|
new = (hnode_t *)((u32)node + sizeof(hnode_t) + size);
|
||||||
|
|
||||||
|
new->size = node->size - sizeof(hnode_t) - size;
|
||||||
|
node->size = size;
|
||||||
|
node->used = 1;
|
||||||
|
new->used = 0;
|
||||||
|
new->next = node->next;
|
||||||
|
new->prev = node;
|
||||||
|
node->next = new;
|
||||||
|
|
||||||
|
return (u32)node + sizeof(hnode_t);
|
||||||
|
}
|
||||||
|
if (node->next)
|
||||||
|
node = node->next;
|
||||||
|
else
|
||||||
|
search = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
new = (hnode_t *)((u32)node + sizeof(hnode_t) + node->size);
|
||||||
|
new->used = 1;
|
||||||
|
new->size = size;
|
||||||
|
new->prev = node;
|
||||||
|
new->next = NULL;
|
||||||
|
node->next = new;
|
||||||
|
|
||||||
|
return (u32)new + sizeof(hnode_t);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _heap_free(heap_t *heap, u32 addr)
|
||||||
|
{
|
||||||
|
hnode_t *node = (hnode_t *)(addr - sizeof(hnode_t));
|
||||||
|
node->used = 0;
|
||||||
|
node = heap->first;
|
||||||
|
while (node)
|
||||||
|
{
|
||||||
|
if (!node->used)
|
||||||
|
{
|
||||||
|
if (node->prev && !node->prev->used)
|
||||||
|
{
|
||||||
|
node->prev->size += node->size + sizeof(hnode_t);
|
||||||
|
node->prev->next = node->next;
|
||||||
|
if (node->next)
|
||||||
|
node->next->prev = node->prev;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
node = node->next;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
heap_t _heap;
|
||||||
|
|
||||||
|
void heap_init(u32 base)
|
||||||
|
{
|
||||||
|
_heap_create(&_heap, base);
|
||||||
|
}
|
||||||
|
|
||||||
|
void *malloc(u32 size)
|
||||||
|
{
|
||||||
|
return (void *)_heap_alloc(&_heap, size, 0x10);
|
||||||
|
}
|
||||||
|
|
||||||
|
void *memalign(u32 align, u32 size)
|
||||||
|
{
|
||||||
|
return (void *)_heap_alloc(&_heap, size, align);
|
||||||
|
}
|
||||||
|
|
||||||
|
void *calloc(u32 num, u32 size)
|
||||||
|
{
|
||||||
|
void *res = (void *)_heap_alloc(&_heap, num * size, 0x10);
|
||||||
|
memset(res, 0, num * size);
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
void free(void *buf)
|
||||||
|
{
|
||||||
|
if ((u32)buf >= _heap.start)
|
||||||
|
_heap_free(&_heap, (u32)buf);
|
||||||
|
}
|
28
source/mem/heap.h
Normal file
28
source/mem/heap.h
Normal file
@ -0,0 +1,28 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _HEAP_H_
|
||||||
|
#define _HEAP_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
void heap_init(u32 base);
|
||||||
|
void *malloc(u32 size);
|
||||||
|
void *calloc(u32 num, u32 size);
|
||||||
|
void free(void *buf);
|
||||||
|
void *memalign(u32 align, u32 size);
|
||||||
|
|
||||||
|
#endif
|
143
source/mem/mc.c
Normal file
143
source/mem/mc.c
Normal file
@ -0,0 +1,143 @@
|
|||||||
|
#include "../mem/mc.h"
|
||||||
|
#include "../soc/t210.h"
|
||||||
|
#include "../soc/clock.h"
|
||||||
|
#include "../utils/util.h"
|
||||||
|
|
||||||
|
void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock)
|
||||||
|
{
|
||||||
|
MC(MC_SEC_CARVEOUT_BOM) = bom;
|
||||||
|
MC(MC_SEC_CARVEOUT_SIZE_MB) = size1mb;
|
||||||
|
if (lock)
|
||||||
|
MC(MC_SEC_CARVEOUT_REG_CTRL) = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void mc_config_carveout()
|
||||||
|
{
|
||||||
|
*(vu32 *)0x8005FFFC = 0xC0EDBBCC;
|
||||||
|
MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1;
|
||||||
|
MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0;
|
||||||
|
MC(MC_VIDEO_PROTECT_BOM) = 0;
|
||||||
|
MC(MC_VIDEO_PROTECT_SIZE_MB) = 0;
|
||||||
|
MC(MC_VIDEO_PROTECT_REG_CTRL) = 1;
|
||||||
|
|
||||||
|
// Configure TSEC carveout @ 0x90000000, 1MB.
|
||||||
|
//mc_config_tsec_carveout(0x90000000, 1, false);
|
||||||
|
mc_config_tsec_carveout(0, 0, true);
|
||||||
|
|
||||||
|
MC(MC_MTS_CARVEOUT_BOM) = 0;
|
||||||
|
MC(MC_MTS_CARVEOUT_SIZE_MB) = 0;
|
||||||
|
MC(MC_MTS_CARVEOUT_ADR_HI) = 0;
|
||||||
|
MC(MC_MTS_CARVEOUT_REG_CTRL) = 1;
|
||||||
|
|
||||||
|
MC(MC_SECURITY_CARVEOUT1_BOM) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT1_BOM_HI) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT1_CFG0) = 0x4000006;
|
||||||
|
|
||||||
|
MC(MC_SECURITY_CARVEOUT2_BOM) = 0x80020000;
|
||||||
|
MC(MC_SECURITY_CARVEOUT2_BOM_HI) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2;
|
||||||
|
MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = 0x3100000;
|
||||||
|
MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = 0x300;
|
||||||
|
MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT2_CFG0) = 0x440167E;
|
||||||
|
|
||||||
|
MC(MC_SECURITY_CARVEOUT3_BOM) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT3_BOM_HI) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = 0x3000000;
|
||||||
|
MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = 0x300;
|
||||||
|
MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E;
|
||||||
|
|
||||||
|
MC(MC_SECURITY_CARVEOUT4_BOM) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT4_BOM_HI) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F;
|
||||||
|
|
||||||
|
MC(MC_SECURITY_CARVEOUT5_BOM) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT5_BOM_HI) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||||
|
MC(MC_SECURITY_CARVEOUT5_CFG0) = 0x8F;
|
||||||
|
}
|
||||||
|
|
||||||
|
void mc_enable_ahb_redirect()
|
||||||
|
{
|
||||||
|
// Enable ARC_CLK_OVR_ON.
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) = (CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) & 0xFFF7FFFF) | 0x80000;
|
||||||
|
//MC(MC_IRAM_REG_CTRL) &= 0xFFFFFFFE;
|
||||||
|
MC(MC_IRAM_BOM) = 0x40000000;
|
||||||
|
MC(MC_IRAM_TOM) = 0x4003F000;
|
||||||
|
}
|
||||||
|
|
||||||
|
void mc_disable_ahb_redirect()
|
||||||
|
{
|
||||||
|
MC(MC_IRAM_BOM) = 0xFFFFF000;
|
||||||
|
MC(MC_IRAM_TOM) = 0;
|
||||||
|
// Disable IRAM_CFG_WRITE_ACCESS (sticky).
|
||||||
|
//MC(MC_IRAM_REG_CTRL) = MC(MC_IRAM_REG_CTRL) & 0xFFFFFFFE | 1;
|
||||||
|
// Disable ARC_CLK_OVR_ON.
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) &= 0xFFF7FFFF;
|
||||||
|
}
|
||||||
|
|
||||||
|
void mc_enable()
|
||||||
|
{
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF) | 0x40000000;
|
||||||
|
// Enable MIPI CAL clock.
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFDFFFFFF) | 0x2000000;
|
||||||
|
// Enable MC clock.
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFFFFFFFE) | 1;
|
||||||
|
// Enable EMC DLL clock.
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) & 0xFFFFBFFF) | 0x4000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x2000001; //Clear EMC and MC reset.
|
||||||
|
usleep(5);
|
||||||
|
|
||||||
|
//#ifdef CONFIG_ENABLE_AHB_REDIRECT
|
||||||
|
mc_disable_ahb_redirect();
|
||||||
|
//mc_enable_ahb_redirect();
|
||||||
|
//#endif
|
||||||
|
}
|
14
source/mem/mc.h
Normal file
14
source/mem/mc.h
Normal file
@ -0,0 +1,14 @@
|
|||||||
|
#ifndef _MC_H_
|
||||||
|
#define _MC_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
#include "../mem/mc_t210.h"
|
||||||
|
|
||||||
|
void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock);
|
||||||
|
void mc_config_carveout();
|
||||||
|
void mc_config_carveout_finalize();
|
||||||
|
void mc_enable_ahb_redirect();
|
||||||
|
void mc_disable_ahb_redirect();
|
||||||
|
void mc_enable();
|
||||||
|
|
||||||
|
#endif
|
466
source/mem/mc_t210.h
Normal file
466
source/mem/mc_t210.h
Normal file
@ -0,0 +1,466 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2014, NVIDIA Corporation. All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under the terms of the GNU General Public
|
||||||
|
* License version 2, as published by the Free Software Foundation, and
|
||||||
|
* may be copied, distributed, and modified under those terms.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _MC_T210_H_
|
||||||
|
#define _MC_T210_H_
|
||||||
|
|
||||||
|
#define MC_INTSTATUS 0x0
|
||||||
|
#define MC_INTMASK 0x4
|
||||||
|
#define MC_ERR_STATUS 0x8
|
||||||
|
#define MC_ERR_ADR 0xc
|
||||||
|
#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0
|
||||||
|
#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4
|
||||||
|
#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8
|
||||||
|
#define MC_PCFIFO_CLIENT_CONFIG3 0xddc
|
||||||
|
#define MC_PCFIFO_CLIENT_CONFIG4 0xde0
|
||||||
|
#define MC_EMEM_CFG 0x50
|
||||||
|
#define MC_EMEM_ADR_CFG 0x54
|
||||||
|
#define MC_EMEM_ADR_CFG_DEV0 0x58
|
||||||
|
#define MC_EMEM_ADR_CFG_DEV1 0x5c
|
||||||
|
#define MC_EMEM_ADR_CFG_CHANNEL_MASK 0x60
|
||||||
|
#define MC_EMEM_ADR_CFG_BANK_MASK_0 0x64
|
||||||
|
#define MC_EMEM_ADR_CFG_BANK_MASK_1 0x68
|
||||||
|
#define MC_EMEM_ADR_CFG_BANK_MASK_2 0x6c
|
||||||
|
#define MC_SECURITY_CFG0 0x70
|
||||||
|
#define MC_SECURITY_CFG1 0x74
|
||||||
|
#define MC_SECURITY_CFG3 0x9bc
|
||||||
|
#define MC_SECURITY_RSV 0x7c
|
||||||
|
#define MC_EMEM_ARB_CFG 0x90
|
||||||
|
#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
|
||||||
|
#define MC_EMEM_ARB_TIMING_RCD 0x98
|
||||||
|
#define MC_EMEM_ARB_TIMING_RP 0x9c
|
||||||
|
#define MC_EMEM_ARB_TIMING_RC 0xa0
|
||||||
|
#define MC_EMEM_ARB_TIMING_RAS 0xa4
|
||||||
|
#define MC_EMEM_ARB_TIMING_FAW 0xa8
|
||||||
|
#define MC_EMEM_ARB_TIMING_RRD 0xac
|
||||||
|
#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
|
||||||
|
#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
|
||||||
|
#define MC_EMEM_ARB_TIMING_R2R 0xb8
|
||||||
|
#define MC_EMEM_ARB_TIMING_W2W 0xbc
|
||||||
|
#define MC_EMEM_ARB_TIMING_R2W 0xc0
|
||||||
|
#define MC_EMEM_ARB_TIMING_W2R 0xc4
|
||||||
|
#define MC_EMEM_ARB_TIMING_RFCPB 0x6c0
|
||||||
|
#define MC_EMEM_ARB_TIMING_CCDMW 0x6c4
|
||||||
|
#define MC_EMEM_ARB_REFPB_HP_CTRL 0x6f0
|
||||||
|
#define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6f4
|
||||||
|
#define MC_EMEM_ARB_DA_TURNS 0xd0
|
||||||
|
#define MC_EMEM_ARB_DA_COVERS 0xd4
|
||||||
|
#define MC_EMEM_ARB_MISC0 0xd8
|
||||||
|
#define MC_EMEM_ARB_MISC1 0xdc
|
||||||
|
#define MC_EMEM_ARB_MISC2 0xc8
|
||||||
|
#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
|
||||||
|
#define MC_EMEM_ARB_RING3_THROTTLE 0xe4
|
||||||
|
#define MC_EMEM_ARB_NISO_THROTTLE 0x6b0
|
||||||
|
#define MC_EMEM_ARB_OVERRIDE 0xe8
|
||||||
|
#define MC_EMEM_ARB_RSV 0xec
|
||||||
|
#define MC_CLKEN_OVERRIDE 0xf4
|
||||||
|
#define MC_TIMING_CONTROL_DBG 0xf8
|
||||||
|
#define MC_TIMING_CONTROL 0xfc
|
||||||
|
#define MC_STAT_CONTROL 0x100
|
||||||
|
#define MC_STAT_STATUS 0x104
|
||||||
|
#define MC_STAT_EMC_CLOCK_LIMIT 0x108
|
||||||
|
#define MC_STAT_EMC_CLOCK_LIMIT_MSBS 0x10c
|
||||||
|
#define MC_STAT_EMC_CLOCKS 0x110
|
||||||
|
#define MC_STAT_EMC_CLOCKS_MSBS 0x114
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO 0x118
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO 0x158
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI 0x11c
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI 0x15c
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER 0xa20
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER 0xa24
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_LO 0x198
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_LO 0x1a8
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_HI 0x19c
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_HI 0x1ac
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_UPPER 0xa28
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_UPPER 0xa2c
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_ASID 0x1a0
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_ASID 0x1b0
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_SLACK_LIMIT 0x120
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_SLACK_LIMIT 0x160
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_0 0x128
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_0 0x168
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_1 0x12c
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_1 0x16c
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_2 0x130
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_2 0x170
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_3 0x134
|
||||||
|
#define MC_STAT_EMC_FILTER_SET0_CLIENT_4 0xb88
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_3 0x174
|
||||||
|
#define MC_STAT_EMC_FILTER_SET1_CLIENT_4 0xb8c
|
||||||
|
#define MC_STAT_EMC_SET0_COUNT 0x138
|
||||||
|
#define MC_STAT_EMC_SET0_COUNT_MSBS 0x13c
|
||||||
|
#define MC_STAT_EMC_SET1_COUNT 0x178
|
||||||
|
#define MC_STAT_EMC_SET1_COUNT_MSBS 0x17c
|
||||||
|
#define MC_STAT_EMC_SET0_SLACK_ACCUM 0x140
|
||||||
|
#define MC_STAT_EMC_SET0_SLACK_ACCUM_MSBS 0x144
|
||||||
|
#define MC_STAT_EMC_SET1_SLACK_ACCUM 0x180
|
||||||
|
#define MC_STAT_EMC_SET1_SLACK_ACCUM_MSBS 0x184
|
||||||
|
#define MC_STAT_EMC_SET0_HISTO_COUNT 0x148
|
||||||
|
#define MC_STAT_EMC_SET0_HISTO_COUNT_MSBS 0x14c
|
||||||
|
#define MC_STAT_EMC_SET1_HISTO_COUNT 0x188
|
||||||
|
#define MC_STAT_EMC_SET1_HISTO_COUNT_MSBS 0x18c
|
||||||
|
#define MC_STAT_EMC_SET0_MINIMUM_SLACK_OBSERVED 0x150
|
||||||
|
#define MC_STAT_EMC_SET1_MINIMUM_SLACK_OBSERVED 0x190
|
||||||
|
#define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT 0x1b8
|
||||||
|
#define MC_STAT_EMC_SET0_IDLE_CYCL_COUNT_MSBS 0x1bc
|
||||||
|
#define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT 0x1c8
|
||||||
|
#define MC_STAT_EMC_SET1_IDLE_CYCL_COUNT_MSBS 0x1cc
|
||||||
|
#define MC_STAT_EMC_SET0_IDLE_CYCLE_PARTITION_SELECT 0x1c0
|
||||||
|
#define MC_STAT_EMC_SET1_IDLE_CYCLE_PARTITION_SELECT 0x1d0
|
||||||
|
#define MC_CLIENT_HOTRESET_CTRL 0x200
|
||||||
|
#define MC_CLIENT_HOTRESET_CTRL_1 0x970
|
||||||
|
#define MC_CLIENT_HOTRESET_STATUS 0x204
|
||||||
|
#define MC_CLIENT_HOTRESET_STATUS_1 0x974
|
||||||
|
#define MC_EMEM_ARB_ISOCHRONOUS_0 0x208
|
||||||
|
#define MC_EMEM_ARB_ISOCHRONOUS_1 0x20c
|
||||||
|
#define MC_EMEM_ARB_ISOCHRONOUS_2 0x210
|
||||||
|
#define MC_EMEM_ARB_ISOCHRONOUS_3 0x214
|
||||||
|
#define MC_EMEM_ARB_ISOCHRONOUS_4 0xb94
|
||||||
|
#define MC_EMEM_ARB_HYSTERESIS_0 0x218
|
||||||
|
#define MC_EMEM_ARB_HYSTERESIS_1 0x21c
|
||||||
|
#define MC_EMEM_ARB_HYSTERESIS_2 0x220
|
||||||
|
#define MC_EMEM_ARB_HYSTERESIS_3 0x224
|
||||||
|
#define MC_EMEM_ARB_HYSTERESIS_4 0xb84
|
||||||
|
#define MC_EMEM_ARB_DHYSTERESIS_0 0xbb0
|
||||||
|
#define MC_EMEM_ARB_DHYSTERESIS_1 0xbb4
|
||||||
|
#define MC_EMEM_ARB_DHYSTERESIS_2 0xbb8
|
||||||
|
#define MC_EMEM_ARB_DHYSTERESIS_3 0xbbc
|
||||||
|
#define MC_EMEM_ARB_DHYSTERESIS_4 0xbc0
|
||||||
|
#define MC_EMEM_ARB_DHYST_CTRL 0xbcc
|
||||||
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xbd0
|
||||||
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xbd4
|
||||||
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xbd8
|
||||||
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xbdc
|
||||||
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xbe0
|
||||||
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xbe4
|
||||||
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xbe8
|
||||||
|
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xbec
|
||||||
|
#define MC_RESERVED_RSV 0x3fc
|
||||||
|
#define MC_DISB_EXTRA_SNAP_LEVELS 0x408
|
||||||
|
#define MC_APB_EXTRA_SNAP_LEVELS 0x2a4
|
||||||
|
#define MC_AHB_EXTRA_SNAP_LEVELS 0x2a0
|
||||||
|
#define MC_USBD_EXTRA_SNAP_LEVELS 0xa18
|
||||||
|
#define MC_ISP_EXTRA_SNAP_LEVELS 0xa08
|
||||||
|
#define MC_AUD_EXTRA_SNAP_LEVELS 0xa10
|
||||||
|
#define MC_MSE_EXTRA_SNAP_LEVELS 0x40c
|
||||||
|
#define MC_GK2_EXTRA_SNAP_LEVELS 0xa40
|
||||||
|
#define MC_A9AVPPC_EXTRA_SNAP_LEVELS 0x414
|
||||||
|
#define MC_FTOP_EXTRA_SNAP_LEVELS 0x2bc
|
||||||
|
#define MC_JPG_EXTRA_SNAP_LEVELS 0xa3c
|
||||||
|
#define MC_HOST_EXTRA_SNAP_LEVELS 0xa14
|
||||||
|
#define MC_SAX_EXTRA_SNAP_LEVELS 0x2c0
|
||||||
|
#define MC_DIS_EXTRA_SNAP_LEVELS 0x2ac
|
||||||
|
#define MC_VICPC_EXTRA_SNAP_LEVELS 0xa1c
|
||||||
|
#define MC_HDAPC_EXTRA_SNAP_LEVELS 0xa48
|
||||||
|
#define MC_AVP_EXTRA_SNAP_LEVELS 0x2a8
|
||||||
|
#define MC_USBX_EXTRA_SNAP_LEVELS 0x404
|
||||||
|
#define MC_PCX_EXTRA_SNAP_LEVELS 0x2b8
|
||||||
|
#define MC_SD_EXTRA_SNAP_LEVELS 0xa04
|
||||||
|
#define MC_DFD_EXTRA_SNAP_LEVELS 0xa4c
|
||||||
|
#define MC_VE_EXTRA_SNAP_LEVELS 0x2d8
|
||||||
|
#define MC_GK_EXTRA_SNAP_LEVELS 0xa00
|
||||||
|
#define MC_VE2_EXTRA_SNAP_LEVELS 0x410
|
||||||
|
#define MC_SDM_EXTRA_SNAP_LEVELS 0xa44
|
||||||
|
#define MC_VIDEO_PROTECT_BOM 0x648
|
||||||
|
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
|
||||||
|
#define MC_VIDEO_PROTECT_BOM_ADR_HI 0x978
|
||||||
|
#define MC_VIDEO_PROTECT_REG_CTRL 0x650
|
||||||
|
#define MC_ERR_VPR_STATUS 0x654
|
||||||
|
#define MC_ERR_VPR_ADR 0x658
|
||||||
|
#define MC_VIDEO_PROTECT_VPR_OVERRIDE 0x418
|
||||||
|
#define MC_VIDEO_PROTECT_VPR_OVERRIDE1 0x590
|
||||||
|
#define MC_IRAM_BOM 0x65c
|
||||||
|
#define MC_IRAM_TOM 0x660
|
||||||
|
#define MC_IRAM_ADR_HI 0x980
|
||||||
|
#define MC_IRAM_REG_CTRL 0x964
|
||||||
|
#define MC_EMEM_CFG_ACCESS_CTRL 0x664
|
||||||
|
#define MC_TZ_SECURITY_CTRL 0x668
|
||||||
|
#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3 0x66c
|
||||||
|
#define MC_EMEM_ARB_OUTSTANDING_REQ_NISO 0x6b4
|
||||||
|
#define MC_EMEM_ARB_RING0_THROTTLE_MASK 0x6bc
|
||||||
|
#define MC_EMEM_ARB_NISO_THROTTLE_MASK 0x6b8
|
||||||
|
#define MC_EMEM_ARB_NISO_THROTTLE_MASK_1 0xb80
|
||||||
|
#define MC_SEC_CARVEOUT_BOM 0x670
|
||||||
|
#define MC_SEC_CARVEOUT_SIZE_MB 0x674
|
||||||
|
#define MC_SEC_CARVEOUT_ADR_HI 0x9d4
|
||||||
|
#define MC_SEC_CARVEOUT_REG_CTRL 0x678
|
||||||
|
#define MC_ERR_SEC_STATUS 0x67c
|
||||||
|
#define MC_ERR_SEC_ADR 0x680
|
||||||
|
#define MC_PC_IDLE_CLOCK_GATE_CONFIG 0x684
|
||||||
|
#define MC_STUTTER_CONTROL 0x688
|
||||||
|
#define MC_RESERVED_RSV_1 0x958
|
||||||
|
#define MC_DVFS_PIPE_SELECT 0x95c
|
||||||
|
#define MC_AHB_PTSA_MIN 0x4e0
|
||||||
|
#define MC_AUD_PTSA_MIN 0x54c
|
||||||
|
#define MC_MLL_MPCORER_PTSA_RATE 0x44c
|
||||||
|
#define MC_RING2_PTSA_RATE 0x440
|
||||||
|
#define MC_USBD_PTSA_RATE 0x530
|
||||||
|
#define MC_USBX_PTSA_MIN 0x528
|
||||||
|
#define MC_USBD_PTSA_MIN 0x534
|
||||||
|
#define MC_APB_PTSA_MAX 0x4f0
|
||||||
|
#define MC_JPG_PTSA_RATE 0x584
|
||||||
|
#define MC_DIS_PTSA_MIN 0x420
|
||||||
|
#define MC_AVP_PTSA_MAX 0x4fc
|
||||||
|
#define MC_AVP_PTSA_RATE 0x4f4
|
||||||
|
#define MC_RING1_PTSA_MIN 0x480
|
||||||
|
#define MC_DIS_PTSA_MAX 0x424
|
||||||
|
#define MC_SD_PTSA_MAX 0x4d8
|
||||||
|
#define MC_MSE_PTSA_RATE 0x4c4
|
||||||
|
#define MC_VICPC_PTSA_MIN 0x558
|
||||||
|
#define MC_PCX_PTSA_MAX 0x4b4
|
||||||
|
#define MC_ISP_PTSA_RATE 0x4a0
|
||||||
|
#define MC_A9AVPPC_PTSA_MIN 0x48c
|
||||||
|
#define MC_RING2_PTSA_MAX 0x448
|
||||||
|
#define MC_AUD_PTSA_RATE 0x548
|
||||||
|
#define MC_HOST_PTSA_MIN 0x51c
|
||||||
|
#define MC_MLL_MPCORER_PTSA_MAX 0x454
|
||||||
|
#define MC_SD_PTSA_MIN 0x4d4
|
||||||
|
#define MC_RING1_PTSA_RATE 0x47c
|
||||||
|
#define MC_JPG_PTSA_MIN 0x588
|
||||||
|
#define MC_HDAPC_PTSA_MIN 0x62c
|
||||||
|
#define MC_AVP_PTSA_MIN 0x4f8
|
||||||
|
#define MC_JPG_PTSA_MAX 0x58c
|
||||||
|
#define MC_VE_PTSA_MAX 0x43c
|
||||||
|
#define MC_DFD_PTSA_MAX 0x63c
|
||||||
|
#define MC_VICPC_PTSA_RATE 0x554
|
||||||
|
#define MC_GK_PTSA_MAX 0x544
|
||||||
|
#define MC_VICPC_PTSA_MAX 0x55c
|
||||||
|
#define MC_SDM_PTSA_MAX 0x624
|
||||||
|
#define MC_SAX_PTSA_RATE 0x4b8
|
||||||
|
#define MC_PCX_PTSA_MIN 0x4b0
|
||||||
|
#define MC_APB_PTSA_MIN 0x4ec
|
||||||
|
#define MC_GK2_PTSA_MIN 0x614
|
||||||
|
#define MC_PCX_PTSA_RATE 0x4ac
|
||||||
|
#define MC_RING1_PTSA_MAX 0x484
|
||||||
|
#define MC_HDAPC_PTSA_RATE 0x628
|
||||||
|
#define MC_MLL_MPCORER_PTSA_MIN 0x450
|
||||||
|
#define MC_GK2_PTSA_MAX 0x618
|
||||||
|
#define MC_AUD_PTSA_MAX 0x550
|
||||||
|
#define MC_GK2_PTSA_RATE 0x610
|
||||||
|
#define MC_ISP_PTSA_MAX 0x4a8
|
||||||
|
#define MC_DISB_PTSA_RATE 0x428
|
||||||
|
#define MC_VE2_PTSA_MAX 0x49c
|
||||||
|
#define MC_DFD_PTSA_MIN 0x638
|
||||||
|
#define MC_FTOP_PTSA_RATE 0x50c
|
||||||
|
#define MC_A9AVPPC_PTSA_RATE 0x488
|
||||||
|
#define MC_VE2_PTSA_MIN 0x498
|
||||||
|
#define MC_USBX_PTSA_MAX 0x52c
|
||||||
|
#define MC_DIS_PTSA_RATE 0x41c
|
||||||
|
#define MC_USBD_PTSA_MAX 0x538
|
||||||
|
#define MC_A9AVPPC_PTSA_MAX 0x490
|
||||||
|
#define MC_USBX_PTSA_RATE 0x524
|
||||||
|
#define MC_FTOP_PTSA_MAX 0x514
|
||||||
|
#define MC_HDAPC_PTSA_MAX 0x630
|
||||||
|
#define MC_SD_PTSA_RATE 0x4d0
|
||||||
|
#define MC_DFD_PTSA_RATE 0x634
|
||||||
|
#define MC_FTOP_PTSA_MIN 0x510
|
||||||
|
#define MC_SDM_PTSA_RATE 0x61c
|
||||||
|
#define MC_AHB_PTSA_RATE 0x4dc
|
||||||
|
#define MC_SMMU_SMMU_PTSA_MAX 0x460
|
||||||
|
#define MC_RING2_PTSA_MIN 0x444
|
||||||
|
#define MC_SDM_PTSA_MIN 0x620
|
||||||
|
#define MC_APB_PTSA_RATE 0x4e8
|
||||||
|
#define MC_MSE_PTSA_MIN 0x4c8
|
||||||
|
#define MC_HOST_PTSA_RATE 0x518
|
||||||
|
#define MC_VE_PTSA_RATE 0x434
|
||||||
|
#define MC_AHB_PTSA_MAX 0x4e4
|
||||||
|
#define MC_SAX_PTSA_MIN 0x4bc
|
||||||
|
#define MC_SMMU_SMMU_PTSA_MIN 0x45c
|
||||||
|
#define MC_ISP_PTSA_MIN 0x4a4
|
||||||
|
#define MC_HOST_PTSA_MAX 0x520
|
||||||
|
#define MC_SAX_PTSA_MAX 0x4c0
|
||||||
|
#define MC_VE_PTSA_MIN 0x438
|
||||||
|
#define MC_GK_PTSA_MIN 0x540
|
||||||
|
#define MC_MSE_PTSA_MAX 0x4cc
|
||||||
|
#define MC_DISB_PTSA_MAX 0x430
|
||||||
|
#define MC_DISB_PTSA_MIN 0x42c
|
||||||
|
#define MC_SMMU_SMMU_PTSA_RATE 0x458
|
||||||
|
#define MC_VE2_PTSA_RATE 0x494
|
||||||
|
#define MC_GK_PTSA_RATE 0x53c
|
||||||
|
#define MC_PTSA_GRANT_DECREMENT 0x960
|
||||||
|
#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4
|
||||||
|
#define MC_LATENCY_ALLOWANCE_AXIAP_0 0x3a0
|
||||||
|
#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380
|
||||||
|
#define MC_LATENCY_ALLOWANCE_ISP2B_0 0x384
|
||||||
|
#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3bc
|
||||||
|
#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b8
|
||||||
|
#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
|
||||||
|
#define MC_LATENCY_ALLOWANCE_SE_0 0x3e0
|
||||||
|
#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
|
||||||
|
#define MC_LATENCY_ALLOWANCE_DC_0 0x2e8
|
||||||
|
#define MC_LATENCY_ALLOWANCE_VIC_0 0x394
|
||||||
|
#define MC_LATENCY_ALLOWANCE_DCB_1 0x2f8
|
||||||
|
#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3d8
|
||||||
|
#define MC_LATENCY_ALLOWANCE_DCB_2 0x2fc
|
||||||
|
#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390
|
||||||
|
#define MC_LATENCY_ALLOWANCE_DC_2 0x2f0
|
||||||
|
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB 0x694
|
||||||
|
#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
|
||||||
|
#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c
|
||||||
|
#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
|
||||||
|
#define MC_LATENCY_ALLOWANCE_TSECB_0 0x3f0
|
||||||
|
#define MC_LATENCY_ALLOWANCE_AFI_0 0x2e0
|
||||||
|
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B 0x698
|
||||||
|
#define MC_LATENCY_ALLOWANCE_DC_1 0x2ec
|
||||||
|
#define MC_LATENCY_ALLOWANCE_APE_0 0x3dc
|
||||||
|
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C 0x6a0
|
||||||
|
#define MC_LATENCY_ALLOWANCE_A9AVP_0 0x3a4
|
||||||
|
#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3e8
|
||||||
|
#define MC_LATENCY_ALLOWANCE_DCB_0 0x2f4
|
||||||
|
#define MC_LATENCY_ALLOWANCE_HC_1 0x314
|
||||||
|
#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c0
|
||||||
|
#define MC_LATENCY_ALLOWANCE_NVJPG_0 0x3e4
|
||||||
|
#define MC_LATENCY_ALLOWANCE_PTC_0 0x34c
|
||||||
|
#define MC_LATENCY_ALLOWANCE_ETR_0 0x3ec
|
||||||
|
#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
|
||||||
|
#define MC_LATENCY_ALLOWANCE_VI2_0 0x398
|
||||||
|
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB 0x69c
|
||||||
|
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB 0x6a4
|
||||||
|
#define MC_LATENCY_ALLOWANCE_SATA_0 0x350
|
||||||
|
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A 0x690
|
||||||
|
#define MC_LATENCY_ALLOWANCE_HC_0 0x310
|
||||||
|
#define MC_LATENCY_ALLOWANCE_DC_3 0x3c8
|
||||||
|
#define MC_LATENCY_ALLOWANCE_GPU_0 0x3ac
|
||||||
|
#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c4
|
||||||
|
#define MC_LATENCY_ALLOWANCE_ISP2B_1 0x388
|
||||||
|
#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
|
||||||
|
#define MC_LATENCY_ALLOWANCE_HDA_0 0x318
|
||||||
|
#define MC_MIN_LENGTH_APE_0 0xb34
|
||||||
|
#define MC_MIN_LENGTH_DCB_2 0x8a8
|
||||||
|
#define MC_MIN_LENGTH_A9AVP_0 0x950
|
||||||
|
#define MC_MIN_LENGTH_TSEC_0 0x93c
|
||||||
|
#define MC_MIN_LENGTH_DC_1 0x898
|
||||||
|
#define MC_MIN_LENGTH_AXIAP_0 0x94c
|
||||||
|
#define MC_MIN_LENGTH_ISP2B_0 0x930
|
||||||
|
#define MC_MIN_LENGTH_VI2_0 0x944
|
||||||
|
#define MC_MIN_LENGTH_DCB_0 0x8a0
|
||||||
|
#define MC_MIN_LENGTH_DCB_1 0x8a4
|
||||||
|
#define MC_MIN_LENGTH_PPCS_1 0x8f4
|
||||||
|
#define MC_MIN_LENGTH_NVJPG_0 0xb3c
|
||||||
|
#define MC_MIN_LENGTH_HDA_0 0x8c4
|
||||||
|
#define MC_MIN_LENGTH_NVENC_0 0x8d4
|
||||||
|
#define MC_MIN_LENGTH_SDMMC_0 0xb18
|
||||||
|
#define MC_MIN_LENGTH_ISP2B_1 0x934
|
||||||
|
#define MC_MIN_LENGTH_HC_1 0x8c0
|
||||||
|
#define MC_MIN_LENGTH_DC_3 0xb20
|
||||||
|
#define MC_MIN_LENGTH_AVPC_0 0x890
|
||||||
|
#define MC_MIN_LENGTH_VIC_0 0x940
|
||||||
|
#define MC_MIN_LENGTH_ISP2_0 0x91c
|
||||||
|
#define MC_MIN_LENGTH_HC_0 0x8bc
|
||||||
|
#define MC_MIN_LENGTH_SE_0 0xb38
|
||||||
|
#define MC_MIN_LENGTH_NVDEC_0 0xb30
|
||||||
|
#define MC_MIN_LENGTH_SATA_0 0x8fc
|
||||||
|
#define MC_MIN_LENGTH_DC_0 0x894
|
||||||
|
#define MC_MIN_LENGTH_XUSB_1 0x92c
|
||||||
|
#define MC_MIN_LENGTH_DC_2 0x89c
|
||||||
|
#define MC_MIN_LENGTH_SDMMCAA_0 0xb14
|
||||||
|
#define MC_MIN_LENGTH_GPU_0 0xb04
|
||||||
|
#define MC_MIN_LENGTH_ETR_0 0xb44
|
||||||
|
#define MC_MIN_LENGTH_AFI_0 0x88c
|
||||||
|
#define MC_MIN_LENGTH_PPCS_0 0x8f0
|
||||||
|
#define MC_MIN_LENGTH_ISP2_1 0x920
|
||||||
|
#define MC_MIN_LENGTH_XUSB_0 0x928
|
||||||
|
#define MC_MIN_LENGTH_MPCORE_0 0x8cc
|
||||||
|
#define MC_MIN_LENGTH_TSECB_0 0xb48
|
||||||
|
#define MC_MIN_LENGTH_SDMMCA_0 0xb10
|
||||||
|
#define MC_MIN_LENGTH_GPU2_0 0xb40
|
||||||
|
#define MC_MIN_LENGTH_SDMMCAB_0 0xb1c
|
||||||
|
#define MC_MIN_LENGTH_PTC_0 0x8f8
|
||||||
|
#define MC_EMEM_ARB_OVERRIDE_1 0x968
|
||||||
|
#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0 0x984
|
||||||
|
#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1 0x988
|
||||||
|
#define MC_EMEM_ARB_STATS_0 0x990
|
||||||
|
#define MC_EMEM_ARB_STATS_1 0x994
|
||||||
|
#define MC_MTS_CARVEOUT_BOM 0x9a0
|
||||||
|
#define MC_MTS_CARVEOUT_SIZE_MB 0x9a4
|
||||||
|
#define MC_MTS_CARVEOUT_ADR_HI 0x9a8
|
||||||
|
#define MC_MTS_CARVEOUT_REG_CTRL 0x9ac
|
||||||
|
#define MC_ERR_MTS_STATUS 0x9b0
|
||||||
|
#define MC_ERR_MTS_ADR 0x9b4
|
||||||
|
#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00
|
||||||
|
#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2 0xd74
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CFG0 0xcf8
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2 0xd10
|
||||||
|
#define MC_SECURITY_CARVEOUT4_SIZE_128KB 0xd04
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4 0xc28
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1 0xc30
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4 0xc8c
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0 0xd1c
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1 0xd70
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0 0xc2c
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4 0xd7c
|
||||||
|
#define MC_SECURITY_CARVEOUT3_SIZE_128KB 0xcb4
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CFG0 0xc58
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CFG0 0xc08
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2 0xc84
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0 0xc68
|
||||||
|
#define MC_SECURITY_CARVEOUT3_BOM 0xcac
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2 0xc70
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3 0xd78
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0 0xc7c
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4 0xd18
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1 0xcbc
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3 0xc38
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2 0xc34
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2 0xcc0
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2 0xd60
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CFG0 0xca8
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0 0xcb8
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3 0xc88
|
||||||
|
#define MC_SECURITY_CARVEOUT2_SIZE_128KB 0xc64
|
||||||
|
#define MC_SECURITY_CARVEOUT5_BOM_HI 0xd50
|
||||||
|
#define MC_SECURITY_CARVEOUT1_SIZE_128KB 0xc14
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3 0xd14
|
||||||
|
#define MC_SECURITY_CARVEOUT1_BOM 0xc0c
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4 0xd2c
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4 0xd68
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4 0xcc8
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0 0xd58
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2 0xd24
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3 0xcc4
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4 0xc78
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1 0xc1c
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0 0xc18
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3 0xd28
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1 0xd5c
|
||||||
|
#define MC_SECURITY_CARVEOUT3_BOM_HI 0xcb0
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3 0xcd8
|
||||||
|
#define MC_SECURITY_CARVEOUT2_BOM_HI 0xc60
|
||||||
|
#define MC_SECURITY_CARVEOUT4_BOM_HI 0xd00
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3 0xd64
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4 0xcdc
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1 0xc80
|
||||||
|
#define MC_SECURITY_CARVEOUT5_SIZE_128KB 0xd54
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1 0xd20
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2 0xcd4
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1 0xd0c
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3 0xc74
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0 0xccc
|
||||||
|
#define MC_SECURITY_CARVEOUT4_BOM 0xcfc
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CFG0 0xd48
|
||||||
|
#define MC_SECURITY_CARVEOUT2_BOM 0xc5c
|
||||||
|
#define MC_SECURITY_CARVEOUT5_BOM 0xd4c
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3 0xc24
|
||||||
|
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0 0xd6c
|
||||||
|
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1 0xcd0
|
||||||
|
#define MC_SECURITY_CARVEOUT1_BOM_HI 0xc10
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2 0xc20
|
||||||
|
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4 0xc3c
|
||||||
|
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1 0xc6c
|
||||||
|
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08
|
||||||
|
#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0
|
||||||
|
#define MC_DA_CONFIG0 0x9dc
|
||||||
|
|
||||||
|
#endif
|
555
source/mem/sdram.c
Normal file
555
source/mem/sdram.c
Normal file
@ -0,0 +1,555 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (c) 2018 balika011
|
||||||
|
* Copyright (c) 2019 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "../soc/i2c.h"
|
||||||
|
#include "../soc/t210.h"
|
||||||
|
#include "mc.h"
|
||||||
|
#include "emc.h"
|
||||||
|
#include "sdram_param_t210.h"
|
||||||
|
#include "../soc/pmc.h"
|
||||||
|
#include "../utils/util.h"
|
||||||
|
#include "../soc/fuse.h"
|
||||||
|
#include "../power/max77620.h"
|
||||||
|
#include "../power/max7762x.h"
|
||||||
|
#include "../soc/clock.h"
|
||||||
|
|
||||||
|
#define CONFIG_SDRAM_COMPRESS_CFG
|
||||||
|
|
||||||
|
#ifdef CONFIG_SDRAM_COMPRESS_CFG
|
||||||
|
#include "../libs/compr/lz.h"
|
||||||
|
#include "sdram_config_lz.inl"
|
||||||
|
#else
|
||||||
|
#include "sdram_config.inl"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static u32 _get_sdram_id()
|
||||||
|
{
|
||||||
|
return (fuse_read_odm(4) & 0x38) >> 3;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _sdram_config(const sdram_params_t *params)
|
||||||
|
{
|
||||||
|
PMC(APBDEV_PMC_IO_DPD3_REQ) = (((4 * params->emc_pmc_scratch1 >> 2) + 0x80000000) ^ 0xFFFF) & 0xC000FFFF;
|
||||||
|
usleep(params->pmc_io_dpd3_req_wait);
|
||||||
|
|
||||||
|
u32 req = (4 * params->emc_pmc_scratch2 >> 2) + 0x80000000;
|
||||||
|
PMC(APBDEV_PMC_IO_DPD4_REQ) = (req >> 16 << 16) ^ 0x3FFF0000;
|
||||||
|
usleep(params->pmc_io_dpd4_req_wait);
|
||||||
|
PMC(APBDEV_PMC_IO_DPD4_REQ) = (req ^ 0xFFFF) & 0xC000FFFF;
|
||||||
|
usleep(params->pmc_io_dpd4_req_wait);
|
||||||
|
PMC(APBDEV_PMC_WEAK_BIAS) = 0;
|
||||||
|
usleep(1);
|
||||||
|
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_PLLM_MISC1) = params->pllm_setup_control;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_PLLM_MISC2) = 0;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = (params->pllm_feedback_divider << 8) | params->pllm_input_divider | 0x40000000 | ((params->pllm_post_divider & 0xFFFF) << 20);
|
||||||
|
|
||||||
|
u32 wait_end = get_tmr_us() + 300;
|
||||||
|
while (!(CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) & 0x8000000))
|
||||||
|
{
|
||||||
|
if (get_tmr_us() >= wait_end)
|
||||||
|
goto break_nosleep;
|
||||||
|
}
|
||||||
|
usleep(10);
|
||||||
|
break_nosleep:
|
||||||
|
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = ((params->mc_emem_arb_misc0 >> 11) & 0x10000) | (params->emc_clock_source & 0xFFFEFFFF);
|
||||||
|
if (params->emc_clock_source_dll)
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL) = params->emc_clock_source_dll;
|
||||||
|
if (params->clear_clock2_mc1)
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_CLR) = 0x40000000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = 0x2000001;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = 0x4000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x2000001;
|
||||||
|
EMC(EMC_PMACRO_VTTGEN_CTRL_0) = params->emc_pmacro_vttgen_ctrl0;
|
||||||
|
EMC(EMC_PMACRO_VTTGEN_CTRL_1) = params->emc_pmacro_vttgen_ctrl1;
|
||||||
|
EMC(EMC_PMACRO_VTTGEN_CTRL_2) = params->emc_pmacro_vttgen_ctrl2;
|
||||||
|
EMC(EMC_TIMING_CONTROL) = 1;
|
||||||
|
usleep(1);
|
||||||
|
EMC(EMC_DBG) = (params->emc_dbg_write_mux << 1) | params->emc_dbg;
|
||||||
|
if (params->emc_bct_spare2)
|
||||||
|
*(vu32 *)params->emc_bct_spare2 = params->emc_bct_spare3;
|
||||||
|
EMC(EMC_FBIO_CFG7) = params->emc_fbio_cfg7;
|
||||||
|
EMC(EMC_CMD_MAPPING_CMD0_0) = params->emc_cmd_mapping_cmd0_0;
|
||||||
|
EMC(EMC_CMD_MAPPING_CMD0_1) = params->emc_cmd_mapping_cmd0_1;
|
||||||
|
EMC(EMC_CMD_MAPPING_CMD0_2) = params->emc_cmd_mapping_cmd0_2;
|
||||||
|
EMC(EMC_CMD_MAPPING_CMD1_0) = params->emc_cmd_mapping_cmd1_0;
|
||||||
|
EMC(EMC_CMD_MAPPING_CMD1_1) = params->emc_cmd_mapping_cmd1_1;
|
||||||
|
EMC(EMC_CMD_MAPPING_CMD1_2) = params->emc_cmd_mapping_cmd1_2;
|
||||||
|
EMC(EMC_CMD_MAPPING_CMD2_0) = params->emc_cmd_mapping_cmd2_0;
|
||||||
|
EMC(EMC_CMD_MAPPING_CMD2_1) = params->emc_cmd_mapping_cmd2_1;
|
||||||
|
EMC(EMC_CMD_MAPPING_CMD2_2) = params->emc_cmd_mapping_cmd2_2;
|
||||||
|
EMC(EMC_CMD_MAPPING_CMD3_0) = params->emc_cmd_mapping_cmd3_0;
|
||||||
|
EMC(EMC_CMD_MAPPING_CMD3_1) = params->emc_cmd_mapping_cmd3_1;
|
||||||
|
EMC(EMC_CMD_MAPPING_CMD3_2) = params->emc_cmd_mapping_cmd3_2;
|
||||||
|
EMC(EMC_CMD_MAPPING_BYTE) = params->emc_cmd_mapping_byte;
|
||||||
|
EMC(EMC_PMACRO_BRICK_MAPPING_0) = params->emc_pmacro_brick_mapping0;
|
||||||
|
EMC(EMC_PMACRO_BRICK_MAPPING_1) = params->emc_pmacro_brick_mapping1;
|
||||||
|
EMC(EMC_PMACRO_BRICK_MAPPING_2) = params->emc_pmacro_brick_mapping2;
|
||||||
|
EMC(EMC_PMACRO_BRICK_CTRL_RFU1) = (params->emc_pmacro_brick_ctrl_rfu1 & 0x1120112) | 0x1EED1EED;
|
||||||
|
EMC(EMC_CONFIG_SAMPLE_DELAY) = params->emc_config_sample_delay;
|
||||||
|
EMC(EMC_FBIO_CFG8) = params->emc_fbio_cfg8;
|
||||||
|
EMC(EMC_SWIZZLE_RANK0_BYTE0) = params->emc_swizzle_rank0_byte0;
|
||||||
|
EMC(EMC_SWIZZLE_RANK0_BYTE1) = params->emc_swizzle_rank0_byte1;
|
||||||
|
EMC(EMC_SWIZZLE_RANK0_BYTE2) = params->emc_swizzle_rank0_byte2;
|
||||||
|
EMC(EMC_SWIZZLE_RANK0_BYTE3) = params->emc_swizzle_rank0_byte3;
|
||||||
|
EMC(EMC_SWIZZLE_RANK1_BYTE0) = params->emc_swizzle_rank1_byte0;
|
||||||
|
EMC(EMC_SWIZZLE_RANK1_BYTE1) = params->emc_swizzle_rank1_byte1;
|
||||||
|
EMC(EMC_SWIZZLE_RANK1_BYTE2) = params->emc_swizzle_rank1_byte2;
|
||||||
|
EMC(EMC_SWIZZLE_RANK1_BYTE3) = params->emc_swizzle_rank1_byte3;
|
||||||
|
if (params->emc_bct_spare6)
|
||||||
|
*(vu32 *)params->emc_bct_spare6 = params->emc_bct_spare7;
|
||||||
|
EMC(EMC_XM2COMPPADCTRL) = params->emc_xm2_comp_pad_ctrl;
|
||||||
|
EMC(EMC_XM2COMPPADCTRL2) = params->emc_xm2_comp_pad_ctrl2;
|
||||||
|
EMC(EMC_XM2COMPPADCTRL3) = params->emc_xm2_comp_pad_ctrl3;
|
||||||
|
EMC(EMC_AUTO_CAL_CONFIG2) = params->emc_auto_cal_config2;
|
||||||
|
EMC(EMC_AUTO_CAL_CONFIG3) = params->emc_auto_cal_config3;
|
||||||
|
EMC(EMC_AUTO_CAL_CONFIG4) = params->emc_auto_cal_config4;
|
||||||
|
EMC(EMC_AUTO_CAL_CONFIG5) = params->emc_auto_cal_config5;
|
||||||
|
EMC(EMC_AUTO_CAL_CONFIG6) = params->emc_auto_cal_config6;
|
||||||
|
EMC(EMC_AUTO_CAL_CONFIG7) = params->emc_auto_cal_config7;
|
||||||
|
EMC(EMC_AUTO_CAL_CONFIG8) = params->emc_auto_cal_config8;
|
||||||
|
EMC(EMC_PMACRO_RX_TERM) = params->emc_pmacro_rx_term;
|
||||||
|
EMC(EMC_PMACRO_DQ_TX_DRV) = params->emc_pmacro_dq_tx_drive;
|
||||||
|
EMC(EMC_PMACRO_CA_TX_DRV) = params->emc_pmacro_ca_tx_drive;
|
||||||
|
EMC(EMC_PMACRO_CMD_TX_DRV) = params->emc_pmacro_cmd_tx_drive;
|
||||||
|
EMC(EMC_PMACRO_AUTOCAL_CFG_COMMON) = params->emc_pmacro_auto_cal_common;
|
||||||
|
EMC(EMC_AUTO_CAL_CHANNEL) = params->emc_auto_cal_channel;
|
||||||
|
EMC(EMC_PMACRO_ZCTRL) = params->emc_pmacro_zcrtl;
|
||||||
|
EMC(EMC_DLL_CFG_0) = params->emc_dll_cfg0;
|
||||||
|
EMC(EMC_DLL_CFG_1) = params->emc_dll_cfg1;
|
||||||
|
EMC(EMC_CFG_DIG_DLL_1) = params->emc_cfg_dig_dll_1;
|
||||||
|
EMC(EMC_DATA_BRLSHFT_0) = params->emc_data_brlshft0;
|
||||||
|
EMC(EMC_DATA_BRLSHFT_1) = params->emc_data_brlshft1;
|
||||||
|
EMC(EMC_DQS_BRLSHFT_0) = params->emc_dqs_brlshft0;
|
||||||
|
EMC(EMC_DQS_BRLSHFT_1) = params->emc_dqs_brlshft1;
|
||||||
|
EMC(EMC_CMD_BRLSHFT_0) = params->emc_cmd_brlshft0;
|
||||||
|
EMC(EMC_CMD_BRLSHFT_1) = params->emc_cmd_brlshft1;
|
||||||
|
EMC(EMC_CMD_BRLSHFT_2) = params->emc_cmd_brlshft2;
|
||||||
|
EMC(EMC_CMD_BRLSHFT_3) = params->emc_cmd_brlshft3;
|
||||||
|
EMC(EMC_QUSE_BRLSHFT_0) = params->emc_quse_brlshft0;
|
||||||
|
EMC(EMC_QUSE_BRLSHFT_1) = params->emc_quse_brlshft1;
|
||||||
|
EMC(EMC_QUSE_BRLSHFT_2) = params->emc_quse_brlshft2;
|
||||||
|
EMC(EMC_QUSE_BRLSHFT_3) = params->emc_quse_brlshft3;
|
||||||
|
EMC(EMC_PMACRO_BRICK_CTRL_RFU1) = (params->emc_pmacro_brick_ctrl_rfu1 & 0x1BF01BF) | 0x1E401E40;
|
||||||
|
EMC(EMC_PMACRO_PAD_CFG_CTRL) = params->emc_pmacro_pad_cfg_ctrl;
|
||||||
|
EMC(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->emc_pmacro_cmd_brick_ctrl_fdpd;
|
||||||
|
EMC(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2 & 0xFF7FFF7F;
|
||||||
|
EMC(EMC_PMACRO_DATA_BRICK_CTRL_FDPD) = params->emc_pmacro_data_brick_ctrl_fdpd;
|
||||||
|
EMC(EMC_PMACRO_BG_BIAS_CTRL_0) = params->emc_pmacro_bg_bias_ctrl0;
|
||||||
|
EMC(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->emc_pmacro_data_pad_rx_ctrl;
|
||||||
|
EMC(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->emc_pmacro_cmd_pad_rx_ctrl;
|
||||||
|
EMC(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->emc_pmacro_data_pad_tx_ctrl;
|
||||||
|
EMC(EMC_PMACRO_DATA_RX_TERM_MODE) = params->emc_pmacro_data_rx_term_mode;
|
||||||
|
EMC(EMC_PMACRO_CMD_RX_TERM_MODE) = params->emc_pmacro_cmd_rx_term_mode;
|
||||||
|
EMC(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->emc_pmacro_cmd_pad_tx_ctrl;
|
||||||
|
EMC(EMC_CFG_3) = params->emc_cfg3;
|
||||||
|
EMC(EMC_PMACRO_TX_PWRD_0) = params->emc_pmacro_tx_pwrd0;
|
||||||
|
EMC(EMC_PMACRO_TX_PWRD_1) = params->emc_pmacro_tx_pwrd1;
|
||||||
|
EMC(EMC_PMACRO_TX_PWRD_2) = params->emc_pmacro_tx_pwrd2;
|
||||||
|
EMC(EMC_PMACRO_TX_PWRD_3) = params->emc_pmacro_tx_pwrd3;
|
||||||
|
EMC(EMC_PMACRO_TX_PWRD_4) = params->emc_pmacro_tx_pwrd4;
|
||||||
|
EMC(EMC_PMACRO_TX_PWRD_5) = params->emc_pmacro_tx_pwrd5;
|
||||||
|
EMC(EMC_PMACRO_TX_SEL_CLK_SRC_0) = params->emc_pmacro_tx_sel_clk_src0;
|
||||||
|
EMC(EMC_PMACRO_TX_SEL_CLK_SRC_1) = params->emc_pmacro_tx_sel_clk_src1;
|
||||||
|
EMC(EMC_PMACRO_TX_SEL_CLK_SRC_2) = params->emc_pmacro_tx_sel_clk_src2;
|
||||||
|
EMC(EMC_PMACRO_TX_SEL_CLK_SRC_3) = params->emc_pmacro_tx_sel_clk_src3;
|
||||||
|
EMC(EMC_PMACRO_TX_SEL_CLK_SRC_4) = params->emc_pmacro_tx_sel_clk_src4;
|
||||||
|
EMC(EMC_PMACRO_TX_SEL_CLK_SRC_5) = params->emc_pmacro_tx_sel_clk_src5;
|
||||||
|
EMC(EMC_PMACRO_DDLL_BYPASS) = params->emc_pmacro_ddll_bypass;
|
||||||
|
EMC(EMC_PMACRO_DDLL_PWRD_0) = params->emc_pmacro_ddll_pwrd0;
|
||||||
|
EMC(EMC_PMACRO_DDLL_PWRD_1) = params->emc_pmacro_ddll_pwrd1;
|
||||||
|
EMC(EMC_PMACRO_DDLL_PWRD_2) = params->emc_pmacro_ddll_pwrd2;
|
||||||
|
EMC(EMC_PMACRO_CMD_CTRL_0) = params->emc_pmacro_cmd_ctrl0;
|
||||||
|
EMC(EMC_PMACRO_CMD_CTRL_1) = params->emc_pmacro_cmd_ctrl1;
|
||||||
|
EMC(EMC_PMACRO_CMD_CTRL_2) = params->emc_pmacro_cmd_ctrl2;
|
||||||
|
EMC(EMC_PMACRO_IB_VREF_DQ_0) = params->emc_pmacro_ib_vref_dq_0;
|
||||||
|
EMC(EMC_PMACRO_IB_VREF_DQ_1) = params->emc_pmacro_ib_vref_dq_1;
|
||||||
|
EMC(EMC_PMACRO_IB_VREF_DQS_0) = params->emc_pmacro_ib_vref_dqs_0;
|
||||||
|
EMC(EMC_PMACRO_IB_VREF_DQS_1) = params->emc_pmacro_ib_vref_dqs_1;
|
||||||
|
EMC(EMC_PMACRO_IB_RXRT) = params->emc_pmacro_ib_rxrt;
|
||||||
|
EMC(EMC_PMACRO_QUSE_DDLL_RANK0_0) = params->emc_pmacro_quse_ddll_rank0_0;
|
||||||
|
EMC(EMC_PMACRO_QUSE_DDLL_RANK0_1) = params->emc_pmacro_quse_ddll_rank0_1;
|
||||||
|
EMC(EMC_PMACRO_QUSE_DDLL_RANK0_2) = params->emc_pmacro_quse_ddll_rank0_2;
|
||||||
|
EMC(EMC_PMACRO_QUSE_DDLL_RANK0_3) = params->emc_pmacro_quse_ddll_rank0_3;
|
||||||
|
EMC(EMC_PMACRO_QUSE_DDLL_RANK0_4) = params->emc_pmacro_quse_ddll_rank0_4;
|
||||||
|
EMC(EMC_PMACRO_QUSE_DDLL_RANK0_5) = params->emc_pmacro_quse_ddll_rank0_5;
|
||||||
|
EMC(EMC_PMACRO_QUSE_DDLL_RANK1_0) = params->emc_pmacro_quse_ddll_rank1_0;
|
||||||
|
EMC(EMC_PMACRO_QUSE_DDLL_RANK1_1) = params->emc_pmacro_quse_ddll_rank1_1;
|
||||||
|
EMC(EMC_PMACRO_QUSE_DDLL_RANK1_2) = params->emc_pmacro_quse_ddll_rank1_2;
|
||||||
|
EMC(EMC_PMACRO_QUSE_DDLL_RANK1_3) = params->emc_pmacro_quse_ddll_rank1_3;
|
||||||
|
EMC(EMC_PMACRO_QUSE_DDLL_RANK1_4) = params->emc_pmacro_quse_ddll_rank1_4;
|
||||||
|
EMC(EMC_PMACRO_QUSE_DDLL_RANK1_5) = params->emc_pmacro_quse_ddll_rank1_5;
|
||||||
|
EMC(EMC_PMACRO_BRICK_CTRL_RFU1) = params->emc_pmacro_brick_ctrl_rfu1;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0) = params->emc_pmacro_ob_ddll_long_dq_rank0_0;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1) = params->emc_pmacro_ob_ddll_long_dq_rank0_1;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2) = params->emc_pmacro_ob_ddll_long_dq_rank0_2;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3) = params->emc_pmacro_ob_ddll_long_dq_rank0_3;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4) = params->emc_pmacro_ob_ddll_long_dq_rank0_4;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5) = params->emc_pmacro_ob_ddll_long_dq_rank0_5;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0) = params->emc_pmacro_ob_ddll_long_dq_rank1_0;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1) = params->emc_pmacro_ob_ddll_long_dq_rank1_1;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2) = params->emc_pmacro_ob_ddll_long_dq_rank1_2;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3) = params->emc_pmacro_ob_ddll_long_dq_rank1_3;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4) = params->emc_pmacro_ob_ddll_long_dq_rank1_4;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5) = params->emc_pmacro_ob_ddll_long_dq_rank1_5;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0) = params->emc_pmacro_ob_ddll_long_dqs_rank0_0;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1) = params->emc_pmacro_ob_ddll_long_dqs_rank0_1;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2) = params->emc_pmacro_ob_ddll_long_dqs_rank0_2;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3) = params->emc_pmacro_ob_ddll_long_dqs_rank0_3;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4) = params->emc_pmacro_ob_ddll_long_dqs_rank0_4;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5) = params->emc_pmacro_ob_ddll_long_dqs_rank0_5;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0) = params->emc_pmacro_ob_ddll_long_dqs_rank1_0;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1) = params->emc_pmacro_ob_ddll_long_dqs_rank1_1;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2) = params->emc_pmacro_ob_ddll_long_dqs_rank1_2;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3) = params->emc_pmacro_ob_ddll_long_dqs_rank1_3;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4) = params->emc_pmacro_ob_ddll_long_dqs_rank1_4;
|
||||||
|
EMC(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5) = params->emc_pmacro_ob_ddll_long_dqs_rank1_5;
|
||||||
|
EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0) = params->emc_pmacro_ib_ddll_long_dqs_rank0_0;
|
||||||
|
EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1) = params->emc_pmacro_ib_ddll_long_dqs_rank0_1;
|
||||||
|
EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2) = params->emc_pmacro_ib_ddll_long_dqs_rank0_2;
|
||||||
|
EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3) = params->emc_pmacro_ib_ddll_long_dqs_rank0_3;
|
||||||
|
EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0) = params->emc_pmacro_ib_ddll_long_dqs_rank1_0;
|
||||||
|
EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1) = params->emc_pmacro_ib_ddll_long_dqs_rank1_1;
|
||||||
|
EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2) = params->emc_pmacro_ib_ddll_long_dqs_rank1_2;
|
||||||
|
EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3) = params->emc_pmacro_ib_ddll_long_dqs_rank1_3;
|
||||||
|
EMC(EMC_PMACRO_DDLL_LONG_CMD_0) = params->emc_pmacro_ddll_long_cmd_0;
|
||||||
|
EMC(EMC_PMACRO_DDLL_LONG_CMD_1) = params->emc_pmacro_ddll_long_cmd_1;
|
||||||
|
EMC(EMC_PMACRO_DDLL_LONG_CMD_2) = params->emc_pmacro_ddll_long_cmd_2;
|
||||||
|
EMC(EMC_PMACRO_DDLL_LONG_CMD_3) = params->emc_pmacro_ddll_long_cmd_3;
|
||||||
|
EMC(EMC_PMACRO_DDLL_LONG_CMD_4) = params->emc_pmacro_ddll_long_cmd_4;
|
||||||
|
EMC(EMC_PMACRO_DDLL_SHORT_CMD_0) = params->emc_pmacro_ddll_short_cmd_0;
|
||||||
|
EMC(EMC_PMACRO_DDLL_SHORT_CMD_1) = params->emc_pmacro_ddll_short_cmd_1;
|
||||||
|
EMC(EMC_PMACRO_DDLL_SHORT_CMD_2) = params->emc_pmacro_ddll_short_cmd_2;
|
||||||
|
EMC(EMC_PMACRO_COMMON_PAD_TX_CTRL) = (params->emc_pmacro_common_pad_tx_ctrl & 1) | 0xE;
|
||||||
|
if (params->emc_bct_spare4)
|
||||||
|
*(vu32 *)params->emc_bct_spare4 = params->emc_bct_spare5;
|
||||||
|
EMC(EMC_TIMING_CONTROL) = 1;
|
||||||
|
MC(MC_VIDEO_PROTECT_BOM) = params->mc_video_protect_bom;
|
||||||
|
MC(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->mc_video_protect_bom_adr_hi;
|
||||||
|
MC(MC_VIDEO_PROTECT_SIZE_MB) = params->mc_video_protect_size_mb;
|
||||||
|
MC(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->mc_video_protect_vpr_override;
|
||||||
|
MC(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->mc_video_protect_vpr_override1;
|
||||||
|
MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = params->mc_video_protect_gpu_override0;
|
||||||
|
MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = params->mc_video_protect_gpu_override1;
|
||||||
|
MC(MC_EMEM_ADR_CFG) = params->mc_emem_adr_cfg;
|
||||||
|
MC(MC_EMEM_ADR_CFG_DEV0) = params->mc_emem_adr_cfg_dev0;
|
||||||
|
MC(MC_EMEM_ADR_CFG_DEV1) = params->mc_emem_adr_cfg_dev1;
|
||||||
|
MC(MC_EMEM_ADR_CFG_CHANNEL_MASK) = params->mc_emem_adr_cfg_channel_mask;
|
||||||
|
MC(MC_EMEM_ADR_CFG_BANK_MASK_0) = params->mc_emem_adr_cfg_bank_mask0;
|
||||||
|
MC(MC_EMEM_ADR_CFG_BANK_MASK_1) = params->mc_emem_adr_cfg_bank_mask1;
|
||||||
|
MC(MC_EMEM_ADR_CFG_BANK_MASK_2) = params->mc_emem_adr_cfg_bank_mask2;
|
||||||
|
MC(MC_EMEM_CFG) = params->mc_emem_cfg;
|
||||||
|
MC(MC_SEC_CARVEOUT_BOM) = params->mc_sec_carveout_bom;
|
||||||
|
MC(MC_SEC_CARVEOUT_ADR_HI) = params->mc_sec_carveout_adr_hi;
|
||||||
|
MC(MC_SEC_CARVEOUT_SIZE_MB) = params->mc_sec_carveout_size_mb;
|
||||||
|
MC(MC_MTS_CARVEOUT_BOM) = params->mc_mts_carveout_bom;
|
||||||
|
MC(MC_MTS_CARVEOUT_ADR_HI) = params->mc_mts_carveout_adr_hi;
|
||||||
|
MC(MC_MTS_CARVEOUT_SIZE_MB) = params->mc_mts_carveout_size_mb;
|
||||||
|
MC(MC_EMEM_ARB_CFG) = params->mc_emem_arb_cfg;
|
||||||
|
MC(MC_EMEM_ARB_OUTSTANDING_REQ) = params->mc_emem_arb_outstanding_req;
|
||||||
|
MC(MC_EMEM_ARB_REFPB_HP_CTRL) = params->emc_emem_arb_refpb_hp_ctrl;
|
||||||
|
MC(MC_EMEM_ARB_REFPB_BANK_CTRL) = params->emc_emem_arb_refpb_bank_ctrl;
|
||||||
|
MC(MC_EMEM_ARB_TIMING_RCD) = params->mc_emem_arb_timing_rcd;
|
||||||
|
MC(MC_EMEM_ARB_TIMING_RP) = params->mc_emem_arb_timing_rp;
|
||||||
|
MC(MC_EMEM_ARB_TIMING_RC) = params->mc_emem_arb_timing_rc;
|
||||||
|
MC(MC_EMEM_ARB_TIMING_RAS) = params->mc_emem_arb_timing_ras;
|
||||||
|
MC(MC_EMEM_ARB_TIMING_FAW) = params->mc_emem_arb_timing_faw;
|
||||||
|
MC(MC_EMEM_ARB_TIMING_RRD) = params->mc_emem_arb_timing_rrd;
|
||||||
|
MC(MC_EMEM_ARB_TIMING_RAP2PRE) = params->mc_emem_arb_timing_rap2pre;
|
||||||
|
MC(MC_EMEM_ARB_TIMING_WAP2PRE) = params->mc_emem_arb_timing_wap2pre;
|
||||||
|
MC(MC_EMEM_ARB_TIMING_R2R) = params->mc_emem_arb_timing_r2r;
|
||||||
|
MC(MC_EMEM_ARB_TIMING_W2W) = params->mc_emem_arb_timing_w2w;
|
||||||
|
MC(MC_EMEM_ARB_TIMING_CCDMW) = params->mc_emem_arb_timing_ccdmw;
|
||||||
|
MC(MC_EMEM_ARB_TIMING_R2W) = params->mc_emem_arb_timing_r2w;
|
||||||
|
MC(MC_EMEM_ARB_TIMING_W2R) = params->mc_emem_arb_timing_w2r;
|
||||||
|
MC(MC_EMEM_ARB_TIMING_RFCPB) = params->mc_emem_arb_timing_rfcpb;
|
||||||
|
MC(MC_EMEM_ARB_DA_TURNS) = params->mc_emem_arb_da_turns;
|
||||||
|
MC(MC_EMEM_ARB_DA_COVERS) = params->mc_emem_arb_da_covers;
|
||||||
|
MC(MC_EMEM_ARB_MISC0) = params->mc_emem_arb_misc0;
|
||||||
|
MC(MC_EMEM_ARB_MISC1) = params->mc_emem_arb_misc1;
|
||||||
|
MC(MC_EMEM_ARB_MISC2) = params->mc_emem_arb_misc2;
|
||||||
|
MC(MC_EMEM_ARB_RING1_THROTTLE) = params->mc_emem_arb_ring1_throttle;
|
||||||
|
MC(MC_EMEM_ARB_OVERRIDE) = params->mc_emem_arb_override;
|
||||||
|
MC(MC_EMEM_ARB_OVERRIDE_1) = params->mc_emem_arb_override1;
|
||||||
|
MC(MC_EMEM_ARB_RSV) = params->mc_emem_arb_rsv;
|
||||||
|
MC(MC_DA_CONFIG0) = params->mc_da_cfg0;
|
||||||
|
MC(MC_TIMING_CONTROL) = 1;
|
||||||
|
MC(MC_CLKEN_OVERRIDE) = params->mc_clken_override;
|
||||||
|
MC(MC_STAT_CONTROL) = params->mc_stat_control;
|
||||||
|
EMC(EMC_ADR_CFG) = params->emc_adr_cfg;
|
||||||
|
EMC(EMC_CLKEN_OVERRIDE) = params->emc_clken_override;
|
||||||
|
EMC(EMC_PMACRO_AUTOCAL_CFG_0) = params->emc_pmacro_auto_cal_cfg0;
|
||||||
|
EMC(EMC_PMACRO_AUTOCAL_CFG_1) = params->emc_pmacro_auto_cal_cfg1;
|
||||||
|
EMC(EMC_PMACRO_AUTOCAL_CFG_2) = params->emc_pmacro_auto_cal_cfg2;
|
||||||
|
EMC(EMC_AUTO_CAL_VREF_SEL_0) = params->emc_auto_cal_vref_sel0;
|
||||||
|
EMC(EMC_AUTO_CAL_VREF_SEL_1) = params->emc_auto_cal_vref_sel1;
|
||||||
|
EMC(EMC_AUTO_CAL_INTERVAL) = params->emc_auto_cal_interval;
|
||||||
|
EMC(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config;
|
||||||
|
usleep(params->emc_auto_cal_wait);
|
||||||
|
if (params->emc_bct_spare8)
|
||||||
|
*(vu32 *)params->emc_bct_spare8 = params->emc_bct_spare9;
|
||||||
|
EMC(EMC_CFG_2) = params->emc_cfg2;
|
||||||
|
EMC(EMC_CFG_PIPE) = params->emc_cfg_pipe;
|
||||||
|
EMC(EMC_CFG_PIPE_1) = params->emc_cfg_pipe1;
|
||||||
|
EMC(EMC_CFG_PIPE_2) = params->emc_cfg_pipe2;
|
||||||
|
EMC(EMC_CMDQ) = params->emc_cmd_q;
|
||||||
|
EMC(EMC_MC2EMCQ) = params->emc_mc2emc_q;
|
||||||
|
EMC(EMC_MRS_WAIT_CNT) = params->emc_mrs_wait_cnt;
|
||||||
|
EMC(EMC_MRS_WAIT_CNT2) = params->emc_mrs_wait_cnt2;
|
||||||
|
EMC(EMC_FBIO_CFG5) = params->emc_fbio_cfg5;
|
||||||
|
EMC(EMC_RC) = params->emc_rc;
|
||||||
|
EMC(EMC_RFC) = params->emc_rfc;
|
||||||
|
EMC(EMC_RFCPB) = params->emc_rfc_pb;
|
||||||
|
EMC(EMC_REFCTRL2) = params->emc_ref_ctrl2;
|
||||||
|
EMC(EMC_RFC_SLR) = params->emc_rfc_slr;
|
||||||
|
EMC(EMC_RAS) = params->emc_ras;
|
||||||
|
EMC(EMC_RP) = params->emc_rp;
|
||||||
|
EMC(EMC_TPPD) = params->emc_tppd;
|
||||||
|
EMC(EMC_R2R) = params->emc_r2r;
|
||||||
|
EMC(EMC_W2W) = params->emc_w2w;
|
||||||
|
EMC(EMC_R2W) = params->emc_r2w;
|
||||||
|
EMC(EMC_W2R) = params->emc_w2r;
|
||||||
|
EMC(EMC_R2P) = params->emc_r2p;
|
||||||
|
EMC(EMC_W2P) = params->emc_w2p;
|
||||||
|
EMC(EMC_CCDMW) = params->emc_ccdmw;
|
||||||
|
EMC(EMC_RD_RCD) = params->emc_rd_rcd;
|
||||||
|
EMC(EMC_WR_RCD) = params->emc_wr_rcd;
|
||||||
|
EMC(EMC_RRD) = params->emc_rrd;
|
||||||
|
EMC(EMC_REXT) = params->emc_rext;
|
||||||
|
EMC(EMC_WEXT) = params->emc_wext;
|
||||||
|
EMC(EMC_WDV) = params->emc_wdv;
|
||||||
|
EMC(EMC_WDV_CHK) = params->emc_wdv_chk;
|
||||||
|
EMC(EMC_WSV) = params->emc_wsv;
|
||||||
|
EMC(EMC_WEV) = params->emc_wev;
|
||||||
|
EMC(EMC_WDV_MASK) = params->emc_wdv_mask;
|
||||||
|
EMC(EMC_WS_DURATION) = params->emc_ws_duration;
|
||||||
|
EMC(EMC_WE_DURATION) = params->emc_we_duration;
|
||||||
|
EMC(EMC_QUSE) = params->emc_quse;
|
||||||
|
EMC(EMC_QUSE_WIDTH) = params->emc_quse_width;
|
||||||
|
EMC(EMC_IBDLY) = params->emc_ibdly;
|
||||||
|
EMC(EMC_OBDLY) = params->emc_obdly;
|
||||||
|
EMC(EMC_EINPUT) = params->emc_einput;
|
||||||
|
EMC(EMC_EINPUT_DURATION) = params->emc_einput_duration;
|
||||||
|
EMC(EMC_PUTERM_EXTRA) = params->emc_puterm_extra;
|
||||||
|
EMC(EMC_PUTERM_WIDTH) = params->emc_puterm_width;
|
||||||
|
EMC(EMC_PMACRO_COMMON_PAD_TX_CTRL) = params->emc_pmacro_common_pad_tx_ctrl;
|
||||||
|
EMC(EMC_DBG) = params->emc_dbg;
|
||||||
|
EMC(EMC_QRST) = params->emc_qrst;
|
||||||
|
EMC(EMC_ISSUE_QRST) = 0;
|
||||||
|
EMC(EMC_QSAFE) = params->emc_qsafe;
|
||||||
|
EMC(EMC_RDV) = params->emc_rdv;
|
||||||
|
EMC(EMC_RDV_MASK) = params->emc_rdv_mask;
|
||||||
|
EMC(EMC_RDV_EARLY) = params->emc_rdv_early;
|
||||||
|
EMC(EMC_RDV_EARLY_MASK) = params->emc_rdv_early_mask;
|
||||||
|
EMC(EMC_QPOP) = params->emc_qpop;
|
||||||
|
EMC(EMC_REFRESH) = params->emc_refresh;
|
||||||
|
EMC(EMC_BURST_REFRESH_NUM) = params->emc_burst_refresh_num;
|
||||||
|
EMC(EMC_PRE_REFRESH_REQ_CNT) = params->emc_prerefresh_req_cnt;
|
||||||
|
EMC(EMC_PDEX2WR) = params->emc_pdex2wr;
|
||||||
|
EMC(EMC_PDEX2RD) = params->emc_pdex2rd;
|
||||||
|
EMC(EMC_PCHG2PDEN) = params->emc_pchg2pden;
|
||||||
|
EMC(EMC_ACT2PDEN) = params->emc_act2pden;
|
||||||
|
EMC(EMC_AR2PDEN) = params->emc_ar2pden;
|
||||||
|
EMC(EMC_RW2PDEN) = params->emc_rw2pden;
|
||||||
|
EMC(EMC_CKE2PDEN) = params->emc_cke2pden;
|
||||||
|
EMC(EMC_PDEX2CKE) = params->emc_pdex2che;
|
||||||
|
EMC(EMC_PDEX2MRR) = params->emc_pdex2mrr;
|
||||||
|
EMC(EMC_TXSR) = params->emc_txsr;
|
||||||
|
EMC(EMC_TXSRDLL) = params->emc_txsr_dll;
|
||||||
|
EMC(EMC_TCKE) = params->emc_tcke;
|
||||||
|
EMC(EMC_TCKESR) = params->emc_tckesr;
|
||||||
|
EMC(EMC_TPD) = params->emc_tpd;
|
||||||
|
EMC(EMC_TFAW) = params->emc_tfaw;
|
||||||
|
EMC(EMC_TRPAB) = params->emc_trpab;
|
||||||
|
EMC(EMC_TCLKSTABLE) = params->emc_tclkstable;
|
||||||
|
EMC(EMC_TCLKSTOP) = params->emc_tclkstop;
|
||||||
|
EMC(EMC_TREFBW) = params->emc_trefbw;
|
||||||
|
EMC(EMC_ODT_WRITE) = params->emc_odt_write;
|
||||||
|
EMC(EMC_CFG_DIG_DLL) = params->emc_cfg_dig_dll;
|
||||||
|
EMC(EMC_CFG_DIG_DLL_PERIOD) = params->emc_cfg_dig_dll_period;
|
||||||
|
EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare & 0xFFFFFFFD;
|
||||||
|
EMC(EMC_CFG_RSV) = params->emc_cfg_rsv;
|
||||||
|
EMC(EMC_PMC_SCRATCH1) = params->emc_pmc_scratch1;
|
||||||
|
EMC(EMC_PMC_SCRATCH2) = params->emc_pmc_scratch2;
|
||||||
|
EMC(EMC_PMC_SCRATCH3) = params->emc_pmc_scratch3;
|
||||||
|
EMC(EMC_ACPD_CONTROL) = params->emc_acpd_control;
|
||||||
|
EMC(EMC_TXDSRVTTGEN) = params->emc_txdsrvttgen;
|
||||||
|
EMC(EMC_CFG) = (params->emc_cfg & 0xE) | 0x3C00000;
|
||||||
|
if (params->boot_rom_patch_control & (1 << 31))
|
||||||
|
{
|
||||||
|
*(vu32 *)(APB_MISC_BASE + params->boot_rom_patch_control * 4) = params->boot_rom_patch_data;
|
||||||
|
MC(MC_TIMING_CONTROL) = 1;
|
||||||
|
}
|
||||||
|
PMC(APBDEV_PMC_IO_DPD3_REQ) = ((4 * params->emc_pmc_scratch1 >> 2) + 0x40000000) & 0xCFFF0000;
|
||||||
|
usleep(params->pmc_io_dpd3_req_wait);
|
||||||
|
if (!params->emc_auto_cal_interval)
|
||||||
|
EMC(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config | 0x200;
|
||||||
|
EMC(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2;
|
||||||
|
if (params->emc_zcal_warm_cold_boot_enables & 1)
|
||||||
|
{
|
||||||
|
if (params->memory_type == 2)
|
||||||
|
EMC(EMC_ZCAL_WAIT_CNT) = 8 * params->emc_zcal_wait_cnt;
|
||||||
|
if (params->memory_type == 3)
|
||||||
|
{
|
||||||
|
EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt;
|
||||||
|
EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
EMC(EMC_TIMING_CONTROL) = 1;
|
||||||
|
usleep(params->emc_timing_control_wait);
|
||||||
|
PMC(APBDEV_PMC_DDR_CNTRL) &= 0xFFF8007F;
|
||||||
|
usleep(params->pmc_ddr_ctrl_wait);
|
||||||
|
if (params->memory_type == 2)
|
||||||
|
{
|
||||||
|
EMC(EMC_PIN) = (params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12);
|
||||||
|
usleep(params->emc_pin_extra_wait + 200);
|
||||||
|
EMC(EMC_PIN) = ((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 256;
|
||||||
|
usleep(params->emc_pin_extra_wait + 500);
|
||||||
|
}
|
||||||
|
if (params->memory_type == 3)
|
||||||
|
{
|
||||||
|
EMC(EMC_PIN) = (params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12);
|
||||||
|
usleep(params->emc_pin_extra_wait + 200);
|
||||||
|
EMC(EMC_PIN) = ((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 256;
|
||||||
|
usleep(params->emc_pin_extra_wait + 2000);
|
||||||
|
}
|
||||||
|
EMC(EMC_PIN) = ((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 0x101;
|
||||||
|
usleep(params->emc_pin_program_wait);
|
||||||
|
if (params->memory_type != 3)
|
||||||
|
EMC(EMC_NOP) = (params->emc_dev_select << 30) + 1;
|
||||||
|
if (params->memory_type == 1)
|
||||||
|
usleep(params->emc_pin_extra_wait + 200);
|
||||||
|
if (params->memory_type == 3)
|
||||||
|
{
|
||||||
|
if (params->emc_bct_spare10)
|
||||||
|
*(vu32 *)params->emc_bct_spare10 = params->emc_bct_spare11;
|
||||||
|
EMC(EMC_MRW2) = params->emc_mrw2;
|
||||||
|
EMC(EMC_MRW) = params->emc_mrw1;
|
||||||
|
EMC(EMC_MRW3) = params->emc_mrw3;
|
||||||
|
EMC(EMC_MRW4) = params->emc_mrw4;
|
||||||
|
EMC(EMC_MRW6) = params->emc_mrw6;
|
||||||
|
EMC(EMC_MRW14) = params->emc_mrw14;
|
||||||
|
EMC(EMC_MRW8) = params->emc_mrw8;
|
||||||
|
EMC(EMC_MRW12) = params->emc_mrw12;
|
||||||
|
EMC(EMC_MRW9) = params->emc_mrw9;
|
||||||
|
EMC(EMC_MRW13) = params->emc_mrw13;
|
||||||
|
if (params->emc_zcal_warm_cold_boot_enables & 1)
|
||||||
|
{
|
||||||
|
EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev0;
|
||||||
|
usleep(params->emc_zcal_init_wait);
|
||||||
|
EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev0 ^ 3;
|
||||||
|
if (!(params->emc_dev_select & 2))
|
||||||
|
{
|
||||||
|
EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev1;
|
||||||
|
usleep(params->emc_zcal_init_wait);
|
||||||
|
EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev1 ^ 3;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
PMC(APBDEV_PMC_DDR_CFG) = params->pmc_ddr_cfg;
|
||||||
|
if (params->memory_type - 1 <= 2)
|
||||||
|
{
|
||||||
|
EMC(EMC_ZCAL_INTERVAL) = params->emc_zcal_interval;
|
||||||
|
EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt;
|
||||||
|
EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd;
|
||||||
|
}
|
||||||
|
if (params->emc_bct_spare12)
|
||||||
|
*(vu32 *)params->emc_bct_spare12 = params->emc_bct_spare13;
|
||||||
|
EMC(EMC_TIMING_CONTROL) = 1;
|
||||||
|
if (params->emc_extra_refresh_num)
|
||||||
|
EMC(EMC_REF) = ((1 << params->emc_extra_refresh_num << 8) - 0xFD) | (params->emc_pin_gpio << 30);
|
||||||
|
EMC(EMC_REFCTRL) = params->emc_dev_select | 0x80000000;
|
||||||
|
EMC(EMC_DYN_SELF_REF_CONTROL) = params->emc_dyn_self_ref_control;
|
||||||
|
EMC(EMC_CFG_UPDATE) = params->emc_cfg_update;
|
||||||
|
EMC(EMC_CFG) = params->emc_cfg;
|
||||||
|
EMC(EMC_FDPD_CTRL_DQ) = params->emc_fdpd_ctrl_dq;
|
||||||
|
EMC(EMC_FDPD_CTRL_CMD) = params->emc_fdpd_ctrl_cmd;
|
||||||
|
EMC(EMC_SEL_DPD_CTRL) = params->emc_sel_dpd_ctrl;
|
||||||
|
EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare | 2;
|
||||||
|
EMC(EMC_TIMING_CONTROL) = 1;
|
||||||
|
EMC(EMC_CFG_PIPE_CLK) = params->emc_cfg_pipe_clk;
|
||||||
|
EMC(EMC_FDPD_CTRL_CMD_NO_RAMP) = params->emc_fdpd_ctrl_cmd_no_ramp;
|
||||||
|
SYSREG(AHB_ARBITRATION_XBAR_CTRL) = (SYSREG(AHB_ARBITRATION_XBAR_CTRL) & 0xFFFEFFFF) | ((params->ahb_arbitration_xbar_ctrl_meminit_done & 0xFFFF) << 16);
|
||||||
|
MC(MC_VIDEO_PROTECT_REG_CTRL) = params->mc_video_protect_write_access;
|
||||||
|
MC(MC_SEC_CARVEOUT_REG_CTRL) = params->mc_sec_carveout_protect_write_access;
|
||||||
|
MC(MC_MTS_CARVEOUT_REG_CTRL) = params->mc_mts_carveout_reg_ctrl;
|
||||||
|
MC(MC_EMEM_CFG_ACCESS_CTRL) = 1; //Disable write access to a bunch of EMC registers.
|
||||||
|
}
|
||||||
|
|
||||||
|
sdram_params_t *sdram_get_params()
|
||||||
|
{
|
||||||
|
//TODO: sdram_id should be in [0, 7].
|
||||||
|
|
||||||
|
#ifdef CONFIG_SDRAM_COMPRESS_CFG
|
||||||
|
u8 *buf = (u8 *)0x40030000;
|
||||||
|
LZ_Uncompress(_dram_cfg_lz, buf, sizeof(_dram_cfg_lz));
|
||||||
|
return (sdram_params_t *)&buf[sizeof(sdram_params_t) * _get_sdram_id()];
|
||||||
|
#else
|
||||||
|
return _dram_cfgs[_get_sdram_id()];
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Function: sdram_get_params_patched
|
||||||
|
*
|
||||||
|
* This code implements a warmboot exploit. Warmboot, that is actually so hot, it burns Nvidia once again.
|
||||||
|
* If the boot_rom_patch_control's MSB is set, it uses it as an index to
|
||||||
|
* APB_MISC_BASE (u32 array) and sets it to the value of boot_rom_patch_data.
|
||||||
|
* (The MSB falls out when it gets multiplied by sizeof(u32)).
|
||||||
|
* Because the bootrom does not do any boundary checks, it lets us write anywhere and anything.
|
||||||
|
* Ipatch hardware let us apply 12 changes to the bootrom and can be changed any time.
|
||||||
|
* The first patch is not needed any more when the exploit is triggered, so we overwrite that.
|
||||||
|
* 0x10459E is the address where it returns an error when the signature is not valid.
|
||||||
|
* We change that to MOV R0, #0, so we pass the check.
|
||||||
|
*
|
||||||
|
* Note: The modulus in the header must match and validated.
|
||||||
|
*/
|
||||||
|
|
||||||
|
sdram_params_t *sdram_get_params_patched()
|
||||||
|
{
|
||||||
|
#define IPATCH_CONFIG(addr, data) (((addr - 0x100000) / 2) << 16 | (data & 0xffff))
|
||||||
|
sdram_params_t *sdram_params = sdram_get_params();
|
||||||
|
|
||||||
|
// Disable Warmboot signature check.
|
||||||
|
sdram_params->boot_rom_patch_control = (1 << 31) | (((IPATCH_BASE + 4) - APB_MISC_BASE) / 4);
|
||||||
|
sdram_params->boot_rom_patch_data = IPATCH_CONFIG(0x10459E, 0x2000);
|
||||||
|
|
||||||
|
return sdram_params;
|
||||||
|
}
|
||||||
|
|
||||||
|
void sdram_init()
|
||||||
|
{
|
||||||
|
//TODO: sdram_id should be in [0,4].
|
||||||
|
const sdram_params_t *params = (const sdram_params_t *)sdram_get_params();
|
||||||
|
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD_CFG2, 0x05);
|
||||||
|
max77620_regulator_set_voltage(REGULATOR_SD1, 1100000);
|
||||||
|
|
||||||
|
PMC(APBDEV_PMC_VDDP_SEL) = params->pmc_vddp_sel;
|
||||||
|
usleep(params->pmc_vddp_sel_wait);
|
||||||
|
PMC(APBDEV_PMC_DDR_PWR) = PMC(APBDEV_PMC_DDR_PWR);
|
||||||
|
PMC(APBDEV_PMC_NO_IOPOWER) = params->pmc_no_io_power;
|
||||||
|
PMC(APBDEV_PMC_REG_SHORT) = params->pmc_reg_short;
|
||||||
|
PMC(APBDEV_PMC_DDR_CNTRL) = params->pmc_ddr_ctrl;
|
||||||
|
|
||||||
|
if (params->emc_bct_spare0)
|
||||||
|
*(vu32 *)params->emc_bct_spare0 = params->emc_bct_spare1;
|
||||||
|
|
||||||
|
_sdram_config(params);
|
||||||
|
}
|
27
source/mem/sdram.h
Normal file
27
source/mem/sdram.h
Normal file
@ -0,0 +1,27 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _SDRAM_H_
|
||||||
|
#define _SDRAM_H_
|
||||||
|
|
||||||
|
#include "sdram_param_t210.h"
|
||||||
|
|
||||||
|
void sdram_init();
|
||||||
|
sdram_params_t *sdram_get_params();
|
||||||
|
sdram_params_t *sdram_get_params_patched();
|
||||||
|
void sdram_lp0_save_params(const void *params);
|
||||||
|
|
||||||
|
#endif
|
1152
source/mem/sdram_config.inl
Normal file
1152
source/mem/sdram_config.inl
Normal file
File diff suppressed because it is too large
Load Diff
124
source/mem/sdram_config_lz.inl
Normal file
124
source/mem/sdram_config_lz.inl
Normal file
@ -0,0 +1,124 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
static const u8 _dram_cfg_lz[1262] = {
|
||||||
|
0x17, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00,
|
||||||
|
0x00, 0x2C, 0x17, 0x04, 0x09, 0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08,
|
||||||
|
0x17, 0x10, 0x10, 0x00, 0x00, 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00,
|
||||||
|
0x00, 0x04, 0xB4, 0x01, 0x70, 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00,
|
||||||
|
0x70, 0x17, 0x10, 0x24, 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40,
|
||||||
|
0x00, 0x00, 0x00, 0x17, 0x04, 0x04, 0x17, 0x09, 0x18, 0xFF, 0xFF, 0x1F,
|
||||||
|
0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05, 0x00, 0x00, 0x77,
|
||||||
|
0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08, 0x17, 0x08, 0x08, 0xA6, 0xA6,
|
||||||
|
0xAF, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x03, 0x03, 0xE0, 0xC1, 0x04, 0x04,
|
||||||
|
0x04, 0x04, 0x17, 0x04, 0x04, 0x17, 0x04, 0x3C, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||||
|
0x17, 0x04, 0x04, 0x17, 0x06, 0x06, 0x00, 0x00, 0x04, 0x08, 0x17, 0x06,
|
||||||
|
0x46, 0xA1, 0x01, 0x00, 0x00, 0x32, 0x17, 0x0B, 0x64, 0x01, 0x17, 0x04,
|
||||||
|
0x7C, 0x17, 0x07, 0x0C, 0x03, 0x17, 0x04, 0x04, 0x00, 0x00, 0x00, 0x1E,
|
||||||
|
0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x13,
|
||||||
|
0x17, 0x0B, 0x2C, 0x09, 0x00, 0x00, 0x00, 0x17, 0x05, 0x5D, 0x17, 0x07,
|
||||||
|
0x10, 0x0B, 0x17, 0x07, 0x28, 0x08, 0x17, 0x07, 0x0C, 0x17, 0x04, 0x1C,
|
||||||
|
0x20, 0x00, 0x00, 0x00, 0x06, 0x17, 0x04, 0x04, 0x17, 0x07, 0x08, 0x17,
|
||||||
|
0x04, 0x50, 0x17, 0x04, 0x2C, 0x17, 0x04, 0x1C, 0x17, 0x04, 0x10, 0x17,
|
||||||
|
0x08, 0x6C, 0x17, 0x04, 0x10, 0x17, 0x04, 0x38, 0x17, 0x04, 0x40, 0x05,
|
||||||
|
0x17, 0x07, 0x1C, 0x17, 0x08, 0x58, 0x17, 0x04, 0x24, 0x17, 0x04, 0x18,
|
||||||
|
0x17, 0x08, 0x64, 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14,
|
||||||
|
0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x17, 0x09, 0x0C, 0x17, 0x05, 0x82,
|
||||||
|
0x58, 0x17, 0x07, 0x61, 0xC1, 0x17, 0x07, 0x50, 0x17, 0x04, 0x04, 0x17,
|
||||||
|
0x08, 0x81, 0x48, 0x17, 0x04, 0x04, 0x17, 0x04, 0x28, 0x17, 0x04, 0x60,
|
||||||
|
0x17, 0x08, 0x54, 0x27, 0x17, 0x04, 0x04, 0x17, 0x07, 0x14, 0x17, 0x04,
|
||||||
|
0x04, 0x04, 0x17, 0x07, 0x81, 0x58, 0x17, 0x0C, 0x0C, 0x1C, 0x03, 0x00,
|
||||||
|
0x00, 0x0D, 0xA0, 0x60, 0x91, 0xBF, 0x3B, 0x17, 0x04, 0x5A, 0xF3, 0x0C,
|
||||||
|
0x04, 0x05, 0x1B, 0x06, 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05,
|
||||||
|
0x08, 0x1D, 0x09, 0x0A, 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03,
|
||||||
|
0x02, 0x1B, 0x1C, 0x23, 0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02,
|
||||||
|
0x0A, 0x0B, 0x1D, 0x0D, 0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08,
|
||||||
|
0x24, 0x06, 0x07, 0x9A, 0x12, 0x17, 0x05, 0x83, 0x41, 0x00, 0xFF, 0x17,
|
||||||
|
0x10, 0x83, 0x6C, 0x04, 0x00, 0x01, 0x08, 0x00, 0x00, 0x02, 0x08, 0x00,
|
||||||
|
0x00, 0x0D, 0x08, 0x00, 0x00, 0x00, 0xC0, 0x71, 0x71, 0x03, 0x08, 0x00,
|
||||||
|
0x00, 0x0B, 0x08, 0x72, 0x72, 0x0E, 0x0C, 0x17, 0x04, 0x20, 0x08, 0x08,
|
||||||
|
0x0D, 0x0C, 0x00, 0x00, 0x0D, 0x0C, 0x14, 0x14, 0x16, 0x08, 0x17, 0x06,
|
||||||
|
0x2C, 0x11, 0x08, 0x17, 0x10, 0x84, 0x67, 0x15, 0x00, 0xCC, 0x00, 0x0A,
|
||||||
|
0x00, 0x33, 0x00, 0x00, 0x00, 0x20, 0xF3, 0x05, 0x08, 0x11, 0x00, 0xFF,
|
||||||
|
0x0F, 0xFF, 0x0F, 0x17, 0x08, 0x83, 0x4C, 0x01, 0x03, 0x00, 0x70, 0x00,
|
||||||
|
0x0C, 0x00, 0x01, 0x17, 0x04, 0x0C, 0x08, 0x44, 0x00, 0x10, 0x04, 0x04,
|
||||||
|
0x00, 0x06, 0x13, 0x07, 0x00, 0x80, 0x17, 0x04, 0x10, 0xA0, 0x00, 0x2C,
|
||||||
|
0x00, 0x01, 0x37, 0x00, 0x00, 0x00, 0x80, 0x17, 0x06, 0x48, 0x08, 0x00,
|
||||||
|
0x04, 0x00, 0x1F, 0x22, 0x20, 0x80, 0x0F, 0xF4, 0x20, 0x02, 0x28, 0x28,
|
||||||
|
0x28, 0x28, 0x17, 0x04, 0x04, 0x11, 0x11, 0x11, 0x11, 0x17, 0x04, 0x04,
|
||||||
|
0xBE, 0x00, 0x00, 0x17, 0x05, 0x58, 0x17, 0x08, 0x5C, 0x17, 0x22, 0x85,
|
||||||
|
0x6A, 0x17, 0x1A, 0x1A, 0x14, 0x00, 0x12, 0x00, 0x10, 0x17, 0x05, 0x83,
|
||||||
|
0x0A, 0x17, 0x16, 0x18, 0x30, 0x00, 0x2E, 0x00, 0x33, 0x00, 0x30, 0x00,
|
||||||
|
0x33, 0x00, 0x35, 0x00, 0x30, 0x00, 0x32, 0x17, 0x05, 0x83, 0x0C, 0x17,
|
||||||
|
0x04, 0x20, 0x17, 0x18, 0x18, 0x28, 0x00, 0x28, 0x17, 0x04, 0x04, 0x17,
|
||||||
|
0x08, 0x08, 0x17, 0x10, 0x10, 0x00, 0x14, 0x17, 0x05, 0x5A, 0x17, 0x04,
|
||||||
|
0x5C, 0x17, 0x04, 0x5E, 0x17, 0x04, 0x0E, 0x17, 0x0E, 0x78, 0x17, 0x09,
|
||||||
|
0x82, 0x50, 0x40, 0x06, 0x00, 0xCC, 0x00, 0x09, 0x00, 0x4F, 0x00, 0x51,
|
||||||
|
0x17, 0x08, 0x18, 0x80, 0x01, 0x00, 0x00, 0x40, 0x17, 0x04, 0x20, 0x03,
|
||||||
|
0x00, 0x00, 0x00, 0xAB, 0x00, 0x0A, 0x04, 0x11, 0x17, 0x08, 0x82, 0x58,
|
||||||
|
0x17, 0x0C, 0x38, 0x17, 0x1B, 0x81, 0x6C, 0x17, 0x08, 0x85, 0x60, 0x17,
|
||||||
|
0x08, 0x86, 0x50, 0x17, 0x08, 0x86, 0x60, 0x17, 0x06, 0x83, 0x21, 0x22,
|
||||||
|
0x04, 0xFF, 0xFF, 0xAF, 0x4F, 0x17, 0x0C, 0x86, 0x74, 0x17, 0x08, 0x2C,
|
||||||
|
0x8B, 0xFF, 0x07, 0x17, 0x06, 0x81, 0x04, 0x32, 0x54, 0x76, 0x10, 0x47,
|
||||||
|
0x32, 0x65, 0x10, 0x34, 0x76, 0x25, 0x01, 0x34, 0x67, 0x25, 0x01, 0x75,
|
||||||
|
0x64, 0x32, 0x01, 0x72, 0x56, 0x34, 0x10, 0x23, 0x74, 0x56, 0x01, 0x45,
|
||||||
|
0x32, 0x67, 0x17, 0x04, 0x24, 0x49, 0x92, 0x24, 0x17, 0x04, 0x04, 0x17,
|
||||||
|
0x11, 0x7C, 0x1B, 0x17, 0x04, 0x04, 0x17, 0x13, 0x81, 0x14, 0x2F, 0x41,
|
||||||
|
0x13, 0x1F, 0x14, 0x00, 0x01, 0x00, 0x17, 0x04, 0x7C, 0xFF, 0xFF, 0xFF,
|
||||||
|
0x7F, 0x0B, 0xD7, 0x06, 0x40, 0x00, 0x00, 0x02, 0x00, 0x08, 0x08, 0x03,
|
||||||
|
0x00, 0x00, 0x5C, 0x01, 0x00, 0x10, 0x10, 0x10, 0x17, 0x06, 0x86, 0x59,
|
||||||
|
0x17, 0x0F, 0x89, 0x14, 0x37, 0x17, 0x07, 0x82, 0x72, 0x10, 0x17, 0x06,
|
||||||
|
0x83, 0x0D, 0x00, 0x11, 0x01, 0x17, 0x05, 0x85, 0x39, 0x17, 0x04, 0x0E,
|
||||||
|
0x0A, 0x17, 0x07, 0x89, 0x29, 0x17, 0x04, 0x1B, 0x17, 0x08, 0x86, 0x77,
|
||||||
|
0x17, 0x09, 0x12, 0x20, 0x00, 0x00, 0x00, 0x81, 0x10, 0x09, 0x28, 0x93,
|
||||||
|
0x32, 0xA5, 0x44, 0x5B, 0x8A, 0x67, 0x76, 0x17, 0x18, 0x82, 0x2C, 0xFF,
|
||||||
|
0xEF, 0xFF, 0xEF, 0xC0, 0xC0, 0xC0, 0xC0, 0x17, 0x04, 0x04, 0xDC, 0xDC,
|
||||||
|
0xDC, 0xDC, 0x0A, 0x0A, 0x0A, 0x0A, 0x17, 0x04, 0x04, 0x17, 0x04, 0x04,
|
||||||
|
0x17, 0x05, 0x82, 0x24, 0x03, 0x07, 0x17, 0x04, 0x04, 0x00, 0x00, 0x24,
|
||||||
|
0xFF, 0xFF, 0x00, 0x44, 0x57, 0x6E, 0x00, 0x28, 0x72, 0x39, 0x00, 0x10,
|
||||||
|
0x9C, 0x4B, 0x17, 0x04, 0x64, 0x01, 0x00, 0x00, 0x08, 0x4C, 0x00, 0x00,
|
||||||
|
0x80, 0x20, 0x10, 0x0A, 0x00, 0x28, 0x10, 0x17, 0x06, 0x85, 0x60, 0x17,
|
||||||
|
0x10, 0x82, 0x74, 0x17, 0x08, 0x08, 0x17, 0x08, 0x88, 0x00, 0x17, 0x04,
|
||||||
|
0x10, 0x04, 0x17, 0x0B, 0x87, 0x6C, 0x01, 0x00, 0x02, 0x02, 0x01, 0x02,
|
||||||
|
0x03, 0x00, 0x04, 0x05, 0xC3, 0x71, 0x0F, 0x0F, 0x17, 0x08, 0x8B, 0x18,
|
||||||
|
0x1F, 0x17, 0x09, 0x81, 0x73, 0x00, 0xFF, 0x00, 0xFF, 0x17, 0x05, 0x86,
|
||||||
|
0x48, 0x17, 0x04, 0x0C, 0x17, 0x07, 0x86, 0x34, 0x00, 0x00, 0xF0, 0x17,
|
||||||
|
0x09, 0x87, 0x54, 0x43, 0xC3, 0xBA, 0xE4, 0xD3, 0x1E, 0x17, 0x0C, 0x81,
|
||||||
|
0x52, 0x17, 0x0A, 0x1C, 0x17, 0x10, 0x81, 0x6C, 0x17, 0x0A, 0x82, 0x21,
|
||||||
|
0x17, 0x07, 0x82, 0x4D, 0x17, 0x0A, 0x8A, 0x1B, 0x17, 0x11, 0x2C, 0x76,
|
||||||
|
0x0C, 0x17, 0x0A, 0x8A, 0x67, 0x17, 0x0F, 0x84, 0x28, 0x17, 0x06, 0x34,
|
||||||
|
0x17, 0x17, 0x3A, 0x7E, 0x16, 0x40, 0x17, 0x0C, 0x8B, 0x1F, 0x17, 0x2A,
|
||||||
|
0x38, 0x1E, 0x17, 0x0A, 0x38, 0x17, 0x13, 0x81, 0x28, 0x00, 0xC0, 0x17,
|
||||||
|
0x17, 0x55, 0x46, 0x24, 0x17, 0x0A, 0x81, 0x28, 0x17, 0x14, 0x38, 0x17,
|
||||||
|
0x18, 0x81, 0x60, 0x46, 0x2C, 0x17, 0x06, 0x38, 0xEC, 0x17, 0x0D, 0x16,
|
||||||
|
0x17, 0x0E, 0x82, 0x3C, 0x17, 0x82, 0x0C, 0x8E, 0x68, 0x17, 0x04, 0x24,
|
||||||
|
0x17, 0x5C, 0x8E, 0x68, 0x17, 0x07, 0x82, 0x5F, 0x80, 0x17, 0x87, 0x01,
|
||||||
|
0x8E, 0x68, 0x02, 0x17, 0x81, 0x4A, 0x8E, 0x68, 0x17, 0x0C, 0x87, 0x78,
|
||||||
|
0x17, 0x85, 0x28, 0x8E, 0x68, 0x17, 0x8E, 0x68, 0x9D, 0x50, 0x17, 0x81,
|
||||||
|
0x24, 0x8E, 0x68, 0x17, 0x04, 0x2C, 0x17, 0x28, 0x8E, 0x68, 0x17, 0x04,
|
||||||
|
0x30, 0x17, 0x85, 0x3C, 0x8E, 0x68, 0x12, 0x17, 0x07, 0x85, 0x70, 0x17,
|
||||||
|
0x88, 0x74, 0x8E, 0x68, 0x17, 0x87, 0x3E, 0x9D, 0x50, 0x0C, 0x17, 0x04,
|
||||||
|
0x04, 0x17, 0x12, 0x8E, 0x68, 0x18, 0x17, 0x87, 0x12, 0xBB, 0x20, 0x17,
|
||||||
|
0x83, 0x04, 0x9D, 0x50, 0x15, 0x17, 0x05, 0x8D, 0x76, 0x17, 0x0F, 0x8B,
|
||||||
|
0x49, 0x17, 0x0B, 0x18, 0x32, 0x00, 0x2F, 0x00, 0x32, 0x00, 0x31, 0x00,
|
||||||
|
0x34, 0x00, 0x36, 0x00, 0x2F, 0x00, 0x33, 0x17, 0x09, 0x84, 0x0C, 0x17,
|
||||||
|
0x18, 0x18, 0x17, 0x20, 0x8E, 0x68, 0x15, 0x17, 0x07, 0x5A, 0x17, 0x06,
|
||||||
|
0x5E, 0x16, 0x00, 0x15, 0x17, 0x82, 0x40, 0x9D, 0x50, 0x17, 0x86, 0x5F,
|
||||||
|
0xBB, 0x20, 0x3A, 0x00, 0x00, 0x00, 0x1D, 0x17, 0x81, 0x4F, 0xAC, 0x38,
|
||||||
|
0x3B, 0x17, 0x04, 0x04, 0x17, 0x86, 0x30, 0x8E, 0x68, 0x17, 0x81, 0x53,
|
||||||
|
0xAC, 0x38, 0x07, 0x17, 0x0D, 0x8E, 0x68, 0xA3, 0x72, 0x17, 0x83, 0x10,
|
||||||
|
0x8E, 0x68
|
||||||
|
};
|
1126
source/mem/sdram_lp0.c
Normal file
1126
source/mem/sdram_lp0.c
Normal file
File diff suppressed because it is too large
Load Diff
964
source/mem/sdram_lp0_param_t210.h
Normal file
964
source/mem/sdram_lp0_param_t210.h
Normal file
@ -0,0 +1,964 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved.
|
||||||
|
* Copyright 2014 Google Inc.
|
||||||
|
* Copyright (C) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Defines the SDRAM parameter structure.
|
||||||
|
*
|
||||||
|
* Note that PLLM is used by EMC. The field names are in camel case to ease
|
||||||
|
* directly converting BCT config files (*.cfg) into C structure.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__
|
||||||
|
#define __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
/* Specifies the memory type to be undefined */
|
||||||
|
NvBootMemoryType_None = 0,
|
||||||
|
|
||||||
|
/* Specifies the memory type to be DDR SDRAM */
|
||||||
|
NvBootMemoryType_Ddr = 0,
|
||||||
|
|
||||||
|
/* Specifies the memory type to be LPDDR SDRAM */
|
||||||
|
NvBootMemoryType_LpDdr = 0,
|
||||||
|
|
||||||
|
/* Specifies the memory type to be DDR2 SDRAM */
|
||||||
|
NvBootMemoryType_Ddr2 = 0,
|
||||||
|
|
||||||
|
/* Specifies the memory type to be LPDDR2 SDRAM */
|
||||||
|
NvBootMemoryType_LpDdr2,
|
||||||
|
|
||||||
|
/* Specifies the memory type to be DDR3 SDRAM */
|
||||||
|
NvBootMemoryType_Ddr3,
|
||||||
|
|
||||||
|
/* Specifies the memory type to be LPDDR4 SDRAM */
|
||||||
|
NvBootMemoryType_LpDdr4,
|
||||||
|
|
||||||
|
NvBootMemoryType_Num,
|
||||||
|
|
||||||
|
/* Specifies an entry in the ram_code table that's not in use */
|
||||||
|
NvBootMemoryType_Unused = 0X7FFFFFF,
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Defines the SDRAM parameter structure
|
||||||
|
*/
|
||||||
|
struct sdram_params
|
||||||
|
{
|
||||||
|
|
||||||
|
/* Specifies the type of memory device */
|
||||||
|
u32 MemoryType;
|
||||||
|
|
||||||
|
/* MC/EMC clock source configuration */
|
||||||
|
|
||||||
|
/* Specifies the M value for PllM */
|
||||||
|
u32 PllMInputDivider;
|
||||||
|
/* Specifies the N value for PllM */
|
||||||
|
u32 PllMFeedbackDivider;
|
||||||
|
/* Specifies the time to wait for PLLM to lock (in microseconds) */
|
||||||
|
u32 PllMStableTime;
|
||||||
|
/* Specifies misc. control bits */
|
||||||
|
u32 PllMSetupControl;
|
||||||
|
/* Specifies the P value for PLLM */
|
||||||
|
u32 PllMPostDivider;
|
||||||
|
/* Specifies value for Charge Pump Gain Control */
|
||||||
|
u32 PllMKCP;
|
||||||
|
/* Specifies VCO gain */
|
||||||
|
u32 PllMKVCO;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 EmcBctSpare0;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 EmcBctSpare1;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 EmcBctSpare2;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 EmcBctSpare3;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 EmcBctSpare4;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 EmcBctSpare5;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 EmcBctSpare6;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 EmcBctSpare7;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 EmcBctSpare8;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 EmcBctSpare9;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 EmcBctSpare10;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 EmcBctSpare11;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 EmcBctSpare12;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 EmcBctSpare13;
|
||||||
|
|
||||||
|
/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
|
||||||
|
u32 EmcClockSource;
|
||||||
|
u32 EmcClockSourceDll;
|
||||||
|
|
||||||
|
/* Defines possible override for PLLLM_MISC2 */
|
||||||
|
u32 ClkRstControllerPllmMisc2Override;
|
||||||
|
/* enables override for PLLLM_MISC2 */
|
||||||
|
u32 ClkRstControllerPllmMisc2OverrideEnable;
|
||||||
|
/* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */
|
||||||
|
u32 ClearClk2Mc1;
|
||||||
|
|
||||||
|
/* Auto-calibration of EMC pads */
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
|
||||||
|
u32 EmcAutoCalInterval;
|
||||||
|
/*
|
||||||
|
* Specifies the value for EMC_AUTO_CAL_CONFIG
|
||||||
|
* Note: Trigger bits are set by the SDRAM code.
|
||||||
|
*/
|
||||||
|
u32 EmcAutoCalConfig;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
|
||||||
|
u32 EmcAutoCalConfig2;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
|
||||||
|
u32 EmcAutoCalConfig3;
|
||||||
|
|
||||||
|
/* Specifies the values for EMC_AUTO_CAL_CONFIG4-8 */
|
||||||
|
u32 EmcAutoCalConfig4;
|
||||||
|
u32 EmcAutoCalConfig5;
|
||||||
|
u32 EmcAutoCalConfig6;
|
||||||
|
u32 EmcAutoCalConfig7;
|
||||||
|
u32 EmcAutoCalConfig8;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */
|
||||||
|
u32 EmcAutoCalVrefSel0;
|
||||||
|
u32 EmcAutoCalVrefSel1;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_AUTO_CAL_CHANNEL */
|
||||||
|
u32 EmcAutoCalChannel;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */
|
||||||
|
u32 EmcPmacroAutocalCfg0;
|
||||||
|
u32 EmcPmacroAutocalCfg1;
|
||||||
|
u32 EmcPmacroAutocalCfg2;
|
||||||
|
u32 EmcPmacroRxTerm;
|
||||||
|
u32 EmcPmacroDqTxDrv;
|
||||||
|
u32 EmcPmacroCaTxDrv;
|
||||||
|
u32 EmcPmacroCmdTxDrv;
|
||||||
|
u32 EmcPmacroAutocalCfgCommon;
|
||||||
|
u32 EmcPmacroZctrl;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies the time for the calibration
|
||||||
|
* to stabilize (in microseconds)
|
||||||
|
*/
|
||||||
|
u32 EmcAutoCalWait;
|
||||||
|
|
||||||
|
u32 EmcXm2CompPadCtrl;
|
||||||
|
u32 EmcXm2CompPadCtrl2;
|
||||||
|
u32 EmcXm2CompPadCtrl3;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* DRAM size information
|
||||||
|
* Specifies the value for EMC_ADR_CFG
|
||||||
|
*/
|
||||||
|
u32 EmcAdrCfg;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies the time to wait after asserting pin
|
||||||
|
* CKE (in microseconds)
|
||||||
|
*/
|
||||||
|
u32 EmcPinProgramWait;
|
||||||
|
/* Specifies the extra delay before/after pin RESET/CKE command */
|
||||||
|
u32 EmcPinExtraWait;
|
||||||
|
|
||||||
|
u32 EmcPinGpioEn;
|
||||||
|
u32 EmcPinGpio;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies the extra delay after the first writing
|
||||||
|
* of EMC_TIMING_CONTROL
|
||||||
|
*/
|
||||||
|
u32 EmcTimingControlWait;
|
||||||
|
|
||||||
|
/* Timing parameters required for the SDRAM */
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_RC */
|
||||||
|
u32 EmcRc;
|
||||||
|
/* Specifies the value for EMC_RFC */
|
||||||
|
u32 EmcRfc;
|
||||||
|
/* Specifies the value for EMC_RFC_PB */
|
||||||
|
u32 EmcRfcPb;
|
||||||
|
/* Specifies the value for EMC_RFC_CTRL2 */
|
||||||
|
u32 EmcRefctrl2;
|
||||||
|
/* Specifies the value for EMC_RFC_SLR */
|
||||||
|
u32 EmcRfcSlr;
|
||||||
|
/* Specifies the value for EMC_RAS */
|
||||||
|
u32 EmcRas;
|
||||||
|
/* Specifies the value for EMC_RP */
|
||||||
|
u32 EmcRp;
|
||||||
|
/* Specifies the value for EMC_R2R */
|
||||||
|
u32 EmcR2r;
|
||||||
|
/* Specifies the value for EMC_W2W */
|
||||||
|
u32 EmcW2w;
|
||||||
|
/* Specifies the value for EMC_R2W */
|
||||||
|
u32 EmcR2w;
|
||||||
|
/* Specifies the value for EMC_W2R */
|
||||||
|
u32 EmcW2r;
|
||||||
|
/* Specifies the value for EMC_R2P */
|
||||||
|
u32 EmcR2p;
|
||||||
|
/* Specifies the value for EMC_W2P */
|
||||||
|
u32 EmcW2p;
|
||||||
|
|
||||||
|
u32 EmcTppd;
|
||||||
|
u32 EmcCcdmw;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_RD_RCD */
|
||||||
|
u32 EmcRdRcd;
|
||||||
|
/* Specifies the value for EMC_WR_RCD */
|
||||||
|
u32 EmcWrRcd;
|
||||||
|
/* Specifies the value for EMC_RRD */
|
||||||
|
u32 EmcRrd;
|
||||||
|
/* Specifies the value for EMC_REXT */
|
||||||
|
u32 EmcRext;
|
||||||
|
/* Specifies the value for EMC_WEXT */
|
||||||
|
u32 EmcWext;
|
||||||
|
/* Specifies the value for EMC_WDV */
|
||||||
|
u32 EmcWdv;
|
||||||
|
|
||||||
|
u32 EmcWdvChk;
|
||||||
|
u32 EmcWsv;
|
||||||
|
u32 EmcWev;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_WDV_MASK */
|
||||||
|
u32 EmcWdvMask;
|
||||||
|
|
||||||
|
u32 EmcWsDuration;
|
||||||
|
u32 EmcWeDuration;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_QUSE */
|
||||||
|
u32 EmcQUse;
|
||||||
|
/* Specifies the value for EMC_QUSE_WIDTH */
|
||||||
|
u32 EmcQuseWidth;
|
||||||
|
/* Specifies the value for EMC_IBDLY */
|
||||||
|
u32 EmcIbdly;
|
||||||
|
/* Specifies the value for EMC_OBDLY */
|
||||||
|
u32 EmcObdly;
|
||||||
|
/* Specifies the value for EMC_EINPUT */
|
||||||
|
u32 EmcEInput;
|
||||||
|
/* Specifies the value for EMC_EINPUT_DURATION */
|
||||||
|
u32 EmcEInputDuration;
|
||||||
|
/* Specifies the value for EMC_PUTERM_EXTRA */
|
||||||
|
u32 EmcPutermExtra;
|
||||||
|
/* Specifies the value for EMC_PUTERM_WIDTH */
|
||||||
|
u32 EmcPutermWidth;
|
||||||
|
/* Specifies the value for EMC_PUTERM_ADJ */
|
||||||
|
////u32 EmcPutermAdj;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_QRST */
|
||||||
|
u32 EmcQRst;
|
||||||
|
/* Specifies the value for EMC_QSAFE */
|
||||||
|
u32 EmcQSafe;
|
||||||
|
/* Specifies the value for EMC_RDV */
|
||||||
|
u32 EmcRdv;
|
||||||
|
/* Specifies the value for EMC_RDV_MASK */
|
||||||
|
u32 EmcRdvMask;
|
||||||
|
/* Specifies the value for EMC_RDV_EARLY */
|
||||||
|
u32 EmcRdvEarly;
|
||||||
|
/* Specifies the value for EMC_RDV_EARLY_MASK */
|
||||||
|
u32 EmcRdvEarlyMask;
|
||||||
|
/* Specifies the value for EMC_QPOP */
|
||||||
|
u32 EmcQpop;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_REFRESH */
|
||||||
|
u32 EmcRefresh;
|
||||||
|
/* Specifies the value for EMC_BURST_REFRESH_NUM */
|
||||||
|
u32 EmcBurstRefreshNum;
|
||||||
|
/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
|
||||||
|
u32 EmcPreRefreshReqCnt;
|
||||||
|
/* Specifies the value for EMC_PDEX2WR */
|
||||||
|
u32 EmcPdEx2Wr;
|
||||||
|
/* Specifies the value for EMC_PDEX2RD */
|
||||||
|
u32 EmcPdEx2Rd;
|
||||||
|
/* Specifies the value for EMC_PCHG2PDEN */
|
||||||
|
u32 EmcPChg2Pden;
|
||||||
|
/* Specifies the value for EMC_ACT2PDEN */
|
||||||
|
u32 EmcAct2Pden;
|
||||||
|
/* Specifies the value for EMC_AR2PDEN */
|
||||||
|
u32 EmcAr2Pden;
|
||||||
|
/* Specifies the value for EMC_RW2PDEN */
|
||||||
|
u32 EmcRw2Pden;
|
||||||
|
/* Specifies the value for EMC_CKE2PDEN */
|
||||||
|
u32 EmcCke2Pden;
|
||||||
|
/* Specifies the value for EMC_PDEX2CKE */
|
||||||
|
u32 EmcPdex2Cke;
|
||||||
|
/* Specifies the value for EMC_PDEX2MRR */
|
||||||
|
u32 EmcPdex2Mrr;
|
||||||
|
/* Specifies the value for EMC_TXSR */
|
||||||
|
u32 EmcTxsr;
|
||||||
|
/* Specifies the value for EMC_TXSRDLL */
|
||||||
|
u32 EmcTxsrDll;
|
||||||
|
/* Specifies the value for EMC_TCKE */
|
||||||
|
u32 EmcTcke;
|
||||||
|
/* Specifies the value for EMC_TCKESR */
|
||||||
|
u32 EmcTckesr;
|
||||||
|
/* Specifies the value for EMC_TPD */
|
||||||
|
u32 EmcTpd;
|
||||||
|
/* Specifies the value for EMC_TFAW */
|
||||||
|
u32 EmcTfaw;
|
||||||
|
/* Specifies the value for EMC_TRPAB */
|
||||||
|
u32 EmcTrpab;
|
||||||
|
/* Specifies the value for EMC_TCLKSTABLE */
|
||||||
|
u32 EmcTClkStable;
|
||||||
|
/* Specifies the value for EMC_TCLKSTOP */
|
||||||
|
u32 EmcTClkStop;
|
||||||
|
/* Specifies the value for EMC_TREFBW */
|
||||||
|
u32 EmcTRefBw;
|
||||||
|
|
||||||
|
/* FBIO configuration values */
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_FBIO_CFG5 */
|
||||||
|
u32 EmcFbioCfg5;
|
||||||
|
/* Specifies the value for EMC_FBIO_CFG7 */
|
||||||
|
u32 EmcFbioCfg7;
|
||||||
|
/* Specifies the value for EMC_FBIO_CFG8 */
|
||||||
|
u32 EmcFbioCfg8;
|
||||||
|
|
||||||
|
/* Command mapping for CMD brick 0 */
|
||||||
|
u32 EmcCmdMappingCmd0_0;
|
||||||
|
u32 EmcCmdMappingCmd0_1;
|
||||||
|
u32 EmcCmdMappingCmd0_2;
|
||||||
|
u32 EmcCmdMappingCmd1_0;
|
||||||
|
u32 EmcCmdMappingCmd1_1;
|
||||||
|
u32 EmcCmdMappingCmd1_2;
|
||||||
|
u32 EmcCmdMappingCmd2_0;
|
||||||
|
u32 EmcCmdMappingCmd2_1;
|
||||||
|
u32 EmcCmdMappingCmd2_2;
|
||||||
|
u32 EmcCmdMappingCmd3_0;
|
||||||
|
u32 EmcCmdMappingCmd3_1;
|
||||||
|
u32 EmcCmdMappingCmd3_2;
|
||||||
|
u32 EmcCmdMappingByte;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_FBIO_SPARE */
|
||||||
|
u32 EmcFbioSpare;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_CFG_RSV */
|
||||||
|
u32 EmcCfgRsv;
|
||||||
|
|
||||||
|
/* MRS command values */
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_MRS */
|
||||||
|
u32 EmcMrs;
|
||||||
|
/* Specifies the MP0 command to initialize mode registers */
|
||||||
|
u32 EmcEmrs;
|
||||||
|
/* Specifies the MP2 command to initialize mode registers */
|
||||||
|
u32 EmcEmrs2;
|
||||||
|
/* Specifies the MP3 command to initialize mode registers */
|
||||||
|
u32 EmcEmrs3;
|
||||||
|
/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
|
||||||
|
u32 EmcMrw1;
|
||||||
|
/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
|
||||||
|
u32 EmcMrw2;
|
||||||
|
/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
|
||||||
|
u32 EmcMrw3;
|
||||||
|
/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
|
||||||
|
u32 EmcMrw4;
|
||||||
|
/* Specifies the programming to LPDDR2 Mode Register 3? at cold boot */
|
||||||
|
u32 EmcMrw6;
|
||||||
|
/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
|
||||||
|
u32 EmcMrw8;
|
||||||
|
/* Specifies the programming to LPDDR2 Mode Register 11? at cold boot */
|
||||||
|
u32 EmcMrw9;
|
||||||
|
/* Specifies the programming to LPDDR2 Mode Register 12 at cold boot */
|
||||||
|
u32 EmcMrw10;
|
||||||
|
/* Specifies the programming to LPDDR2 Mode Register 14 at cold boot */
|
||||||
|
u32 EmcMrw12;
|
||||||
|
/* Specifies the programming to LPDDR2 Mode Register 14? at cold boot */
|
||||||
|
u32 EmcMrw13;
|
||||||
|
/* Specifies the programming to LPDDR2 Mode Register 22 at cold boot */
|
||||||
|
u32 EmcMrw14;
|
||||||
|
/*
|
||||||
|
* Specifies the programming to extra LPDDR2 Mode Register
|
||||||
|
* at cold boot
|
||||||
|
*/
|
||||||
|
u32 EmcMrwExtra;
|
||||||
|
/*
|
||||||
|
* Specifies the programming to extra LPDDR2 Mode Register
|
||||||
|
* at warm boot
|
||||||
|
*/
|
||||||
|
u32 EmcWarmBootMrwExtra;
|
||||||
|
/*
|
||||||
|
* Specify the enable of extra Mode Register programming at
|
||||||
|
* warm boot
|
||||||
|
*/
|
||||||
|
u32 EmcWarmBootExtraModeRegWriteEnable;
|
||||||
|
/*
|
||||||
|
* Specify the enable of extra Mode Register programming at
|
||||||
|
* cold boot
|
||||||
|
*/
|
||||||
|
u32 EmcExtraModeRegWriteEnable;
|
||||||
|
|
||||||
|
/* Specifies the EMC_MRW reset command value */
|
||||||
|
u32 EmcMrwResetCommand;
|
||||||
|
/* Specifies the EMC Reset wait time (in microseconds) */
|
||||||
|
u32 EmcMrwResetNInitWait;
|
||||||
|
/* Specifies the value for EMC_MRS_WAIT_CNT */
|
||||||
|
u32 EmcMrsWaitCnt;
|
||||||
|
/* Specifies the value for EMC_MRS_WAIT_CNT2 */
|
||||||
|
u32 EmcMrsWaitCnt2;
|
||||||
|
|
||||||
|
/* EMC miscellaneous configurations */
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_CFG */
|
||||||
|
u32 EmcCfg;
|
||||||
|
/* Specifies the value for EMC_CFG_2 */
|
||||||
|
u32 EmcCfg2;
|
||||||
|
/* Specifies the pipe bypass controls */
|
||||||
|
u32 EmcCfgPipe;
|
||||||
|
u32 EmcCfgPipeClk;
|
||||||
|
u32 EmcFdpdCtrlCmdNoRamp;
|
||||||
|
u32 EmcCfgUpdate;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_DBG */
|
||||||
|
u32 EmcDbg;
|
||||||
|
u32 EmcDbgWriteMux;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_CMDQ */
|
||||||
|
u32 EmcCmdQ;
|
||||||
|
/* Specifies the value for EMC_MC2EMCQ */
|
||||||
|
u32 EmcMc2EmcQ;
|
||||||
|
/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
|
||||||
|
u32 EmcDynSelfRefControl;
|
||||||
|
|
||||||
|
/* Specifies the value for MEM_INIT_DONE */
|
||||||
|
u32 AhbArbitrationXbarCtrlMemInitDone;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_CFG_DIG_DLL */
|
||||||
|
u32 EmcCfgDigDll;
|
||||||
|
u32 EmcCfgDigDll_1;
|
||||||
|
/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
|
||||||
|
u32 EmcCfgDigDllPeriod;
|
||||||
|
/* Specifies the value of *DEV_SELECTN of various EMC registers */
|
||||||
|
u32 EmcDevSelect;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_SEL_DPD_CTRL */
|
||||||
|
u32 EmcSelDpdCtrl;
|
||||||
|
|
||||||
|
/* Pads trimmer delays */
|
||||||
|
u32 EmcFdpdCtrlDq;
|
||||||
|
u32 EmcFdpdCtrlCmd;
|
||||||
|
u32 EmcPmacroIbVrefDq_0;
|
||||||
|
u32 EmcPmacroIbVrefDq_1;
|
||||||
|
u32 EmcPmacroIbVrefDqs_0;
|
||||||
|
u32 EmcPmacroIbVrefDqs_1;
|
||||||
|
u32 EmcPmacroIbRxrt;
|
||||||
|
u32 EmcCfgPipe1;
|
||||||
|
u32 EmcCfgPipe2;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */
|
||||||
|
u32 EmcPmacroQuseDdllRank0_0;
|
||||||
|
u32 EmcPmacroQuseDdllRank0_1;
|
||||||
|
u32 EmcPmacroQuseDdllRank0_2;
|
||||||
|
u32 EmcPmacroQuseDdllRank0_3;
|
||||||
|
u32 EmcPmacroQuseDdllRank0_4;
|
||||||
|
u32 EmcPmacroQuseDdllRank0_5;
|
||||||
|
u32 EmcPmacroQuseDdllRank1_0;
|
||||||
|
u32 EmcPmacroQuseDdllRank1_1;
|
||||||
|
u32 EmcPmacroQuseDdllRank1_2;
|
||||||
|
u32 EmcPmacroQuseDdllRank1_3;
|
||||||
|
u32 EmcPmacroQuseDdllRank1_4;
|
||||||
|
u32 EmcPmacroQuseDdllRank1_5;
|
||||||
|
|
||||||
|
u32 EmcPmacroObDdllLongDqRank0_0;
|
||||||
|
u32 EmcPmacroObDdllLongDqRank0_1;
|
||||||
|
u32 EmcPmacroObDdllLongDqRank0_2;
|
||||||
|
u32 EmcPmacroObDdllLongDqRank0_3;
|
||||||
|
u32 EmcPmacroObDdllLongDqRank0_4;
|
||||||
|
u32 EmcPmacroObDdllLongDqRank0_5;
|
||||||
|
u32 EmcPmacroObDdllLongDqRank1_0;
|
||||||
|
u32 EmcPmacroObDdllLongDqRank1_1;
|
||||||
|
u32 EmcPmacroObDdllLongDqRank1_2;
|
||||||
|
u32 EmcPmacroObDdllLongDqRank1_3;
|
||||||
|
u32 EmcPmacroObDdllLongDqRank1_4;
|
||||||
|
u32 EmcPmacroObDdllLongDqRank1_5;
|
||||||
|
|
||||||
|
u32 EmcPmacroObDdllLongDqsRank0_0;
|
||||||
|
u32 EmcPmacroObDdllLongDqsRank0_1;
|
||||||
|
u32 EmcPmacroObDdllLongDqsRank0_2;
|
||||||
|
u32 EmcPmacroObDdllLongDqsRank0_3;
|
||||||
|
u32 EmcPmacroObDdllLongDqsRank0_4;
|
||||||
|
u32 EmcPmacroObDdllLongDqsRank0_5;
|
||||||
|
u32 EmcPmacroObDdllLongDqsRank1_0;
|
||||||
|
u32 EmcPmacroObDdllLongDqsRank1_1;
|
||||||
|
u32 EmcPmacroObDdllLongDqsRank1_2;
|
||||||
|
u32 EmcPmacroObDdllLongDqsRank1_3;
|
||||||
|
u32 EmcPmacroObDdllLongDqsRank1_4;
|
||||||
|
u32 EmcPmacroObDdllLongDqsRank1_5;
|
||||||
|
|
||||||
|
u32 EmcPmacroIbDdllLongDqsRank0_0;
|
||||||
|
u32 EmcPmacroIbDdllLongDqsRank0_1;
|
||||||
|
u32 EmcPmacroIbDdllLongDqsRank0_2;
|
||||||
|
u32 EmcPmacroIbDdllLongDqsRank0_3;
|
||||||
|
u32 EmcPmacroIbDdllLongDqsRank1_0;
|
||||||
|
u32 EmcPmacroIbDdllLongDqsRank1_1;
|
||||||
|
u32 EmcPmacroIbDdllLongDqsRank1_2;
|
||||||
|
u32 EmcPmacroIbDdllLongDqsRank1_3;
|
||||||
|
|
||||||
|
u32 EmcPmacroDdllLongCmd_0;
|
||||||
|
u32 EmcPmacroDdllLongCmd_1;
|
||||||
|
u32 EmcPmacroDdllLongCmd_2;
|
||||||
|
u32 EmcPmacroDdllLongCmd_3;
|
||||||
|
u32 EmcPmacroDdllLongCmd_4;
|
||||||
|
u32 EmcPmacroDdllShortCmd_0;
|
||||||
|
u32 EmcPmacroDdllShortCmd_1;
|
||||||
|
u32 EmcPmacroDdllShortCmd_2;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies the delay after asserting CKE pin during a WarmBoot0
|
||||||
|
* sequence (in microseconds)
|
||||||
|
*/
|
||||||
|
u32 WarmBootWait;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_ODT_WRITE */
|
||||||
|
u32 EmcOdtWrite;
|
||||||
|
|
||||||
|
/* Periodic ZQ calibration */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies the value for EMC_ZCAL_INTERVAL
|
||||||
|
* Value 0 disables ZQ calibration
|
||||||
|
*/
|
||||||
|
u32 EmcZcalInterval;
|
||||||
|
/* Specifies the value for EMC_ZCAL_WAIT_CNT */
|
||||||
|
u32 EmcZcalWaitCnt;
|
||||||
|
/* Specifies the value for EMC_ZCAL_MRW_CMD */
|
||||||
|
u32 EmcZcalMrwCmd;
|
||||||
|
|
||||||
|
/* DRAM initialization sequence flow control */
|
||||||
|
|
||||||
|
/* Specifies the MRS command value for resetting DLL */
|
||||||
|
u32 EmcMrsResetDll;
|
||||||
|
/* Specifies the command for ZQ initialization of device 0 */
|
||||||
|
u32 EmcZcalInitDev0;
|
||||||
|
/* Specifies the command for ZQ initialization of device 1 */
|
||||||
|
u32 EmcZcalInitDev1;
|
||||||
|
/*
|
||||||
|
* Specifies the wait time after programming a ZQ initialization
|
||||||
|
* command (in microseconds)
|
||||||
|
*/
|
||||||
|
u32 EmcZcalInitWait;
|
||||||
|
/*
|
||||||
|
* Specifies the enable for ZQ calibration at cold boot [bit 0]
|
||||||
|
* and warm boot [bit 1]
|
||||||
|
*/
|
||||||
|
u32 EmcZcalWarmColdBootEnables;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies the MRW command to LPDDR2 for ZQ calibration
|
||||||
|
* on warmboot
|
||||||
|
*/
|
||||||
|
/* Is issued to both devices separately */
|
||||||
|
u32 EmcMrwLpddr2ZcalWarmBoot;
|
||||||
|
/*
|
||||||
|
* Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
|
||||||
|
* Is issued to both devices separately
|
||||||
|
*/
|
||||||
|
u32 EmcZqCalDdr3WarmBoot;
|
||||||
|
u32 EmcZqCalLpDdr4WarmBoot;
|
||||||
|
/*
|
||||||
|
* Specifies the wait time for ZQ calibration on warmboot
|
||||||
|
* (in microseconds)
|
||||||
|
*/
|
||||||
|
u32 EmcZcalWarmBootWait;
|
||||||
|
/*
|
||||||
|
* Specifies the enable for DRAM Mode Register programming
|
||||||
|
* at warm boot
|
||||||
|
*/
|
||||||
|
u32 EmcMrsWarmBootEnable;
|
||||||
|
/*
|
||||||
|
* Specifies the wait time after sending an MRS DLL reset command
|
||||||
|
* in microseconds)
|
||||||
|
*/
|
||||||
|
u32 EmcMrsResetDllWait;
|
||||||
|
/* Specifies the extra MRS command to initialize mode registers */
|
||||||
|
u32 EmcMrsExtra;
|
||||||
|
/* Specifies the extra MRS command at warm boot */
|
||||||
|
u32 EmcWarmBootMrsExtra;
|
||||||
|
/* Specifies the EMRS command to enable the DDR2 DLL */
|
||||||
|
u32 EmcEmrsDdr2DllEnable;
|
||||||
|
/* Specifies the MRS command to reset the DDR2 DLL */
|
||||||
|
u32 EmcMrsDdr2DllReset;
|
||||||
|
/* Specifies the EMRS command to set OCD calibration */
|
||||||
|
u32 EmcEmrsDdr2OcdCalib;
|
||||||
|
/*
|
||||||
|
* Specifies the wait between initializing DDR and setting OCD
|
||||||
|
* calibration (in microseconds)
|
||||||
|
*/
|
||||||
|
u32 EmcDdr2Wait;
|
||||||
|
/* Specifies the value for EMC_CLKEN_OVERRIDE */
|
||||||
|
u32 EmcClkenOverride;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies LOG2 of the extra refresh numbers after booting
|
||||||
|
* Program 0 to disable
|
||||||
|
*/
|
||||||
|
u32 EmcExtraRefreshNum;
|
||||||
|
/* Specifies the master override for all EMC clocks */
|
||||||
|
u32 EmcClkenOverrideAllWarmBoot;
|
||||||
|
/* Specifies the master override for all MC clocks */
|
||||||
|
u32 McClkenOverrideAllWarmBoot;
|
||||||
|
/* Specifies digital dll period, choosing between 4 to 64 ms */
|
||||||
|
u32 EmcCfgDigDllPeriodWarmBoot;
|
||||||
|
|
||||||
|
/* Pad controls */
|
||||||
|
|
||||||
|
/* Specifies the value for PMC_VDDP_SEL */
|
||||||
|
u32 PmcVddpSel;
|
||||||
|
/* Specifies the wait time after programming PMC_VDDP_SEL */
|
||||||
|
u32 PmcVddpSelWait;
|
||||||
|
/* Specifies the value for PMC_DDR_PWR */
|
||||||
|
u32 PmcDdrPwr;
|
||||||
|
/* Specifies the value for PMC_DDR_CFG */
|
||||||
|
u32 PmcDdrCfg;
|
||||||
|
/* Specifies the value for PMC_IO_DPD3_REQ */
|
||||||
|
u32 PmcIoDpd3Req;
|
||||||
|
/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
|
||||||
|
u32 PmcIoDpd3ReqWait;
|
||||||
|
u32 PmcIoDpd4ReqWait;
|
||||||
|
|
||||||
|
/* Specifies the value for PMC_REG_SHORT */
|
||||||
|
u32 PmcRegShort;
|
||||||
|
/* Specifies the value for PMC_NO_IOPOWER */
|
||||||
|
u32 PmcNoIoPower;
|
||||||
|
|
||||||
|
u32 PmcDdrCntrlWait;
|
||||||
|
u32 PmcDdrCntrl;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_ACPD_CONTROL */
|
||||||
|
u32 EmcAcpdControl;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */
|
||||||
|
////u32 EmcSwizzleRank0ByteCfg;
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
|
||||||
|
u32 EmcSwizzleRank0Byte0;
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
|
||||||
|
u32 EmcSwizzleRank0Byte1;
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
|
||||||
|
u32 EmcSwizzleRank0Byte2;
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
|
||||||
|
u32 EmcSwizzleRank0Byte3;
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */
|
||||||
|
////u32 EmcSwizzleRank1ByteCfg;
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
|
||||||
|
u32 EmcSwizzleRank1Byte0;
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
|
||||||
|
u32 EmcSwizzleRank1Byte1;
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
|
||||||
|
u32 EmcSwizzleRank1Byte2;
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
|
||||||
|
u32 EmcSwizzleRank1Byte3;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_TXDSRVTTGEN */
|
||||||
|
u32 EmcTxdsrvttgen;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_DATA_BRLSHFT_0 */
|
||||||
|
u32 EmcDataBrlshft0;
|
||||||
|
u32 EmcDataBrlshft1;
|
||||||
|
|
||||||
|
u32 EmcDqsBrlshft0;
|
||||||
|
u32 EmcDqsBrlshft1;
|
||||||
|
|
||||||
|
u32 EmcCmdBrlshft0;
|
||||||
|
u32 EmcCmdBrlshft1;
|
||||||
|
u32 EmcCmdBrlshft2;
|
||||||
|
u32 EmcCmdBrlshft3;
|
||||||
|
|
||||||
|
u32 EmcQuseBrlshft0;
|
||||||
|
u32 EmcQuseBrlshft1;
|
||||||
|
u32 EmcQuseBrlshft2;
|
||||||
|
u32 EmcQuseBrlshft3;
|
||||||
|
|
||||||
|
u32 EmcDllCfg0;
|
||||||
|
u32 EmcDllCfg1;
|
||||||
|
|
||||||
|
u32 EmcPmcScratch1;
|
||||||
|
u32 EmcPmcScratch2;
|
||||||
|
u32 EmcPmcScratch3;
|
||||||
|
|
||||||
|
u32 EmcPmacroPadCfgCtrl;
|
||||||
|
|
||||||
|
u32 EmcPmacroVttgenCtrl0;
|
||||||
|
u32 EmcPmacroVttgenCtrl1;
|
||||||
|
u32 EmcPmacroVttgenCtrl2;
|
||||||
|
|
||||||
|
u32 EmcPmacroBrickCtrlRfu1;
|
||||||
|
u32 EmcPmacroCmdBrickCtrlFdpd;
|
||||||
|
u32 EmcPmacroBrickCtrlRfu2;
|
||||||
|
u32 EmcPmacroDataBrickCtrlFdpd;
|
||||||
|
u32 EmcPmacroBgBiasCtrl0;
|
||||||
|
u32 EmcPmacroDataPadRxCtrl;
|
||||||
|
u32 EmcPmacroCmdPadRxCtrl;
|
||||||
|
u32 EmcPmacroDataRxTermMode;
|
||||||
|
u32 EmcPmacroCmdRxTermMode;
|
||||||
|
u32 EmcPmacroDataPadTxCtrl;
|
||||||
|
u32 EmcPmacroCommonPadTxCtrl;
|
||||||
|
u32 EmcPmacroCmdPadTxCtrl;
|
||||||
|
u32 EmcCfg3;
|
||||||
|
|
||||||
|
u32 EmcPmacroTxPwrd0;
|
||||||
|
u32 EmcPmacroTxPwrd1;
|
||||||
|
u32 EmcPmacroTxPwrd2;
|
||||||
|
u32 EmcPmacroTxPwrd3;
|
||||||
|
u32 EmcPmacroTxPwrd4;
|
||||||
|
u32 EmcPmacroTxPwrd5;
|
||||||
|
|
||||||
|
u32 EmcConfigSampleDelay;
|
||||||
|
|
||||||
|
u32 EmcPmacroBrickMapping0;
|
||||||
|
u32 EmcPmacroBrickMapping1;
|
||||||
|
u32 EmcPmacroBrickMapping2;
|
||||||
|
|
||||||
|
u32 EmcPmacroTxSelClkSrc0;
|
||||||
|
u32 EmcPmacroTxSelClkSrc1;
|
||||||
|
u32 EmcPmacroTxSelClkSrc2;
|
||||||
|
u32 EmcPmacroTxSelClkSrc3;
|
||||||
|
u32 EmcPmacroTxSelClkSrc4;
|
||||||
|
u32 EmcPmacroTxSelClkSrc5;
|
||||||
|
|
||||||
|
u32 EmcPmacroDdllBypass;
|
||||||
|
|
||||||
|
u32 EmcPmacroDdllPwrd0;
|
||||||
|
u32 EmcPmacroDdllPwrd1;
|
||||||
|
u32 EmcPmacroDdllPwrd2;
|
||||||
|
|
||||||
|
u32 EmcPmacroCmdCtrl0;
|
||||||
|
u32 EmcPmacroCmdCtrl1;
|
||||||
|
u32 EmcPmacroCmdCtrl2;
|
||||||
|
|
||||||
|
/* DRAM size information */
|
||||||
|
|
||||||
|
/* Specifies the value for MC_EMEM_ADR_CFG */
|
||||||
|
u32 McEmemAdrCfg;
|
||||||
|
/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
|
||||||
|
u32 McEmemAdrCfgDev0;
|
||||||
|
/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
|
||||||
|
u32 McEmemAdrCfgDev1;
|
||||||
|
u32 McEmemAdrCfgChannelMask;
|
||||||
|
|
||||||
|
/* Specifies the value for MC_EMEM_BANK_SWIZZLECfg0 */
|
||||||
|
u32 McEmemAdrCfgBankMask0;
|
||||||
|
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
|
||||||
|
u32 McEmemAdrCfgBankMask1;
|
||||||
|
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
|
||||||
|
u32 McEmemAdrCfgBankMask2;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies the value for MC_EMEM_CFG which holds the external memory
|
||||||
|
* size (in KBytes)
|
||||||
|
*/
|
||||||
|
u32 McEmemCfg;
|
||||||
|
|
||||||
|
/* MC arbitration configuration */
|
||||||
|
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_CFG */
|
||||||
|
u32 McEmemArbCfg;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
|
||||||
|
u32 McEmemArbOutstandingReq;
|
||||||
|
|
||||||
|
u32 McEmemArbRefpbHpCtrl;
|
||||||
|
u32 McEmemArbRefpbBankCtrl;
|
||||||
|
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
|
||||||
|
u32 McEmemArbTimingRcd;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
|
||||||
|
u32 McEmemArbTimingRp;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
|
||||||
|
u32 McEmemArbTimingRc;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
|
||||||
|
u32 McEmemArbTimingRas;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
|
||||||
|
u32 McEmemArbTimingFaw;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
|
||||||
|
u32 McEmemArbTimingRrd;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
|
||||||
|
u32 McEmemArbTimingRap2Pre;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
|
||||||
|
u32 McEmemArbTimingWap2Pre;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
|
||||||
|
u32 McEmemArbTimingR2R;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
|
||||||
|
u32 McEmemArbTimingW2W;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
|
||||||
|
u32 McEmemArbTimingR2W;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
|
||||||
|
u32 McEmemArbTimingW2R;
|
||||||
|
|
||||||
|
u32 McEmemArbTimingRFCPB;
|
||||||
|
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
|
||||||
|
u32 McEmemArbDaTurns;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
|
||||||
|
u32 McEmemArbDaCovers;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_MISC0 */
|
||||||
|
u32 McEmemArbMisc0;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_MISC1 */
|
||||||
|
u32 McEmemArbMisc1;
|
||||||
|
u32 McEmemArbMisc2;
|
||||||
|
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
|
||||||
|
u32 McEmemArbRing1Throttle;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
|
||||||
|
u32 McEmemArbOverride;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
|
||||||
|
u32 McEmemArbOverride1;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_RSV */
|
||||||
|
u32 McEmemArbRsv;
|
||||||
|
|
||||||
|
u32 McDaCfg0;
|
||||||
|
u32 McEmemArbTimingCcdmw;
|
||||||
|
|
||||||
|
/* Specifies the value for MC_CLKEN_OVERRIDE */
|
||||||
|
u32 McClkenOverride;
|
||||||
|
|
||||||
|
/* Specifies the value for MC_STAT_CONTROL */
|
||||||
|
u32 McStatControl;
|
||||||
|
|
||||||
|
/* Specifies the value for MC_VIDEO_PROTECT_BOM */
|
||||||
|
u32 McVideoProtectBom;
|
||||||
|
/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
|
||||||
|
u32 McVideoProtectBomAdrHi;
|
||||||
|
/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
|
||||||
|
u32 McVideoProtectSizeMb;
|
||||||
|
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
|
||||||
|
u32 McVideoProtectVprOverride;
|
||||||
|
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
|
||||||
|
u32 McVideoProtectVprOverride1;
|
||||||
|
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
|
||||||
|
u32 McVideoProtectGpuOverride0;
|
||||||
|
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
|
||||||
|
u32 McVideoProtectGpuOverride1;
|
||||||
|
/* Specifies the value for MC_SEC_CARVEOUT_BOM */
|
||||||
|
u32 McSecCarveoutBom;
|
||||||
|
/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
|
||||||
|
u32 McSecCarveoutAdrHi;
|
||||||
|
/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
|
||||||
|
u32 McSecCarveoutSizeMb;
|
||||||
|
/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.
|
||||||
|
VIDEO_PROTECT_WRITEAccess */
|
||||||
|
u32 McVideoProtectWriteAccess;
|
||||||
|
/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.
|
||||||
|
SEC_CARVEOUT_WRITEAccess */
|
||||||
|
u32 McSecCarveoutProtectWriteAccess;
|
||||||
|
|
||||||
|
/* Write-Protect Regions (WPR) */
|
||||||
|
u32 McGeneralizedCarveout1Bom;
|
||||||
|
u32 McGeneralizedCarveout1BomHi;
|
||||||
|
u32 McGeneralizedCarveout1Size128kb;
|
||||||
|
u32 McGeneralizedCarveout1Access0;
|
||||||
|
u32 McGeneralizedCarveout1Access1;
|
||||||
|
u32 McGeneralizedCarveout1Access2;
|
||||||
|
u32 McGeneralizedCarveout1Access3;
|
||||||
|
u32 McGeneralizedCarveout1Access4;
|
||||||
|
u32 McGeneralizedCarveout1ForceInternalAccess0;
|
||||||
|
u32 McGeneralizedCarveout1ForceInternalAccess1;
|
||||||
|
u32 McGeneralizedCarveout1ForceInternalAccess2;
|
||||||
|
u32 McGeneralizedCarveout1ForceInternalAccess3;
|
||||||
|
u32 McGeneralizedCarveout1ForceInternalAccess4;
|
||||||
|
u32 McGeneralizedCarveout1Cfg0;
|
||||||
|
|
||||||
|
u32 McGeneralizedCarveout2Bom;
|
||||||
|
u32 McGeneralizedCarveout2BomHi;
|
||||||
|
u32 McGeneralizedCarveout2Size128kb;
|
||||||
|
u32 McGeneralizedCarveout2Access0;
|
||||||
|
u32 McGeneralizedCarveout2Access1;
|
||||||
|
u32 McGeneralizedCarveout2Access2;
|
||||||
|
u32 McGeneralizedCarveout2Access3;
|
||||||
|
u32 McGeneralizedCarveout2Access4;
|
||||||
|
u32 McGeneralizedCarveout2ForceInternalAccess0;
|
||||||
|
u32 McGeneralizedCarveout2ForceInternalAccess1;
|
||||||
|
u32 McGeneralizedCarveout2ForceInternalAccess2;
|
||||||
|
u32 McGeneralizedCarveout2ForceInternalAccess3;
|
||||||
|
u32 McGeneralizedCarveout2ForceInternalAccess4;
|
||||||
|
u32 McGeneralizedCarveout2Cfg0;
|
||||||
|
|
||||||
|
u32 McGeneralizedCarveout3Bom;
|
||||||
|
u32 McGeneralizedCarveout3BomHi;
|
||||||
|
u32 McGeneralizedCarveout3Size128kb;
|
||||||
|
u32 McGeneralizedCarveout3Access0;
|
||||||
|
u32 McGeneralizedCarveout3Access1;
|
||||||
|
u32 McGeneralizedCarveout3Access2;
|
||||||
|
u32 McGeneralizedCarveout3Access3;
|
||||||
|
u32 McGeneralizedCarveout3Access4;
|
||||||
|
u32 McGeneralizedCarveout3ForceInternalAccess0;
|
||||||
|
u32 McGeneralizedCarveout3ForceInternalAccess1;
|
||||||
|
u32 McGeneralizedCarveout3ForceInternalAccess2;
|
||||||
|
u32 McGeneralizedCarveout3ForceInternalAccess3;
|
||||||
|
u32 McGeneralizedCarveout3ForceInternalAccess4;
|
||||||
|
u32 McGeneralizedCarveout3Cfg0;
|
||||||
|
|
||||||
|
u32 McGeneralizedCarveout4Bom;
|
||||||
|
u32 McGeneralizedCarveout4BomHi;
|
||||||
|
u32 McGeneralizedCarveout4Size128kb;
|
||||||
|
u32 McGeneralizedCarveout4Access0;
|
||||||
|
u32 McGeneralizedCarveout4Access1;
|
||||||
|
u32 McGeneralizedCarveout4Access2;
|
||||||
|
u32 McGeneralizedCarveout4Access3;
|
||||||
|
u32 McGeneralizedCarveout4Access4;
|
||||||
|
u32 McGeneralizedCarveout4ForceInternalAccess0;
|
||||||
|
u32 McGeneralizedCarveout4ForceInternalAccess1;
|
||||||
|
u32 McGeneralizedCarveout4ForceInternalAccess2;
|
||||||
|
u32 McGeneralizedCarveout4ForceInternalAccess3;
|
||||||
|
u32 McGeneralizedCarveout4ForceInternalAccess4;
|
||||||
|
u32 McGeneralizedCarveout4Cfg0;
|
||||||
|
|
||||||
|
u32 McGeneralizedCarveout5Bom;
|
||||||
|
u32 McGeneralizedCarveout5BomHi;
|
||||||
|
u32 McGeneralizedCarveout5Size128kb;
|
||||||
|
u32 McGeneralizedCarveout5Access0;
|
||||||
|
u32 McGeneralizedCarveout5Access1;
|
||||||
|
u32 McGeneralizedCarveout5Access2;
|
||||||
|
u32 McGeneralizedCarveout5Access3;
|
||||||
|
u32 McGeneralizedCarveout5Access4;
|
||||||
|
u32 McGeneralizedCarveout5ForceInternalAccess0;
|
||||||
|
u32 McGeneralizedCarveout5ForceInternalAccess1;
|
||||||
|
u32 McGeneralizedCarveout5ForceInternalAccess2;
|
||||||
|
u32 McGeneralizedCarveout5ForceInternalAccess3;
|
||||||
|
u32 McGeneralizedCarveout5ForceInternalAccess4;
|
||||||
|
u32 McGeneralizedCarveout5Cfg0;
|
||||||
|
|
||||||
|
/* Specifies enable for CA training */
|
||||||
|
u32 EmcCaTrainingEnable;
|
||||||
|
|
||||||
|
/* Set if bit 6 select is greater than bit 7 select; uses aremc.
|
||||||
|
spec packet SWIZZLE_BIT6_GT_BIT7 */
|
||||||
|
u32 SwizzleRankByteEncode;
|
||||||
|
/* Specifies enable and offset for patched boot ROM write */
|
||||||
|
u32 BootRomPatchControl;
|
||||||
|
/* Specifies data for patched boot ROM write */
|
||||||
|
u32 BootRomPatchData;
|
||||||
|
|
||||||
|
/* Specifies the value for MC_MTS_CARVEOUT_BOM */
|
||||||
|
u32 McMtsCarveoutBom;
|
||||||
|
/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
|
||||||
|
u32 McMtsCarveoutAdrHi;
|
||||||
|
/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
|
||||||
|
u32 McMtsCarveoutSizeMb;
|
||||||
|
/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
|
||||||
|
u32 McMtsCarveoutRegCtrl;
|
||||||
|
|
||||||
|
/* End */
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ */
|
931
source/mem/sdram_param_t210.h
Normal file
931
source/mem/sdram_param_t210.h
Normal file
@ -0,0 +1,931 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Defines the SDRAM parameter structure.
|
||||||
|
*
|
||||||
|
* Note that PLLM is used by EMC.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _SDRAM_PARAM_T210_H_
|
||||||
|
#define _SDRAM_PARAM_T210_H_
|
||||||
|
|
||||||
|
#define MEMORY_TYPE_NONE 0
|
||||||
|
#define MEMORY_TYPE_DDR 0
|
||||||
|
#define MEMORY_TYPE_LPDDR 0
|
||||||
|
#define MEMORY_TYPE_DDR2 0
|
||||||
|
#define MEMORY_TYPE_LPDDR2 1
|
||||||
|
#define MEMORY_TYPE_DDR3 2
|
||||||
|
#define MEMORY_TYPE_LPDDR4 3
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Defines the SDRAM parameter structure
|
||||||
|
*/
|
||||||
|
typedef struct _sdram_params
|
||||||
|
{
|
||||||
|
/* Specifies the type of memory device */
|
||||||
|
u32 memory_type;
|
||||||
|
|
||||||
|
/* MC/EMC clock source configuration */
|
||||||
|
|
||||||
|
/* Specifies the M value for PllM */
|
||||||
|
u32 pllm_input_divider;
|
||||||
|
/* Specifies the N value for PllM */
|
||||||
|
u32 pllm_feedback_divider;
|
||||||
|
/* Specifies the time to wait for PLLM to lock (in microseconds) */
|
||||||
|
u32 pllm_stable_time;
|
||||||
|
/* Specifies misc. control bits */
|
||||||
|
u32 pllm_setup_control;
|
||||||
|
/* Specifies the P value for PLLM */
|
||||||
|
u32 pllm_post_divider;
|
||||||
|
/* Specifies value for Charge Pump Gain Control */
|
||||||
|
u32 pllm_kcp;
|
||||||
|
/* Specifies VCO gain */
|
||||||
|
u32 pllm_kvco;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 emc_bct_spare0;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 emc_bct_spare1;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 emc_bct_spare2;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 emc_bct_spare3;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 emc_bct_spare4;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 emc_bct_spare5;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 emc_bct_spare6;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 emc_bct_spare7;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 emc_bct_spare8;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 emc_bct_spare9;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 emc_bct_spare10;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 emc_bct_spare11;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 emc_bct_spare12;
|
||||||
|
/* Spare BCT param */
|
||||||
|
u32 emc_bct_spare13;
|
||||||
|
|
||||||
|
/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
|
||||||
|
u32 emc_clock_source;
|
||||||
|
u32 emc_clock_source_dll;
|
||||||
|
|
||||||
|
/* Defines possible override for PLLLM_MISC2 */
|
||||||
|
u32 clk_rst_pllm_misc20_override;
|
||||||
|
/* enables override for PLLLM_MISC2 */
|
||||||
|
u32 clk_rst_pllm_misc20_override_enable;
|
||||||
|
/* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */
|
||||||
|
u32 clear_clock2_mc1;
|
||||||
|
|
||||||
|
/* Auto-calibration of EMC pads */
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
|
||||||
|
u32 emc_auto_cal_interval;
|
||||||
|
/*
|
||||||
|
* Specifies the value for EMC_AUTO_CAL_CONFIG
|
||||||
|
* Note: Trigger bits are set by the SDRAM code.
|
||||||
|
*/
|
||||||
|
u32 emc_auto_cal_config;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
|
||||||
|
u32 emc_auto_cal_config2;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
|
||||||
|
u32 emc_auto_cal_config3;
|
||||||
|
|
||||||
|
u32 emc_auto_cal_config4;
|
||||||
|
u32 emc_auto_cal_config5;
|
||||||
|
u32 emc_auto_cal_config6;
|
||||||
|
u32 emc_auto_cal_config7;
|
||||||
|
u32 emc_auto_cal_config8;
|
||||||
|
/* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */
|
||||||
|
u32 emc_auto_cal_vref_sel0;
|
||||||
|
u32 emc_auto_cal_vref_sel1;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_AUTO_CAL_CHANNEL */
|
||||||
|
u32 emc_auto_cal_channel;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */
|
||||||
|
u32 emc_pmacro_auto_cal_cfg0;
|
||||||
|
u32 emc_pmacro_auto_cal_cfg1;
|
||||||
|
u32 emc_pmacro_auto_cal_cfg2;
|
||||||
|
|
||||||
|
u32 emc_pmacro_rx_term;
|
||||||
|
u32 emc_pmacro_dq_tx_drive;
|
||||||
|
u32 emc_pmacro_ca_tx_drive;
|
||||||
|
u32 emc_pmacro_cmd_tx_drive;
|
||||||
|
u32 emc_pmacro_auto_cal_common;
|
||||||
|
u32 emc_pmacro_zcrtl;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies the time for the calibration
|
||||||
|
* to stabilize (in microseconds)
|
||||||
|
*/
|
||||||
|
u32 emc_auto_cal_wait;
|
||||||
|
|
||||||
|
u32 emc_xm2_comp_pad_ctrl;
|
||||||
|
u32 emc_xm2_comp_pad_ctrl2;
|
||||||
|
u32 emc_xm2_comp_pad_ctrl3;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* DRAM size information
|
||||||
|
* Specifies the value for EMC_ADR_CFG
|
||||||
|
*/
|
||||||
|
u32 emc_adr_cfg;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies the time to wait after asserting pin
|
||||||
|
* CKE (in microseconds)
|
||||||
|
*/
|
||||||
|
u32 emc_pin_program_wait;
|
||||||
|
/* Specifies the extra delay before/after pin RESET/CKE command */
|
||||||
|
u32 emc_pin_extra_wait;
|
||||||
|
|
||||||
|
u32 emc_pin_gpio_enable;
|
||||||
|
u32 emc_pin_gpio;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies the extra delay after the first writing
|
||||||
|
* of EMC_TIMING_CONTROL
|
||||||
|
*/
|
||||||
|
u32 emc_timing_control_wait;
|
||||||
|
|
||||||
|
/* Timing parameters required for the SDRAM */
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_RC */
|
||||||
|
u32 emc_rc;
|
||||||
|
/* Specifies the value for EMC_RFC */
|
||||||
|
u32 emc_rfc;
|
||||||
|
|
||||||
|
u32 emc_rfc_pb;
|
||||||
|
u32 emc_ref_ctrl2;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_RFC_SLR */
|
||||||
|
u32 emc_rfc_slr;
|
||||||
|
/* Specifies the value for EMC_RAS */
|
||||||
|
u32 emc_ras;
|
||||||
|
/* Specifies the value for EMC_RP */
|
||||||
|
u32 emc_rp;
|
||||||
|
/* Specifies the value for EMC_R2R */
|
||||||
|
u32 emc_r2r;
|
||||||
|
/* Specifies the value for EMC_W2W */
|
||||||
|
u32 emc_w2w;
|
||||||
|
/* Specifies the value for EMC_R2W */
|
||||||
|
u32 emc_r2w;
|
||||||
|
/* Specifies the value for EMC_W2R */
|
||||||
|
u32 emc_w2r;
|
||||||
|
/* Specifies the value for EMC_R2P */
|
||||||
|
u32 emc_r2p;
|
||||||
|
/* Specifies the value for EMC_W2P */
|
||||||
|
u32 emc_w2p;
|
||||||
|
/* Specifies the value for EMC_RD_RCD */
|
||||||
|
|
||||||
|
u32 emc_tppd;
|
||||||
|
u32 emc_ccdmw;
|
||||||
|
|
||||||
|
u32 emc_rd_rcd;
|
||||||
|
/* Specifies the value for EMC_WR_RCD */
|
||||||
|
u32 emc_wr_rcd;
|
||||||
|
/* Specifies the value for EMC_RRD */
|
||||||
|
u32 emc_rrd;
|
||||||
|
/* Specifies the value for EMC_REXT */
|
||||||
|
u32 emc_rext;
|
||||||
|
/* Specifies the value for EMC_WEXT */
|
||||||
|
u32 emc_wext;
|
||||||
|
/* Specifies the value for EMC_WDV */
|
||||||
|
u32 emc_wdv;
|
||||||
|
|
||||||
|
u32 emc_wdv_chk;
|
||||||
|
u32 emc_wsv;
|
||||||
|
u32 emc_wev;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_WDV_MASK */
|
||||||
|
u32 emc_wdv_mask;
|
||||||
|
|
||||||
|
u32 emc_ws_duration;
|
||||||
|
u32 emc_we_duration;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_QUSE */
|
||||||
|
u32 emc_quse;
|
||||||
|
/* Specifies the value for EMC_QUSE_WIDTH */
|
||||||
|
u32 emc_quse_width;
|
||||||
|
/* Specifies the value for EMC_IBDLY */
|
||||||
|
u32 emc_ibdly;
|
||||||
|
|
||||||
|
u32 emc_obdly;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_EINPUT */
|
||||||
|
u32 emc_einput;
|
||||||
|
/* Specifies the value for EMC_EINPUT_DURATION */
|
||||||
|
u32 emc_einput_duration;
|
||||||
|
/* Specifies the value for EMC_PUTERM_EXTRA */
|
||||||
|
u32 emc_puterm_extra;
|
||||||
|
/* Specifies the value for EMC_PUTERM_WIDTH */
|
||||||
|
u32 emc_puterm_width;
|
||||||
|
|
||||||
|
u32 emc_qrst;
|
||||||
|
u32 emc_qsafe;
|
||||||
|
u32 emc_rdv;
|
||||||
|
u32 emc_rdv_mask;
|
||||||
|
|
||||||
|
u32 emc_rdv_early;
|
||||||
|
u32 emc_rdv_early_mask;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_QPOP */
|
||||||
|
u32 emc_qpop;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_REFRESH */
|
||||||
|
u32 emc_refresh;
|
||||||
|
/* Specifies the value for EMC_BURST_REFRESH_NUM */
|
||||||
|
u32 emc_burst_refresh_num;
|
||||||
|
/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
|
||||||
|
u32 emc_prerefresh_req_cnt;
|
||||||
|
/* Specifies the value for EMC_PDEX2WR */
|
||||||
|
u32 emc_pdex2wr;
|
||||||
|
/* Specifies the value for EMC_PDEX2RD */
|
||||||
|
u32 emc_pdex2rd;
|
||||||
|
/* Specifies the value for EMC_PCHG2PDEN */
|
||||||
|
u32 emc_pchg2pden;
|
||||||
|
/* Specifies the value for EMC_ACT2PDEN */
|
||||||
|
u32 emc_act2pden;
|
||||||
|
/* Specifies the value for EMC_AR2PDEN */
|
||||||
|
u32 emc_ar2pden;
|
||||||
|
/* Specifies the value for EMC_RW2PDEN */
|
||||||
|
u32 emc_rw2pden;
|
||||||
|
|
||||||
|
u32 emc_cke2pden;
|
||||||
|
u32 emc_pdex2che;
|
||||||
|
u32 emc_pdex2mrr;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_TXSR */
|
||||||
|
u32 emc_txsr;
|
||||||
|
/* Specifies the value for EMC_TXSRDLL */
|
||||||
|
u32 emc_txsr_dll;
|
||||||
|
/* Specifies the value for EMC_TCKE */
|
||||||
|
u32 emc_tcke;
|
||||||
|
/* Specifies the value for EMC_TCKESR */
|
||||||
|
u32 emc_tckesr;
|
||||||
|
/* Specifies the value for EMC_TPD */
|
||||||
|
u32 emc_tpd;
|
||||||
|
/* Specifies the value for EMC_TFAW */
|
||||||
|
u32 emc_tfaw;
|
||||||
|
/* Specifies the value for EMC_TRPAB */
|
||||||
|
u32 emc_trpab;
|
||||||
|
/* Specifies the value for EMC_TCLKSTABLE */
|
||||||
|
u32 emc_tclkstable;
|
||||||
|
/* Specifies the value for EMC_TCLKSTOP */
|
||||||
|
u32 emc_tclkstop;
|
||||||
|
/* Specifies the value for EMC_TREFBW */
|
||||||
|
u32 emc_trefbw;
|
||||||
|
|
||||||
|
/* FBIO configuration values */
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_FBIO_CFG5 */
|
||||||
|
u32 emc_fbio_cfg5;
|
||||||
|
/* Specifies the value for EMC_FBIO_CFG7 */
|
||||||
|
u32 emc_fbio_cfg7;
|
||||||
|
u32 emc_fbio_cfg8;
|
||||||
|
|
||||||
|
/* Command mapping for CMD brick 0 */
|
||||||
|
u32 emc_cmd_mapping_cmd0_0;
|
||||||
|
u32 emc_cmd_mapping_cmd0_1;
|
||||||
|
u32 emc_cmd_mapping_cmd0_2;
|
||||||
|
u32 emc_cmd_mapping_cmd1_0;
|
||||||
|
u32 emc_cmd_mapping_cmd1_1;
|
||||||
|
u32 emc_cmd_mapping_cmd1_2;
|
||||||
|
u32 emc_cmd_mapping_cmd2_0;
|
||||||
|
u32 emc_cmd_mapping_cmd2_1;
|
||||||
|
u32 emc_cmd_mapping_cmd2_2;
|
||||||
|
u32 emc_cmd_mapping_cmd3_0;
|
||||||
|
u32 emc_cmd_mapping_cmd3_1;
|
||||||
|
u32 emc_cmd_mapping_cmd3_2;
|
||||||
|
u32 emc_cmd_mapping_byte;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_FBIO_SPARE */
|
||||||
|
u32 emc_fbio_spare;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_CFG_RSV */
|
||||||
|
u32 emc_cfg_rsv;
|
||||||
|
|
||||||
|
/* MRS command values */
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_MRS */
|
||||||
|
u32 emc_mrs;
|
||||||
|
/* Specifies the MP0 command to initialize mode registers */
|
||||||
|
u32 emc_emrs;
|
||||||
|
/* Specifies the MP2 command to initialize mode registers */
|
||||||
|
u32 emc_emrs2;
|
||||||
|
/* Specifies the MP3 command to initialize mode registers */
|
||||||
|
u32 emc_emrs3;
|
||||||
|
/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
|
||||||
|
u32 emc_mrw1;
|
||||||
|
/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
|
||||||
|
u32 emc_mrw2;
|
||||||
|
/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
|
||||||
|
u32 emc_mrw3;
|
||||||
|
/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
|
||||||
|
u32 emc_mrw4;
|
||||||
|
|
||||||
|
/* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */
|
||||||
|
u32 emc_mrw6;
|
||||||
|
/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
|
||||||
|
u32 emc_mrw8;
|
||||||
|
/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
|
||||||
|
u32 emc_mrw9;
|
||||||
|
/* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */
|
||||||
|
u32 emc_mrw10;
|
||||||
|
/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
|
||||||
|
u32 emc_mrw12;
|
||||||
|
/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
|
||||||
|
u32 emc_mrw13;
|
||||||
|
/* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */
|
||||||
|
u32 emc_mrw14;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies the programming to extra LPDDR2 Mode Register
|
||||||
|
* at cold boot
|
||||||
|
*/
|
||||||
|
u32 emc_mrw_extra;
|
||||||
|
/*
|
||||||
|
* Specifies the programming to extra LPDDR2 Mode Register
|
||||||
|
* at warm boot
|
||||||
|
*/
|
||||||
|
u32 emc_warm_boot_mrw_extra;
|
||||||
|
/*
|
||||||
|
* Specify the enable of extra Mode Register programming at
|
||||||
|
* warm boot
|
||||||
|
*/
|
||||||
|
u32 emc_warm_boot_extramode_reg_write_enable;
|
||||||
|
/*
|
||||||
|
* Specify the enable of extra Mode Register programming at
|
||||||
|
* cold boot
|
||||||
|
*/
|
||||||
|
u32 emc_extramode_reg_write_enable;
|
||||||
|
|
||||||
|
/* Specifies the EMC_MRW reset command value */
|
||||||
|
u32 emc_mrw_reset_command;
|
||||||
|
/* Specifies the EMC Reset wait time (in microseconds) */
|
||||||
|
u32 emc_mrw_reset_ninit_wait;
|
||||||
|
/* Specifies the value for EMC_MRS_WAIT_CNT */
|
||||||
|
u32 emc_mrs_wait_cnt;
|
||||||
|
/* Specifies the value for EMC_MRS_WAIT_CNT2 */
|
||||||
|
u32 emc_mrs_wait_cnt2;
|
||||||
|
|
||||||
|
/* EMC miscellaneous configurations */
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_CFG */
|
||||||
|
u32 emc_cfg;
|
||||||
|
/* Specifies the value for EMC_CFG_2 */
|
||||||
|
u32 emc_cfg2;
|
||||||
|
/* Specifies the pipe bypass controls */
|
||||||
|
u32 emc_cfg_pipe;
|
||||||
|
|
||||||
|
u32 emc_cfg_pipe_clk;
|
||||||
|
u32 emc_fdpd_ctrl_cmd_no_ramp;
|
||||||
|
u32 emc_cfg_update;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_DBG */
|
||||||
|
u32 emc_dbg;
|
||||||
|
|
||||||
|
u32 emc_dbg_write_mux;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_CMDQ */
|
||||||
|
u32 emc_cmd_q;
|
||||||
|
/* Specifies the value for EMC_MC2EMCQ */
|
||||||
|
u32 emc_mc2emc_q;
|
||||||
|
/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
|
||||||
|
u32 emc_dyn_self_ref_control;
|
||||||
|
|
||||||
|
/* Specifies the value for MEM_INIT_DONE */
|
||||||
|
u32 ahb_arbitration_xbar_ctrl_meminit_done;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_CFG_DIG_DLL */
|
||||||
|
u32 emc_cfg_dig_dll;
|
||||||
|
u32 emc_cfg_dig_dll_1;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
|
||||||
|
u32 emc_cfg_dig_dll_period;
|
||||||
|
/* Specifies the value of *DEV_SELECTN of various EMC registers */
|
||||||
|
u32 emc_dev_select;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_SEL_DPD_CTRL */
|
||||||
|
u32 emc_sel_dpd_ctrl;
|
||||||
|
|
||||||
|
/* Pads trimmer delays */
|
||||||
|
u32 emc_fdpd_ctrl_dq;
|
||||||
|
u32 emc_fdpd_ctrl_cmd;
|
||||||
|
u32 emc_pmacro_ib_vref_dq_0;
|
||||||
|
u32 emc_pmacro_ib_vref_dq_1;
|
||||||
|
u32 emc_pmacro_ib_vref_dqs_0;
|
||||||
|
u32 emc_pmacro_ib_vref_dqs_1;
|
||||||
|
u32 emc_pmacro_ib_rxrt;
|
||||||
|
u32 emc_cfg_pipe1;
|
||||||
|
u32 emc_cfg_pipe2;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */
|
||||||
|
u32 emc_pmacro_quse_ddll_rank0_0;
|
||||||
|
u32 emc_pmacro_quse_ddll_rank0_1;
|
||||||
|
u32 emc_pmacro_quse_ddll_rank0_2;
|
||||||
|
u32 emc_pmacro_quse_ddll_rank0_3;
|
||||||
|
u32 emc_pmacro_quse_ddll_rank0_4;
|
||||||
|
u32 emc_pmacro_quse_ddll_rank0_5;
|
||||||
|
u32 emc_pmacro_quse_ddll_rank1_0;
|
||||||
|
u32 emc_pmacro_quse_ddll_rank1_1;
|
||||||
|
u32 emc_pmacro_quse_ddll_rank1_2;
|
||||||
|
u32 emc_pmacro_quse_ddll_rank1_3;
|
||||||
|
u32 emc_pmacro_quse_ddll_rank1_4;
|
||||||
|
u32 emc_pmacro_quse_ddll_rank1_5;
|
||||||
|
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dq_rank0_0;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dq_rank0_1;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dq_rank0_2;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dq_rank0_3;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dq_rank0_4;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dq_rank0_5;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dq_rank1_0;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dq_rank1_1;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dq_rank1_2;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dq_rank1_3;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dq_rank1_4;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dq_rank1_5;
|
||||||
|
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dqs_rank0_0;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dqs_rank0_1;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dqs_rank0_2;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dqs_rank0_3;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dqs_rank0_4;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dqs_rank0_5;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dqs_rank1_0;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dqs_rank1_1;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dqs_rank1_2;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dqs_rank1_3;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dqs_rank1_4;
|
||||||
|
u32 emc_pmacro_ob_ddll_long_dqs_rank1_5;
|
||||||
|
|
||||||
|
u32 emc_pmacro_ib_ddll_long_dqs_rank0_0;
|
||||||
|
u32 emc_pmacro_ib_ddll_long_dqs_rank0_1;
|
||||||
|
u32 emc_pmacro_ib_ddll_long_dqs_rank0_2;
|
||||||
|
u32 emc_pmacro_ib_ddll_long_dqs_rank0_3;
|
||||||
|
u32 emc_pmacro_ib_ddll_long_dqs_rank1_0;
|
||||||
|
u32 emc_pmacro_ib_ddll_long_dqs_rank1_1;
|
||||||
|
u32 emc_pmacro_ib_ddll_long_dqs_rank1_2;
|
||||||
|
u32 emc_pmacro_ib_ddll_long_dqs_rank1_3;
|
||||||
|
|
||||||
|
u32 emc_pmacro_ddll_long_cmd_0;
|
||||||
|
u32 emc_pmacro_ddll_long_cmd_1;
|
||||||
|
u32 emc_pmacro_ddll_long_cmd_2;
|
||||||
|
u32 emc_pmacro_ddll_long_cmd_3;
|
||||||
|
u32 emc_pmacro_ddll_long_cmd_4;
|
||||||
|
u32 emc_pmacro_ddll_short_cmd_0;
|
||||||
|
u32 emc_pmacro_ddll_short_cmd_1;
|
||||||
|
u32 emc_pmacro_ddll_short_cmd_2;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies the delay after asserting CKE pin during a WarmBoot0
|
||||||
|
* sequence (in microseconds)
|
||||||
|
*/
|
||||||
|
u32 warm_boot_wait;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_ODT_WRITE */
|
||||||
|
u32 emc_odt_write;
|
||||||
|
|
||||||
|
/* Periodic ZQ calibration */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies the value for EMC_ZCAL_INTERVAL
|
||||||
|
* Value 0 disables ZQ calibration
|
||||||
|
*/
|
||||||
|
u32 emc_zcal_interval;
|
||||||
|
/* Specifies the value for EMC_ZCAL_WAIT_CNT */
|
||||||
|
u32 emc_zcal_wait_cnt;
|
||||||
|
/* Specifies the value for EMC_ZCAL_MRW_CMD */
|
||||||
|
u32 emc_zcal_mrw_cmd;
|
||||||
|
|
||||||
|
/* DRAM initialization sequence flow control */
|
||||||
|
|
||||||
|
/* Specifies the MRS command value for resetting DLL */
|
||||||
|
u32 emc_mrs_reset_dll;
|
||||||
|
/* Specifies the command for ZQ initialization of device 0 */
|
||||||
|
u32 emc_zcal_init_dev0;
|
||||||
|
/* Specifies the command for ZQ initialization of device 1 */
|
||||||
|
u32 emc_zcal_init_dev1;
|
||||||
|
/*
|
||||||
|
* Specifies the wait time after programming a ZQ initialization
|
||||||
|
* command (in microseconds)
|
||||||
|
*/
|
||||||
|
u32 emc_zcal_init_wait;
|
||||||
|
/*
|
||||||
|
* Specifies the enable for ZQ calibration at cold boot [bit 0]
|
||||||
|
* and warm boot [bit 1]
|
||||||
|
*/
|
||||||
|
u32 emc_zcal_warm_cold_boot_enables;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies the MRW command to LPDDR2 for ZQ calibration
|
||||||
|
* on warmboot
|
||||||
|
*/
|
||||||
|
/* Is issued to both devices separately */
|
||||||
|
u32 emc_mrw_lpddr2zcal_warm_boot;
|
||||||
|
/*
|
||||||
|
* Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
|
||||||
|
* Is issued to both devices separately
|
||||||
|
*/
|
||||||
|
u32 emc_zqcal_ddr3_warm_boot;
|
||||||
|
|
||||||
|
u32 emc_zqcal_lpddr4_warm_boot;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies the wait time for ZQ calibration on warmboot
|
||||||
|
* (in microseconds)
|
||||||
|
*/
|
||||||
|
u32 emc_zcal_warm_boot_wait;
|
||||||
|
/*
|
||||||
|
* Specifies the enable for DRAM Mode Register programming
|
||||||
|
* at warm boot
|
||||||
|
*/
|
||||||
|
u32 emc_mrs_warm_boot_enable;
|
||||||
|
/*
|
||||||
|
* Specifies the wait time after sending an MRS DLL reset command
|
||||||
|
* in microseconds)
|
||||||
|
*/
|
||||||
|
u32 emc_mrs_reset_dll_wait;
|
||||||
|
/* Specifies the extra MRS command to initialize mode registers */
|
||||||
|
u32 emc_mrs_extra;
|
||||||
|
/* Specifies the extra MRS command at warm boot */
|
||||||
|
u32 emc_warm_boot_mrs_extra;
|
||||||
|
/* Specifies the EMRS command to enable the DDR2 DLL */
|
||||||
|
u32 emc_emrs_ddr2_dll_enable;
|
||||||
|
/* Specifies the MRS command to reset the DDR2 DLL */
|
||||||
|
u32 emc_mrs_ddr2_dll_reset;
|
||||||
|
/* Specifies the EMRS command to set OCD calibration */
|
||||||
|
u32 emc_emrs_ddr2_ocd_calib;
|
||||||
|
/*
|
||||||
|
* Specifies the wait between initializing DDR and setting OCD
|
||||||
|
* calibration (in microseconds)
|
||||||
|
*/
|
||||||
|
u32 emc_ddr2_wait;
|
||||||
|
/* Specifies the value for EMC_CLKEN_OVERRIDE */
|
||||||
|
u32 emc_clken_override;
|
||||||
|
/*
|
||||||
|
* Specifies LOG2 of the extra refresh numbers after booting
|
||||||
|
* Program 0 to disable
|
||||||
|
*/
|
||||||
|
u32 emc_extra_refresh_num;
|
||||||
|
/* Specifies the master override for all EMC clocks */
|
||||||
|
u32 emc_clken_override_allwarm_boot;
|
||||||
|
/* Specifies the master override for all MC clocks */
|
||||||
|
u32 mc_clken_override_allwarm_boot;
|
||||||
|
/* Specifies digital dll period, choosing between 4 to 64 ms */
|
||||||
|
u32 emc_cfg_dig_dll_period_warm_boot;
|
||||||
|
|
||||||
|
/* Pad controls */
|
||||||
|
|
||||||
|
/* Specifies the value for PMC_VDDP_SEL */
|
||||||
|
u32 pmc_vddp_sel;
|
||||||
|
/* Specifies the wait time after programming PMC_VDDP_SEL */
|
||||||
|
u32 pmc_vddp_sel_wait;
|
||||||
|
/* Specifies the value for PMC_DDR_PWR */
|
||||||
|
u32 pmc_ddr_pwr;
|
||||||
|
/* Specifies the value for PMC_DDR_CFG */
|
||||||
|
u32 pmc_ddr_cfg;
|
||||||
|
/* Specifies the value for PMC_IO_DPD3_REQ */
|
||||||
|
u32 pmc_io_dpd3_req;
|
||||||
|
/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
|
||||||
|
u32 pmc_io_dpd3_req_wait;
|
||||||
|
|
||||||
|
u32 pmc_io_dpd4_req_wait;
|
||||||
|
|
||||||
|
/* Specifies the value for PMC_REG_SHORT */
|
||||||
|
u32 pmc_reg_short;
|
||||||
|
/* Specifies the value for PMC_NO_IOPOWER */
|
||||||
|
u32 pmc_no_io_power;
|
||||||
|
|
||||||
|
u32 pmc_ddr_ctrl_wait;
|
||||||
|
u32 pmc_ddr_ctrl;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_ACPD_CONTROL */
|
||||||
|
u32 emc_acpd_control;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
|
||||||
|
u32 emc_swizzle_rank0_byte0;
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
|
||||||
|
u32 emc_swizzle_rank0_byte1;
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
|
||||||
|
u32 emc_swizzle_rank0_byte2;
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
|
||||||
|
u32 emc_swizzle_rank0_byte3;
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
|
||||||
|
u32 emc_swizzle_rank1_byte0;
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
|
||||||
|
u32 emc_swizzle_rank1_byte1;
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
|
||||||
|
u32 emc_swizzle_rank1_byte2;
|
||||||
|
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
|
||||||
|
u32 emc_swizzle_rank1_byte3;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_TXDSRVTTGEN */
|
||||||
|
u32 emc_txdsrvttgen;
|
||||||
|
|
||||||
|
/* Specifies the value for EMC_DATA_BRLSHFT_0 */
|
||||||
|
u32 emc_data_brlshft0;
|
||||||
|
u32 emc_data_brlshft1;
|
||||||
|
|
||||||
|
u32 emc_dqs_brlshft0;
|
||||||
|
u32 emc_dqs_brlshft1;
|
||||||
|
|
||||||
|
u32 emc_cmd_brlshft0;
|
||||||
|
u32 emc_cmd_brlshft1;
|
||||||
|
u32 emc_cmd_brlshft2;
|
||||||
|
u32 emc_cmd_brlshft3;
|
||||||
|
|
||||||
|
u32 emc_quse_brlshft0;
|
||||||
|
u32 emc_quse_brlshft1;
|
||||||
|
u32 emc_quse_brlshft2;
|
||||||
|
u32 emc_quse_brlshft3;
|
||||||
|
|
||||||
|
u32 emc_dll_cfg0;
|
||||||
|
u32 emc_dll_cfg1;
|
||||||
|
|
||||||
|
u32 emc_pmc_scratch1;
|
||||||
|
u32 emc_pmc_scratch2;
|
||||||
|
u32 emc_pmc_scratch3;
|
||||||
|
|
||||||
|
u32 emc_pmacro_pad_cfg_ctrl;
|
||||||
|
|
||||||
|
u32 emc_pmacro_vttgen_ctrl0;
|
||||||
|
u32 emc_pmacro_vttgen_ctrl1;
|
||||||
|
u32 emc_pmacro_vttgen_ctrl2;
|
||||||
|
|
||||||
|
u32 emc_pmacro_brick_ctrl_rfu1;
|
||||||
|
u32 emc_pmacro_cmd_brick_ctrl_fdpd;
|
||||||
|
u32 emc_pmacro_brick_ctrl_rfu2;
|
||||||
|
u32 emc_pmacro_data_brick_ctrl_fdpd;
|
||||||
|
u32 emc_pmacro_bg_bias_ctrl0;
|
||||||
|
u32 emc_pmacro_data_pad_rx_ctrl;
|
||||||
|
u32 emc_pmacro_cmd_pad_rx_ctrl;
|
||||||
|
u32 emc_pmacro_data_rx_term_mode;
|
||||||
|
u32 emc_pmacro_cmd_rx_term_mode;
|
||||||
|
u32 emc_pmacro_data_pad_tx_ctrl;
|
||||||
|
u32 emc_pmacro_common_pad_tx_ctrl;
|
||||||
|
u32 emc_pmacro_cmd_pad_tx_ctrl;
|
||||||
|
u32 emc_cfg3;
|
||||||
|
|
||||||
|
u32 emc_pmacro_tx_pwrd0;
|
||||||
|
u32 emc_pmacro_tx_pwrd1;
|
||||||
|
u32 emc_pmacro_tx_pwrd2;
|
||||||
|
u32 emc_pmacro_tx_pwrd3;
|
||||||
|
u32 emc_pmacro_tx_pwrd4;
|
||||||
|
u32 emc_pmacro_tx_pwrd5;
|
||||||
|
|
||||||
|
u32 emc_config_sample_delay;
|
||||||
|
|
||||||
|
u32 emc_pmacro_brick_mapping0;
|
||||||
|
u32 emc_pmacro_brick_mapping1;
|
||||||
|
u32 emc_pmacro_brick_mapping2;
|
||||||
|
|
||||||
|
u32 emc_pmacro_tx_sel_clk_src0;
|
||||||
|
u32 emc_pmacro_tx_sel_clk_src1;
|
||||||
|
u32 emc_pmacro_tx_sel_clk_src2;
|
||||||
|
u32 emc_pmacro_tx_sel_clk_src3;
|
||||||
|
u32 emc_pmacro_tx_sel_clk_src4;
|
||||||
|
u32 emc_pmacro_tx_sel_clk_src5;
|
||||||
|
|
||||||
|
u32 emc_pmacro_ddll_bypass;
|
||||||
|
|
||||||
|
u32 emc_pmacro_ddll_pwrd0;
|
||||||
|
u32 emc_pmacro_ddll_pwrd1;
|
||||||
|
u32 emc_pmacro_ddll_pwrd2;
|
||||||
|
|
||||||
|
u32 emc_pmacro_cmd_ctrl0;
|
||||||
|
u32 emc_pmacro_cmd_ctrl1;
|
||||||
|
u32 emc_pmacro_cmd_ctrl2;
|
||||||
|
|
||||||
|
/* DRAM size information */
|
||||||
|
|
||||||
|
/* Specifies the value for MC_EMEM_ADR_CFG */
|
||||||
|
u32 mc_emem_adr_cfg;
|
||||||
|
/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
|
||||||
|
u32 mc_emem_adr_cfg_dev0;
|
||||||
|
/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
|
||||||
|
u32 mc_emem_adr_cfg_dev1;
|
||||||
|
|
||||||
|
u32 mc_emem_adr_cfg_channel_mask;
|
||||||
|
|
||||||
|
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */
|
||||||
|
u32 mc_emem_adr_cfg_bank_mask0;
|
||||||
|
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
|
||||||
|
u32 mc_emem_adr_cfg_bank_mask1;
|
||||||
|
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
|
||||||
|
u32 mc_emem_adr_cfg_bank_mask2;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies the value for MC_EMEM_CFG which holds the external memory
|
||||||
|
* size (in KBytes)
|
||||||
|
*/
|
||||||
|
u32 mc_emem_cfg;
|
||||||
|
|
||||||
|
/* MC arbitration configuration */
|
||||||
|
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_CFG */
|
||||||
|
u32 mc_emem_arb_cfg;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
|
||||||
|
u32 mc_emem_arb_outstanding_req;
|
||||||
|
|
||||||
|
u32 emc_emem_arb_refpb_hp_ctrl;
|
||||||
|
u32 emc_emem_arb_refpb_bank_ctrl;
|
||||||
|
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
|
||||||
|
u32 mc_emem_arb_timing_rcd;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
|
||||||
|
u32 mc_emem_arb_timing_rp;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
|
||||||
|
u32 mc_emem_arb_timing_rc;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
|
||||||
|
u32 mc_emem_arb_timing_ras;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
|
||||||
|
u32 mc_emem_arb_timing_faw;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
|
||||||
|
u32 mc_emem_arb_timing_rrd;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
|
||||||
|
u32 mc_emem_arb_timing_rap2pre;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
|
||||||
|
u32 mc_emem_arb_timing_wap2pre;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
|
||||||
|
u32 mc_emem_arb_timing_r2r;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
|
||||||
|
u32 mc_emem_arb_timing_w2w;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
|
||||||
|
u32 mc_emem_arb_timing_r2w;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
|
||||||
|
u32 mc_emem_arb_timing_w2r;
|
||||||
|
|
||||||
|
u32 mc_emem_arb_timing_rfcpb;
|
||||||
|
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
|
||||||
|
u32 mc_emem_arb_da_turns;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
|
||||||
|
u32 mc_emem_arb_da_covers;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_MISC0 */
|
||||||
|
u32 mc_emem_arb_misc0;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_MISC1 */
|
||||||
|
u32 mc_emem_arb_misc1;
|
||||||
|
u32 mc_emem_arb_misc2;
|
||||||
|
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
|
||||||
|
u32 mc_emem_arb_ring1_throttle;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
|
||||||
|
u32 mc_emem_arb_override;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
|
||||||
|
u32 mc_emem_arb_override1;
|
||||||
|
/* Specifies the value for MC_EMEM_ARB_RSV */
|
||||||
|
u32 mc_emem_arb_rsv;
|
||||||
|
|
||||||
|
u32 mc_da_cfg0;
|
||||||
|
u32 mc_emem_arb_timing_ccdmw;
|
||||||
|
|
||||||
|
/* Specifies the value for MC_CLKEN_OVERRIDE */
|
||||||
|
u32 mc_clken_override;
|
||||||
|
|
||||||
|
/* Specifies the value for MC_STAT_CONTROL */
|
||||||
|
u32 mc_stat_control;
|
||||||
|
/* Specifies the value for MC_VIDEO_PROTECT_BOM */
|
||||||
|
u32 mc_video_protect_bom;
|
||||||
|
/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
|
||||||
|
u32 mc_video_protect_bom_adr_hi;
|
||||||
|
/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
|
||||||
|
u32 mc_video_protect_size_mb;
|
||||||
|
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
|
||||||
|
u32 mc_video_protect_vpr_override;
|
||||||
|
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
|
||||||
|
u32 mc_video_protect_vpr_override1;
|
||||||
|
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
|
||||||
|
u32 mc_video_protect_gpu_override0;
|
||||||
|
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
|
||||||
|
u32 mc_video_protect_gpu_override1;
|
||||||
|
/* Specifies the value for MC_SEC_CARVEOUT_BOM */
|
||||||
|
u32 mc_sec_carveout_bom;
|
||||||
|
/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
|
||||||
|
u32 mc_sec_carveout_adr_hi;
|
||||||
|
/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
|
||||||
|
u32 mc_sec_carveout_size_mb;
|
||||||
|
/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */
|
||||||
|
u32 mc_video_protect_write_access;
|
||||||
|
/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */
|
||||||
|
u32 mc_sec_carveout_protect_write_access;
|
||||||
|
|
||||||
|
u32 mc_generalized_carveout1_bom;
|
||||||
|
u32 mc_generalized_carveout1_bom_hi;
|
||||||
|
u32 mc_generalized_carveout1_size_128kb;
|
||||||
|
u32 mc_generalized_carveout1_access0;
|
||||||
|
u32 mc_generalized_carveout1_access1;
|
||||||
|
u32 mc_generalized_carveout1_access2;
|
||||||
|
u32 mc_generalized_carveout1_access3;
|
||||||
|
u32 mc_generalized_carveout1_access4;
|
||||||
|
u32 mc_generalized_carveout1_force_internal_access0;
|
||||||
|
u32 mc_generalized_carveout1_force_internal_access1;
|
||||||
|
u32 mc_generalized_carveout1_force_internal_access2;
|
||||||
|
u32 mc_generalized_carveout1_force_internal_access3;
|
||||||
|
u32 mc_generalized_carveout1_force_internal_access4;
|
||||||
|
u32 mc_generalized_carveout1_cfg0;
|
||||||
|
|
||||||
|
u32 mc_generalized_carveout2_bom;
|
||||||
|
u32 mc_generalized_carveout2_bom_hi;
|
||||||
|
u32 mc_generalized_carveout2_size_128kb;
|
||||||
|
u32 mc_generalized_carveout2_access0;
|
||||||
|
u32 mc_generalized_carveout2_access1;
|
||||||
|
u32 mc_generalized_carveout2_access2;
|
||||||
|
u32 mc_generalized_carveout2_access3;
|
||||||
|
u32 mc_generalized_carveout2_access4;
|
||||||
|
u32 mc_generalized_carveout2_force_internal_access0;
|
||||||
|
u32 mc_generalized_carveout2_force_internal_access1;
|
||||||
|
u32 mc_generalized_carveout2_force_internal_access2;
|
||||||
|
u32 mc_generalized_carveout2_force_internal_access3;
|
||||||
|
u32 mc_generalized_carveout2_force_internal_access4;
|
||||||
|
u32 mc_generalized_carveout2_cfg0;
|
||||||
|
|
||||||
|
u32 mc_generalized_carveout3_bom;
|
||||||
|
u32 mc_generalized_carveout3_bom_hi;
|
||||||
|
u32 mc_generalized_carveout3_size_128kb;
|
||||||
|
u32 mc_generalized_carveout3_access0;
|
||||||
|
u32 mc_generalized_carveout3_access1;
|
||||||
|
u32 mc_generalized_carveout3_access2;
|
||||||
|
u32 mc_generalized_carveout3_access3;
|
||||||
|
u32 mc_generalized_carveout3_access4;
|
||||||
|
u32 mc_generalized_carveout3_force_internal_access0;
|
||||||
|
u32 mc_generalized_carveout3_force_internal_access1;
|
||||||
|
u32 mc_generalized_carveout3_force_internal_access2;
|
||||||
|
u32 mc_generalized_carveout3_force_internal_access3;
|
||||||
|
u32 mc_generalized_carveout3_force_internal_access4;
|
||||||
|
u32 mc_generalized_carveout3_cfg0;
|
||||||
|
|
||||||
|
u32 mc_generalized_carveout4_bom;
|
||||||
|
u32 mc_generalized_carveout4_bom_hi;
|
||||||
|
u32 mc_generalized_carveout4_size_128kb;
|
||||||
|
u32 mc_generalized_carveout4_access0;
|
||||||
|
u32 mc_generalized_carveout4_access1;
|
||||||
|
u32 mc_generalized_carveout4_access2;
|
||||||
|
u32 mc_generalized_carveout4_access3;
|
||||||
|
u32 mc_generalized_carveout4_access4;
|
||||||
|
u32 mc_generalized_carveout4_force_internal_access0;
|
||||||
|
u32 mc_generalized_carveout4_force_internal_access1;
|
||||||
|
u32 mc_generalized_carveout4_force_internal_access2;
|
||||||
|
u32 mc_generalized_carveout4_force_internal_access3;
|
||||||
|
u32 mc_generalized_carveout4_force_internal_access4;
|
||||||
|
u32 mc_generalized_carveout4_cfg0;
|
||||||
|
|
||||||
|
u32 mc_generalized_carveout5_bom;
|
||||||
|
u32 mc_generalized_carveout5_bom_hi;
|
||||||
|
u32 mc_generalized_carveout5_size_128kb;
|
||||||
|
u32 mc_generalized_carveout5_access0;
|
||||||
|
u32 mc_generalized_carveout5_access1;
|
||||||
|
u32 mc_generalized_carveout5_access2;
|
||||||
|
u32 mc_generalized_carveout5_access3;
|
||||||
|
u32 mc_generalized_carveout5_access4;
|
||||||
|
u32 mc_generalized_carveout5_force_internal_access0;
|
||||||
|
u32 mc_generalized_carveout5_force_internal_access1;
|
||||||
|
u32 mc_generalized_carveout5_force_internal_access2;
|
||||||
|
u32 mc_generalized_carveout5_force_internal_access3;
|
||||||
|
u32 mc_generalized_carveout5_force_internal_access4;
|
||||||
|
u32 mc_generalized_carveout5_cfg0;
|
||||||
|
|
||||||
|
/* Specifies enable for CA training */
|
||||||
|
u32 emc_ca_training_enable;
|
||||||
|
/* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */
|
||||||
|
u32 swizzle_rank_byte_encode;
|
||||||
|
/* Specifies enable and offset for patched boot rom write */
|
||||||
|
u32 boot_rom_patch_control;
|
||||||
|
/* Specifies data for patched boot rom write */
|
||||||
|
u32 boot_rom_patch_data;
|
||||||
|
|
||||||
|
/* Specifies the value for MC_MTS_CARVEOUT_BOM */
|
||||||
|
u32 mc_mts_carveout_bom;
|
||||||
|
/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
|
||||||
|
u32 mc_mts_carveout_adr_hi;
|
||||||
|
/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
|
||||||
|
u32 mc_mts_carveout_size_mb;
|
||||||
|
/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
|
||||||
|
u32 mc_mts_carveout_reg_ctrl;
|
||||||
|
} sdram_params_t;
|
||||||
|
|
||||||
|
#endif
|
162
source/power/bq24193.c
Normal file
162
source/power/bq24193.c
Normal file
@ -0,0 +1,162 @@
|
|||||||
|
/*
|
||||||
|
* Battery charger driver for Nintendo Switch's TI BQ24193
|
||||||
|
*
|
||||||
|
* Copyright (C) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "bq24193.h"
|
||||||
|
#include "../soc/i2c.h"
|
||||||
|
#include "../utils/util.h"
|
||||||
|
|
||||||
|
int bq24193_get_property(enum BQ24193_reg_prop prop, int *value)
|
||||||
|
{
|
||||||
|
u8 data;
|
||||||
|
|
||||||
|
switch (prop) {
|
||||||
|
case BQ24193_InputVoltageLimit: // Input voltage limit (mV).
|
||||||
|
data = i2c_recv_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_InputSource);
|
||||||
|
data = (data & BQ24193_INCONFIG_VINDPM_MASK) >> 3;
|
||||||
|
*value += ((data >> 0) & 1) ? 80 : 0;
|
||||||
|
*value += ((data >> 1) & 1) ? 160 : 0;
|
||||||
|
*value += ((data >> 2) & 1) ? 320 : 0;
|
||||||
|
*value += ((data >> 3) & 1) ? 640 : 0;
|
||||||
|
*value += 3880;
|
||||||
|
break;
|
||||||
|
case BQ24193_InputCurrentLimit: // Input current limit (mA).
|
||||||
|
data = i2c_recv_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_InputSource);
|
||||||
|
data &= BQ24193_INCONFIG_INLIMIT_MASK;
|
||||||
|
switch (data)
|
||||||
|
{
|
||||||
|
case 0:
|
||||||
|
*value = 100;
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
*value = 150;
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
*value = 500;
|
||||||
|
break;
|
||||||
|
case 3:
|
||||||
|
*value = 900;
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
*value = 1200;
|
||||||
|
break;
|
||||||
|
case 5:
|
||||||
|
*value = 1500;
|
||||||
|
break;
|
||||||
|
case 6:
|
||||||
|
*value = 2000;
|
||||||
|
break;
|
||||||
|
case 7:
|
||||||
|
*value = 3000;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case BQ24193_SystemMinimumVoltage: // Minimum system voltage limit (mV).
|
||||||
|
data = i2c_recv_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_PORConfig);
|
||||||
|
*value = (data & BQ24193_PORCONFIG_SYSMIN_MASK) >> 1;
|
||||||
|
*value *= 100;
|
||||||
|
*value += 3000;
|
||||||
|
break;
|
||||||
|
case BQ24193_FastChargeCurrentLimit: // Fast charge current limit (mA).
|
||||||
|
data = i2c_recv_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_ChrgCurr);
|
||||||
|
data = (data & BQ24193_CHRGCURR_ICHG_MASK) >> 2;
|
||||||
|
*value += ((data >> 0) & 1) ? 64 : 0;
|
||||||
|
*value += ((data >> 1) & 1) ? 128 : 0;
|
||||||
|
*value += ((data >> 2) & 1) ? 256 : 0;
|
||||||
|
*value += ((data >> 3) & 1) ? 512 : 0;
|
||||||
|
*value += ((data >> 4) & 1) ? 1024 : 0;
|
||||||
|
*value += ((data >> 5) & 1) ? 2048 : 0;
|
||||||
|
*value += 512;
|
||||||
|
data = i2c_recv_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_ChrgCurr);
|
||||||
|
data &= BQ24193_CHRGCURR_20PCT_MASK;
|
||||||
|
if (data)
|
||||||
|
*value = *value * 20 / 100; // Fast charge current limit is 20%.
|
||||||
|
break;
|
||||||
|
case BQ24193_ChargeVoltageLimit: // Charge voltage limit (mV).
|
||||||
|
data = i2c_recv_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_ChrgVolt);
|
||||||
|
data = (data & BQ24193_CHRGVOLT_VREG) >> 2;
|
||||||
|
*value += ((data >> 0) & 1) ? 16 : 0;
|
||||||
|
*value += ((data >> 1) & 1) ? 32 : 0;
|
||||||
|
*value += ((data >> 2) & 1) ? 64 : 0;
|
||||||
|
*value += ((data >> 3) & 1) ? 128 : 0;
|
||||||
|
*value += ((data >> 4) & 1) ? 256 : 0;
|
||||||
|
*value += ((data >> 5) & 1) ? 512 : 0;
|
||||||
|
*value += 3504;
|
||||||
|
break;
|
||||||
|
case BQ24193_RechargeThreshold: // Recharge voltage threshold less than voltage limit (mV).
|
||||||
|
data = i2c_recv_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_ChrgVolt);
|
||||||
|
data &= BQ24193_IRTHERMAL_THERM_MASK;
|
||||||
|
if (data)
|
||||||
|
*value = 300;
|
||||||
|
else
|
||||||
|
*value = 100;
|
||||||
|
break;
|
||||||
|
case BQ24193_ThermalRegulation: // Thermal regulation threshold (oC).
|
||||||
|
data = i2c_recv_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_IRCompThermal);
|
||||||
|
data &= BQ24193_IRTHERMAL_THERM_MASK;
|
||||||
|
switch (data)
|
||||||
|
{
|
||||||
|
case 0:
|
||||||
|
*value = 60;
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
*value = 80;
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
*value = 100;
|
||||||
|
break;
|
||||||
|
case 3:
|
||||||
|
*value = 120;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case BQ24193_ChargeStatus: // 0: Not charging, 1: Pre-charge, 2: Fast charging, 3: Charge termination done
|
||||||
|
data = i2c_recv_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_Status);
|
||||||
|
*value = (data & BQ24193_STATUS_CHRG_MASK) >> 4;
|
||||||
|
break;
|
||||||
|
case BQ24193_TempStatus: // 0: Normal, 2: Warm, 3: Cool, 5: Cold, 6: Hot.
|
||||||
|
data = i2c_recv_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_FaultReg);
|
||||||
|
*value = data & BQ24193_FAULT_THERM_MASK;
|
||||||
|
break;
|
||||||
|
case BQ24193_DevID: // Dev ID.
|
||||||
|
data = i2c_recv_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_VendorPart);
|
||||||
|
*value = data & BQ24193_VENDORPART_DEV_MASK;
|
||||||
|
break;
|
||||||
|
case BQ24193_ProductNumber: // Product number.
|
||||||
|
data = i2c_recv_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_VendorPart);
|
||||||
|
*value = (data & BQ24193_VENDORPART_PN_MASK) >> 3;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void bq24193_fake_battery_removal()
|
||||||
|
{
|
||||||
|
u8 value;
|
||||||
|
|
||||||
|
// Disable watchdog to keep BATFET disabled.
|
||||||
|
value = i2c_recv_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_ChrgTermTimer);
|
||||||
|
value &= ~BQ24193_CHRGTERM_WATCHDOG_MASK;
|
||||||
|
i2c_send_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_ChrgTermTimer, value);
|
||||||
|
|
||||||
|
// Force BATFET to disabled state. This disconnects the battery from the system.
|
||||||
|
value = i2c_recv_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_Misc);
|
||||||
|
value |= BQ24193_MISC_BATFET_DI_MASK;
|
||||||
|
i2c_send_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_Misc, value);
|
||||||
|
}
|
119
source/power/bq24193.h
Normal file
119
source/power/bq24193.h
Normal file
@ -0,0 +1,119 @@
|
|||||||
|
/*
|
||||||
|
* Battery charger driver for Nintendo Switch's TI BQ24193
|
||||||
|
*
|
||||||
|
* Copyright (C) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __BQ24193_H_
|
||||||
|
#define __BQ24193_H_
|
||||||
|
|
||||||
|
#define BQ24193_I2C_ADDR 0x6B
|
||||||
|
|
||||||
|
// REG 0 masks.
|
||||||
|
#define BQ24193_INCONFIG_INLIMIT_MASK (7<<0)
|
||||||
|
#define BQ24193_INCONFIG_VINDPM_MASK 0x78
|
||||||
|
#define BQ24193_INCONFIG_HIZ_EN_MASK (1<<7)
|
||||||
|
|
||||||
|
// REG 1 masks.
|
||||||
|
#define BQ24193_PORCONFIG_BOOST_MASK (1<<0)
|
||||||
|
#define BQ24193_PORCONFIG_SYSMIN_MASK (7<<1)
|
||||||
|
#define BQ24193_PORCONFIG_CHGCONFIG_MASK (3<<4)
|
||||||
|
#define BQ24193_PORCONFIG_I2CWATCHDOG_MASK (1<<6)
|
||||||
|
#define BQ24193_PORCONFIG_RESET_MASK (1<<7)
|
||||||
|
|
||||||
|
// REG 2 masks.
|
||||||
|
#define BQ24193_CHRGCURR_20PCT_MASK (1<<0)
|
||||||
|
#define BQ24193_CHRGCURR_ICHG_MASK 0xFC
|
||||||
|
|
||||||
|
// REG 3 masks.
|
||||||
|
#define BQ24193_PRECHRG_ITERM 0x0F
|
||||||
|
#define BQ24193_PRECHRG_IPRECHG 0xF0
|
||||||
|
|
||||||
|
// REG 4 masks.
|
||||||
|
#define BQ24193_CHRGVOLT_VTHRES (1<<0)
|
||||||
|
#define BQ24193_CHRGVOLT_BATTLOW (1<<1)
|
||||||
|
#define BQ24193_CHRGVOLT_VREG 0xFC
|
||||||
|
|
||||||
|
// REG 5 masks.
|
||||||
|
#define BQ24193_CHRGTERM_ISET_MASK (1<<0)
|
||||||
|
#define BQ24193_CHRGTERM_CHGTIMER_MASK (3<<1)
|
||||||
|
#define BQ24193_CHRGTERM_ENTIMER_MASK (1<<3)
|
||||||
|
#define BQ24193_CHRGTERM_WATCHDOG_MASK (3<<4)
|
||||||
|
#define BQ24193_CHRGTERM_TERM_ST_MASK (1<<6)
|
||||||
|
#define BQ24193_CHRGTERM_TERM_EN_MASK (1<<7)
|
||||||
|
|
||||||
|
// REG 6 masks.
|
||||||
|
#define BQ24193_IRTHERMAL_THERM_MASK (3<<0)
|
||||||
|
#define BQ24193_IRTHERMAL_VCLAMP_MASK (7<<2)
|
||||||
|
#define BQ24193_IRTHERMAL_BATTCOMP_MASK (7<<5)
|
||||||
|
|
||||||
|
// REG 7 masks.
|
||||||
|
#define BQ24193_MISC_INT_MASK (3<<0)
|
||||||
|
#define BQ24193_MISC_VSET_MASK (1<<4)
|
||||||
|
#define BQ24193_MISC_BATFET_DI_MASK (1<<5)
|
||||||
|
#define BQ24193_MISC_TMR2X_EN_MASK (1<<6)
|
||||||
|
#define BQ24193_MISC_DPDM_EN_MASK (1<<7)
|
||||||
|
|
||||||
|
// REG 8 masks.
|
||||||
|
#define BQ24193_STATUS_VSYS_MASK (1<<0)
|
||||||
|
#define BQ24193_STATUS_THERM_MASK (1<<1)
|
||||||
|
#define BQ24193_STATUS_PG_MASK (1<<2)
|
||||||
|
#define BQ24193_STATUS_DPM_MASK (1<<3)
|
||||||
|
#define BQ24193_STATUS_CHRG_MASK (3<<4)
|
||||||
|
#define BQ24193_STATUS_VBUS_MASK (3<<6)
|
||||||
|
|
||||||
|
// REG 9 masks.
|
||||||
|
#define BQ24193_FAULT_THERM_MASK (7<<0)
|
||||||
|
#define BQ24193_FAULT_BATT_OVP_MASK (1<<3)
|
||||||
|
#define BQ24193_FAULT_CHARGE_MASK (3<<4)
|
||||||
|
#define BQ24193_FAULT_BOOST_MASK (1<<6)
|
||||||
|
#define BQ24193_FAULT_WATCHDOG_MASK (1<<7)
|
||||||
|
|
||||||
|
// REG A masks.
|
||||||
|
#define BQ24193_VENDORPART_DEV_MASK (3<<0)
|
||||||
|
#define BQ24193_VENDORPART_PN_MASK (7<<3)
|
||||||
|
|
||||||
|
enum BQ24193_reg {
|
||||||
|
BQ24193_InputSource = 0x00,
|
||||||
|
BQ24193_PORConfig = 0x01,
|
||||||
|
BQ24193_ChrgCurr = 0x02,
|
||||||
|
BQ24193_PreChrgTerm = 0x03,
|
||||||
|
BQ24193_ChrgVolt = 0x04,
|
||||||
|
BQ24193_ChrgTermTimer = 0x05,
|
||||||
|
BQ24193_IRCompThermal = 0x06,
|
||||||
|
BQ24193_Misc = 0x07,
|
||||||
|
BQ24193_Status = 0x08,
|
||||||
|
BQ24193_FaultReg = 0x09,
|
||||||
|
BQ24193_VendorPart = 0x0A,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum BQ24193_reg_prop {
|
||||||
|
BQ24193_InputVoltageLimit, // REG 0.
|
||||||
|
BQ24193_InputCurrentLimit, // REG 0.
|
||||||
|
BQ24193_SystemMinimumVoltage, // REG 1.
|
||||||
|
BQ24193_FastChargeCurrentLimit, // REG 2.
|
||||||
|
BQ24193_ChargeVoltageLimit, // REG 4.
|
||||||
|
BQ24193_RechargeThreshold, // REG 4.
|
||||||
|
BQ24193_ThermalRegulation, // REG 6.
|
||||||
|
BQ24193_ChargeStatus, // REG 8.
|
||||||
|
BQ24193_TempStatus, // REG 9.
|
||||||
|
BQ24193_DevID, // REG A.
|
||||||
|
BQ24193_ProductNumber, // REG A.
|
||||||
|
};
|
||||||
|
|
||||||
|
int bq24193_get_property(enum BQ24193_reg_prop prop, int *value);
|
||||||
|
void bq24193_fake_battery_removal();
|
||||||
|
|
||||||
|
#endif /* __BQ24193_H_ */
|
266
source/power/max17050.c
Normal file
266
source/power/max17050.c
Normal file
@ -0,0 +1,266 @@
|
|||||||
|
/*
|
||||||
|
* Fuel gauge driver for Nintendo Switch's Maxim 17050
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Samsung Electronics
|
||||||
|
* MyungJoo Ham <myungjoo.ham@samsung.com>
|
||||||
|
* Copyright (C) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||||
|
*
|
||||||
|
* This driver is based on max17040_battery.c
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "max17050.h"
|
||||||
|
#include "../soc/i2c.h"
|
||||||
|
#include "../utils/util.h"
|
||||||
|
|
||||||
|
/* Status register bits */
|
||||||
|
#define STATUS_POR_BIT (1 << 1)
|
||||||
|
#define STATUS_BST_BIT (1 << 3)
|
||||||
|
#define STATUS_VMN_BIT (1 << 8)
|
||||||
|
#define STATUS_TMN_BIT (1 << 9)
|
||||||
|
#define STATUS_SMN_BIT (1 << 10)
|
||||||
|
#define STATUS_BI_BIT (1 << 11)
|
||||||
|
#define STATUS_VMX_BIT (1 << 12)
|
||||||
|
#define STATUS_TMX_BIT (1 << 13)
|
||||||
|
#define STATUS_SMX_BIT (1 << 14)
|
||||||
|
#define STATUS_BR_BIT (1 << 15)
|
||||||
|
|
||||||
|
#define VFSOC0_LOCK 0x0000
|
||||||
|
#define VFSOC0_UNLOCK 0x0080
|
||||||
|
|
||||||
|
#define MAX17050_VMAX_TOLERANCE 50 /* 50 mV */
|
||||||
|
|
||||||
|
int max17050_get_property(enum MAX17050_reg reg, int *value)
|
||||||
|
{
|
||||||
|
u16 data;
|
||||||
|
|
||||||
|
switch (reg)
|
||||||
|
{
|
||||||
|
case MAX17050_Age: // Age (percent). Based on 100% x (FullCAP Register/DesignCap).
|
||||||
|
i2c_recv_buf_small((u8 *)&data, 2, I2C_1, MAXIM17050_I2C_ADDR, MAX17050_Age);
|
||||||
|
*value = data >> 8; /* Show MSB. 1% increments */
|
||||||
|
break;
|
||||||
|
case MAX17050_Cycles: // Cycle count.
|
||||||
|
i2c_recv_buf_small((u8 *)value, 2, I2C_1, MAXIM17050_I2C_ADDR, MAX17050_Cycles);
|
||||||
|
break;
|
||||||
|
case MAX17050_MinVolt: // Voltage max/min
|
||||||
|
i2c_recv_buf_small((u8 *)&data, 2, I2C_1, MAXIM17050_I2C_ADDR, MAX17050_MinMaxVolt);
|
||||||
|
*value = (data & 0xff) * 20; /* Voltage MIN. Units of 20mV */
|
||||||
|
break;
|
||||||
|
case MAX17050_MaxVolt: // Voltage max/min
|
||||||
|
i2c_recv_buf_small((u8 *)&data, 2, I2C_1, MAXIM17050_I2C_ADDR, MAX17050_MinMaxVolt);
|
||||||
|
*value = (data >> 8) * 20; /* Voltage MAX. Units of LSB = 20mV */
|
||||||
|
break;
|
||||||
|
case MAX17050_V_empty: // Voltage min design.
|
||||||
|
i2c_recv_buf_small((u8 *)&data, 2, I2C_1, MAXIM17050_I2C_ADDR, MAX17050_V_empty);
|
||||||
|
*value = (data >> 7) * 10; /* Units of LSB = 10mV */
|
||||||
|
break;
|
||||||
|
case MAX17050_VCELL: // Voltage now.
|
||||||
|
i2c_recv_buf_small((u8 *)&data, 2, I2C_1, MAXIM17050_I2C_ADDR, MAX17050_VCELL);
|
||||||
|
*value = data * 625 / 8 / 1000;
|
||||||
|
break;
|
||||||
|
case MAX17050_AvgVCELL: // Voltage avg.
|
||||||
|
i2c_recv_buf_small((u8 *)&data, 2, I2C_1, MAXIM17050_I2C_ADDR, MAX17050_AvgVCELL);
|
||||||
|
*value = data * 625 / 8 / 1000;
|
||||||
|
break;
|
||||||
|
case MAX17050_OCVInternal: // Voltage ocv.
|
||||||
|
i2c_recv_buf_small((u8 *)&data, 2, I2C_1, MAXIM17050_I2C_ADDR, MAX17050_OCVInternal);
|
||||||
|
*value = data * 625 / 8 / 1000;
|
||||||
|
break;
|
||||||
|
case MAX17050_RepSOC: // Capacity %.
|
||||||
|
i2c_recv_buf_small((u8 *)value, 2, I2C_1, MAXIM17050_I2C_ADDR, MAX17050_RepSOC);
|
||||||
|
break;
|
||||||
|
case MAX17050_DesignCap: // Charge full design.
|
||||||
|
i2c_recv_buf_small((u8 *)&data, 2, I2C_1, MAXIM17050_I2C_ADDR, MAX17050_DesignCap);
|
||||||
|
data = data * 5 / 10;
|
||||||
|
*value = data;
|
||||||
|
break;
|
||||||
|
case MAX17050_FullCAP: // Charge full.
|
||||||
|
i2c_recv_buf_small((u8 *)&data, 2, I2C_1, MAXIM17050_I2C_ADDR, MAX17050_FullCAP);
|
||||||
|
data = data * 5 / 10;
|
||||||
|
*value = data;
|
||||||
|
break;
|
||||||
|
case MAX17050_RepCap: // Charge now.
|
||||||
|
i2c_recv_buf_small((u8 *)&data, 2, I2C_1, MAXIM17050_I2C_ADDR, MAX17050_RepCap);
|
||||||
|
data = data * 5 / 10;
|
||||||
|
*value = data;
|
||||||
|
break;
|
||||||
|
case MAX17050_TEMP: // Temp.
|
||||||
|
i2c_recv_buf_small((u8 *)&data, 2, I2C_1, MAXIM17050_I2C_ADDR, MAX17050_TEMP);
|
||||||
|
*value = (s16)data;
|
||||||
|
*value = *value * 10 / 256;
|
||||||
|
break;
|
||||||
|
case MAX17050_Current: // Current now.
|
||||||
|
i2c_recv_buf_small((u8 *)&data, 2, I2C_1, MAXIM17050_I2C_ADDR, MAX17050_Current);
|
||||||
|
*value = (s16)data;
|
||||||
|
*value *= 1562500 / MAX17050_DEFAULT_SNS_RESISTOR;
|
||||||
|
break;
|
||||||
|
case MAX17050_AvgCurrent: // Current avg.
|
||||||
|
i2c_recv_buf_small((u8 *)&data, 2, I2C_1, MAXIM17050_I2C_ADDR, MAX17050_AvgCurrent);
|
||||||
|
*value = (s16)data;
|
||||||
|
*value *= 1562500 / MAX17050_DEFAULT_SNS_RESISTOR;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int _max17050_write_verify_reg(u8 reg, u16 value)
|
||||||
|
{
|
||||||
|
int retries = 8;
|
||||||
|
int ret;
|
||||||
|
u16 read_value;
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
ret = i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, reg, (u8 *)&value, 2);
|
||||||
|
i2c_recv_buf_small((u8 *)&read_value, 2, I2C_1, MAXIM17050_I2C_ADDR, reg);
|
||||||
|
if (read_value != value)
|
||||||
|
{
|
||||||
|
ret = -1;
|
||||||
|
retries--;
|
||||||
|
}
|
||||||
|
} while (retries && read_value != value);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _max17050_override_por(u8 reg, u16 value)
|
||||||
|
{
|
||||||
|
if (value)
|
||||||
|
i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, reg, (u8 *)&value, 2);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _max17050_load_new_capacity_params()
|
||||||
|
{
|
||||||
|
u16 fullcap, repSoc, dq_acc, dp_acc;
|
||||||
|
|
||||||
|
fullcap = 0x2476; // 4667mAh design capacity.
|
||||||
|
dq_acc = 0x10bc; // From a healthy fuel gauge.
|
||||||
|
dp_acc = 0x5e09; // =||=
|
||||||
|
repSoc = 0x6400; // 100%.
|
||||||
|
|
||||||
|
_max17050_write_verify_reg(MAX17050_RemCap, fullcap);
|
||||||
|
_max17050_write_verify_reg(MAX17050_RepCap, fullcap);
|
||||||
|
|
||||||
|
_max17050_write_verify_reg(MAX17050_dQacc, dq_acc);
|
||||||
|
_max17050_write_verify_reg(MAX17050_dPacc, dp_acc);
|
||||||
|
|
||||||
|
_max17050_write_verify_reg(MAX17050_FullCAP, fullcap);
|
||||||
|
//i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_DesignCap, (u8 *)&fullcap, 2);
|
||||||
|
_max17050_write_verify_reg(MAX17050_FullCAPNom, fullcap);
|
||||||
|
/* Update SOC register with new SOC */
|
||||||
|
i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_RepSOC, (u8 *)&repSoc, 2);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _max17050_reset_vfsoc0_reg()
|
||||||
|
{
|
||||||
|
u16 lockVal = 0;
|
||||||
|
u16 vfSoc = 0x6440; // >100% for fully charged battery
|
||||||
|
|
||||||
|
lockVal = VFSOC0_UNLOCK;
|
||||||
|
i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_VFSOC0Enable, (u8 *)&lockVal, 2);
|
||||||
|
|
||||||
|
_max17050_write_verify_reg(MAX17050_VFSOC0, vfSoc);
|
||||||
|
|
||||||
|
lockVal = VFSOC0_LOCK;
|
||||||
|
i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_VFSOC0Enable, (u8 *)&lockVal, 2);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _max17050_update_capacity_regs()
|
||||||
|
{
|
||||||
|
u16 value = 0x2476; // Set to 4667mAh design capacity.
|
||||||
|
_max17050_write_verify_reg(MAX17050_FullCAP, value);
|
||||||
|
_max17050_write_verify_reg(MAX17050_FullCAPNom, value);
|
||||||
|
//i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_DesignCap, config->design_cap, 2);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _max17050_write_config_regs()
|
||||||
|
{
|
||||||
|
u16 value = 0;
|
||||||
|
|
||||||
|
value = 0x7254;
|
||||||
|
i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_CONFIG, (u8 *)&value, 2);
|
||||||
|
value = 0x2473;
|
||||||
|
i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_LearnCFG, (u8 *)&value, 2);
|
||||||
|
//i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_FilterCFG, (u8 *)&value, 2)
|
||||||
|
//i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_RelaxCFG, (u8 *)&value, 2)
|
||||||
|
//i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_FullSOCThr, (u8 *)&value, 2)
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Block write all the override values coming from platform data.
|
||||||
|
* This function MUST be called before the POR initialization proceedure
|
||||||
|
* specified by maxim.
|
||||||
|
*/
|
||||||
|
static void _max17050_override_por_values()
|
||||||
|
{
|
||||||
|
u16 dq_acc = 0x10bc; // From a healthy fuel gauge.
|
||||||
|
u16 dp_acc = 0x5e09; // =||=
|
||||||
|
|
||||||
|
_max17050_override_por(MAX17050_dQacc, dq_acc);
|
||||||
|
_max17050_override_por(MAX17050_dPacc, dp_acc);
|
||||||
|
|
||||||
|
//_max17050_override_por(MAX17050_RCOMP0, config->rcomp0); //0x58
|
||||||
|
//_max17050_override_por(MAX17050_TempCo, config->tcompc0); //0x1b22
|
||||||
|
|
||||||
|
//u16 k_empty0 = 0x439;
|
||||||
|
//_max17050_override_por(map, MAX17050_K_empty0, k_empty0); // Unknown cell data
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _max17050_set_por_bit(u16 value)
|
||||||
|
{
|
||||||
|
_max17050_write_verify_reg(MAX17050_STATUS, value);
|
||||||
|
}
|
||||||
|
|
||||||
|
int max17050_fix_configuration()
|
||||||
|
{
|
||||||
|
/* Init phase, set the POR bit */
|
||||||
|
_max17050_set_por_bit(STATUS_POR_BIT);
|
||||||
|
|
||||||
|
/* Override POR values */
|
||||||
|
_max17050_override_por_values();
|
||||||
|
/* After Power up, the MAX17050 requires 500ms in order
|
||||||
|
* to perform signal debouncing and initial SOC reporting
|
||||||
|
*/
|
||||||
|
msleep(500);
|
||||||
|
|
||||||
|
/* Initialize configaration */
|
||||||
|
_max17050_write_config_regs();
|
||||||
|
|
||||||
|
/* update capacity params */
|
||||||
|
_max17050_update_capacity_regs();
|
||||||
|
|
||||||
|
/* delay must be atleast 350mS to allow VFSOC
|
||||||
|
* to be calculated from the new configuration
|
||||||
|
*/
|
||||||
|
msleep(350);
|
||||||
|
|
||||||
|
/* reset vfsoc0 reg */
|
||||||
|
_max17050_reset_vfsoc0_reg();
|
||||||
|
|
||||||
|
/* load new capacity params */
|
||||||
|
_max17050_load_new_capacity_params();
|
||||||
|
|
||||||
|
/* Init complete, Clear the POR bit */
|
||||||
|
//_max17050_set_por_bit(0); // Should we? Or let the switch to reconfigure POR?
|
||||||
|
|
||||||
|
// Sets POR, BI, BR.
|
||||||
|
_max17050_set_por_bit(0x8801);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
127
source/power/max17050.h
Normal file
127
source/power/max17050.h
Normal file
@ -0,0 +1,127 @@
|
|||||||
|
/*
|
||||||
|
* Fuel gauge driver for Nintendo Switch's Maxim 17050
|
||||||
|
* Note that Maxim 8966 and 8997 are mfd and this is its subdevice.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Samsung Electronics
|
||||||
|
* MyungJoo Ham <myungjoo.ham@samsung.com>
|
||||||
|
* Copyright (C) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __MAX17050_H_
|
||||||
|
#define __MAX17050_H_
|
||||||
|
|
||||||
|
#define MAX17050_STATUS_BattAbsent (1 << 3)
|
||||||
|
#define MAX17050_DEFAULT_SNS_RESISTOR 10000
|
||||||
|
|
||||||
|
/* Consider RepCap which is less then 10 units below FullCAP full */
|
||||||
|
#define MAX17050_FULL_THRESHOLD 10
|
||||||
|
|
||||||
|
#define MAX17050_CHARACTERIZATION_DATA_SIZE 48
|
||||||
|
|
||||||
|
#define MAXIM17050_I2C_ADDR 0x36
|
||||||
|
|
||||||
|
enum MAX17050_reg {
|
||||||
|
MAX17050_STATUS = 0x00,
|
||||||
|
MAX17050_VALRT_Th = 0x01,
|
||||||
|
MAX17050_TALRT_Th = 0x02,
|
||||||
|
MAX17050_SALRT_Th = 0x03,
|
||||||
|
MAX17050_AtRate = 0x04,
|
||||||
|
MAX17050_RepCap = 0x05,
|
||||||
|
MAX17050_RepSOC = 0x06,
|
||||||
|
MAX17050_Age = 0x07,
|
||||||
|
MAX17050_TEMP = 0x08,
|
||||||
|
MAX17050_VCELL = 0x09,
|
||||||
|
MAX17050_Current = 0x0A,
|
||||||
|
MAX17050_AvgCurrent = 0x0B,
|
||||||
|
|
||||||
|
MAX17050_SOC = 0x0D,
|
||||||
|
MAX17050_AvSOC = 0x0E,
|
||||||
|
MAX17050_RemCap = 0x0F,
|
||||||
|
MAX17050_FullCAP = 0x10,
|
||||||
|
MAX17050_TTE = 0x11,
|
||||||
|
MAX17050_QRTbl00 = 0x12,
|
||||||
|
MAX17050_FullSOCThr = 0x13,
|
||||||
|
MAX17050_RSLOW = 0x14,
|
||||||
|
|
||||||
|
MAX17050_AvgTA = 0x16,
|
||||||
|
MAX17050_Cycles = 0x17,
|
||||||
|
MAX17050_DesignCap = 0x18,
|
||||||
|
MAX17050_AvgVCELL = 0x19,
|
||||||
|
MAX17050_MinMaxTemp = 0x1A,
|
||||||
|
MAX17050_MinMaxVolt = 0x1B,
|
||||||
|
MAX17050_MinMaxCurr = 0x1C,
|
||||||
|
MAX17050_CONFIG = 0x1D,
|
||||||
|
MAX17050_ICHGTerm = 0x1E,
|
||||||
|
MAX17050_AvCap = 0x1F,
|
||||||
|
MAX17050_ManName = 0x20,
|
||||||
|
MAX17050_DevName = 0x21,
|
||||||
|
MAX17050_QRTbl10 = 0x22,
|
||||||
|
MAX17050_FullCAPNom = 0x23,
|
||||||
|
MAX17050_TempNom = 0x24,
|
||||||
|
MAX17050_TempLim = 0x25,
|
||||||
|
MAX17050_TempHot = 0x26,
|
||||||
|
MAX17050_AIN = 0x27,
|
||||||
|
MAX17050_LearnCFG = 0x28,
|
||||||
|
MAX17050_FilterCFG = 0x29,
|
||||||
|
MAX17050_RelaxCFG = 0x2A,
|
||||||
|
MAX17050_MiscCFG = 0x2B,
|
||||||
|
MAX17050_TGAIN = 0x2C,
|
||||||
|
MAX17050_TOFF = 0x2D,
|
||||||
|
MAX17050_CGAIN = 0x2E,
|
||||||
|
MAX17050_COFF = 0x2F,
|
||||||
|
|
||||||
|
MAX17050_QRTbl20 = 0x32,
|
||||||
|
MAX17050_SOC_empty = 0x33,
|
||||||
|
MAX17050_T_empty = 0x34,
|
||||||
|
MAX17050_FullCAP0 = 0x35,
|
||||||
|
MAX17050_LAvg_empty = 0x36,
|
||||||
|
MAX17050_FCTC = 0x37,
|
||||||
|
MAX17050_RCOMP0 = 0x38,
|
||||||
|
MAX17050_TempCo = 0x39,
|
||||||
|
MAX17050_V_empty = 0x3A,
|
||||||
|
MAX17050_K_empty0 = 0x3B,
|
||||||
|
MAX17050_TaskPeriod = 0x3C,
|
||||||
|
MAX17050_FSTAT = 0x3D,
|
||||||
|
|
||||||
|
MAX17050_SHDNTIMER = 0x3F,
|
||||||
|
MAX17050_QRTbl30 = 0x42,
|
||||||
|
MAX17050_dQacc = 0x45,
|
||||||
|
MAX17050_dPacc = 0x46,
|
||||||
|
|
||||||
|
MAX17050_VFSOC0 = 0x48,
|
||||||
|
|
||||||
|
MAX17050_QH = 0x4D,
|
||||||
|
MAX17050_QL = 0x4E,
|
||||||
|
|
||||||
|
MAX17050_MinVolt = 0x50, // Custom ID. Not to be sent to i2c.
|
||||||
|
MAX17050_MaxVolt = 0x51, // Custom ID. Not to be sent to i2c.
|
||||||
|
|
||||||
|
MAX17050_VFSOC0Enable = 0x60,
|
||||||
|
|
||||||
|
MAX17050_MODELChrTbl = 0x80,
|
||||||
|
|
||||||
|
MAX17050_OCV = 0xEE,
|
||||||
|
|
||||||
|
MAX17050_OCVInternal = 0xFB,
|
||||||
|
|
||||||
|
MAX17050_VFSOC = 0xFF,
|
||||||
|
};
|
||||||
|
|
||||||
|
int max17050_get_property(enum MAX17050_reg reg, int *value);
|
||||||
|
int max17050_fix_configuration();
|
||||||
|
|
||||||
|
#endif /* __MAX17050_H_ */
|
331
source/power/max77620.h
Normal file
331
source/power/max77620.h
Normal file
@ -0,0 +1,331 @@
|
|||||||
|
/*
|
||||||
|
* Defining registers address and its bit definitions of MAX77620 and MAX20024
|
||||||
|
*
|
||||||
|
* Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
|
||||||
|
* Copyright (c) 2019 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _MFD_MAX77620_H_
|
||||||
|
#define _MFD_MAX77620_H_
|
||||||
|
|
||||||
|
#define MAX77620_I2C_ADDR 0x3C
|
||||||
|
|
||||||
|
/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
|
||||||
|
#define MAX77620_REG_CNFGGLBL1 0x00
|
||||||
|
#define MAX77620_CNFGGLBL1_LBDAC_EN (1 << 7)
|
||||||
|
#define MAX77620_CNFGGLBL1_MPPLD (1 << 6)
|
||||||
|
#define MAX77620_CNFGGLBL1_LBHYST ((1 << 5) | (1 << 4))
|
||||||
|
#define MAX77620_CNFGGLBL1_LBHYST_N (1 << 4)
|
||||||
|
#define MAX77620_CNFGGLBL1_LBDAC 0x0E
|
||||||
|
#define MAX77620_CNFGGLBL1_LBDAC_N (1 << 1)
|
||||||
|
#define MAX77620_CNFGGLBL1_LBRSTEN (1 << 0)
|
||||||
|
|
||||||
|
#define MAX77620_REG_CNFGGLBL2 0x01
|
||||||
|
#define MAX77620_REG_CNFGGLBL3 0x02
|
||||||
|
#define MAX77620_WDTC_MASK 0x3
|
||||||
|
#define MAX77620_WDTOFFC (1 << 4)
|
||||||
|
#define MAX77620_WDTSLPC (1 << 3)
|
||||||
|
#define MAX77620_WDTEN (1 << 2)
|
||||||
|
#define MAX77620_TWD_MASK 0x3
|
||||||
|
#define MAX77620_TWD_2s 0x0
|
||||||
|
#define MAX77620_TWD_16s 0x1
|
||||||
|
#define MAX77620_TWD_64s 0x2
|
||||||
|
#define MAX77620_TWD_128s 0x3
|
||||||
|
|
||||||
|
#define MAX77620_REG_CNFG1_32K 0x03
|
||||||
|
#define MAX77620_CNFG1_32K_OUT0_EN (1 << 2)
|
||||||
|
|
||||||
|
#define MAX77620_REG_CNFGBBC 0x04
|
||||||
|
#define MAX77620_CNFGBBC_ENABLE (1 << 0)
|
||||||
|
#define MAX77620_CNFGBBC_CURRENT_MASK 0x06
|
||||||
|
#define MAX77620_CNFGBBC_CURRENT_SHIFT 1
|
||||||
|
#define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18
|
||||||
|
#define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3
|
||||||
|
#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE (1 << 5)
|
||||||
|
#define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0
|
||||||
|
#define MAX77620_CNFGBBC_RESISTOR_SHIFT 6
|
||||||
|
#define MAX77620_CNFGBBC_RESISTOR_100 (0 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
|
||||||
|
#define MAX77620_CNFGBBC_RESISTOR_1K (1 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
|
||||||
|
#define MAX77620_CNFGBBC_RESISTOR_3K (2 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
|
||||||
|
#define MAX77620_CNFGBBC_RESISTOR_6K (3 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
|
||||||
|
|
||||||
|
#define MAX77620_REG_IRQTOP 0x05
|
||||||
|
#define MAX77620_IRQ_TOP_GLBL_MASK (1 << 7)
|
||||||
|
#define MAX77620_IRQ_TOP_SD_MASK (1 << 6)
|
||||||
|
#define MAX77620_IRQ_TOP_LDO_MASK (1 << 5)
|
||||||
|
#define MAX77620_IRQ_TOP_GPIO_MASK (1 << 4)
|
||||||
|
#define MAX77620_IRQ_TOP_RTC_MASK (1 << 3)
|
||||||
|
#define MAX77620_IRQ_TOP_32K_MASK (1 << 2)
|
||||||
|
#define MAX77620_IRQ_TOP_ONOFF_MASK (1 << 1)
|
||||||
|
|
||||||
|
#define MAX77620_REG_INTLBT 0x06
|
||||||
|
#define MAX77620_REG_IRQTOPM 0x0D
|
||||||
|
#define MAX77620_IRQ_LBM_MASK (1 << 3)
|
||||||
|
#define MAX77620_IRQ_TJALRM1_MASK (1 << 2)
|
||||||
|
#define MAX77620_IRQ_TJALRM2_MASK (1 << 1)
|
||||||
|
|
||||||
|
#define MAX77620_REG_IRQSD 0x07
|
||||||
|
#define MAX77620_REG_IRQ_LVL2_L0_7 0x08
|
||||||
|
#define MAX77620_REG_IRQ_LVL2_L8 0x09
|
||||||
|
#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A
|
||||||
|
#define MAX77620_REG_ONOFFIRQ 0x0B
|
||||||
|
#define MAX77620_REG_NVERC 0x0C
|
||||||
|
|
||||||
|
#define MAX77620_REG_INTENLBT 0x0E
|
||||||
|
#define MAX77620_GLBLM_MASK (1 << 0)
|
||||||
|
|
||||||
|
#define MAX77620_REG_IRQMASKSD 0x0F
|
||||||
|
#define MAX77620_REG_IRQ_MSK_L0_7 0x10
|
||||||
|
#define MAX77620_REG_IRQ_MSK_L8 0x11
|
||||||
|
#define MAX77620_REG_ONOFFIRQM 0x12
|
||||||
|
#define MAX77620_REG_STATLBT 0x13
|
||||||
|
#define MAX77620_REG_STATSD 0x14
|
||||||
|
#define MAX77620_REG_ONOFFSTAT 0x15
|
||||||
|
|
||||||
|
/* SD and LDO Registers */
|
||||||
|
#define MAX77620_REG_SD0 0x16
|
||||||
|
#define MAX77620_REG_SD1 0x17
|
||||||
|
#define MAX77620_REG_SD2 0x18
|
||||||
|
#define MAX77620_REG_SD3 0x19
|
||||||
|
#define MAX77620_REG_SD4 0x1A
|
||||||
|
#define MAX77620_SDX_VOLT_MASK 0xFF
|
||||||
|
#define MAX77620_SD0_VOLT_MASK 0x3F
|
||||||
|
#define MAX77620_SD1_VOLT_MASK 0x7F
|
||||||
|
#define MAX77620_LDO_VOLT_MASK 0x3F
|
||||||
|
#define MAX77620_REG_DVSSD0 0x1B
|
||||||
|
#define MAX77620_REG_DVSSD1 0x1C
|
||||||
|
#define MAX77620_REG_SD0_CFG 0x1D
|
||||||
|
#define MAX77620_REG_SD1_CFG 0x1E
|
||||||
|
#define MAX77620_REG_SD2_CFG 0x1F
|
||||||
|
#define MAX77620_REG_SD3_CFG 0x20
|
||||||
|
#define MAX77620_REG_SD4_CFG 0x21
|
||||||
|
#define MAX77620_REG_SD_CFG2 0x22
|
||||||
|
#define MAX77620_REG_LDO0_CFG 0x23
|
||||||
|
#define MAX77620_REG_LDO0_CFG2 0x24
|
||||||
|
#define MAX77620_REG_LDO1_CFG 0x25
|
||||||
|
#define MAX77620_REG_LDO1_CFG2 0x26
|
||||||
|
#define MAX77620_REG_LDO2_CFG 0x27
|
||||||
|
#define MAX77620_REG_LDO2_CFG2 0x28
|
||||||
|
#define MAX77620_REG_LDO3_CFG 0x29
|
||||||
|
#define MAX77620_REG_LDO3_CFG2 0x2A
|
||||||
|
#define MAX77620_REG_LDO4_CFG 0x2B
|
||||||
|
#define MAX77620_REG_LDO4_CFG2 0x2C
|
||||||
|
#define MAX77620_REG_LDO5_CFG 0x2D
|
||||||
|
#define MAX77620_REG_LDO5_CFG2 0x2E
|
||||||
|
#define MAX77620_REG_LDO6_CFG 0x2F
|
||||||
|
#define MAX77620_REG_LDO6_CFG2 0x30
|
||||||
|
#define MAX77620_REG_LDO7_CFG 0x31
|
||||||
|
#define MAX77620_REG_LDO7_CFG2 0x32
|
||||||
|
#define MAX77620_REG_LDO8_CFG 0x33
|
||||||
|
#define MAX77620_REG_LDO8_CFG2 0x34
|
||||||
|
#define MAX77620_LDO_POWER_MODE_MASK 0xC0
|
||||||
|
#define MAX77620_LDO_POWER_MODE_SHIFT 6
|
||||||
|
#define MAX77620_POWER_MODE_NORMAL 3
|
||||||
|
#define MAX77620_POWER_MODE_LPM 2
|
||||||
|
#define MAX77620_POWER_MODE_GLPM 1
|
||||||
|
#define MAX77620_POWER_MODE_DISABLE 0
|
||||||
|
#define MAX20024_LDO_CFG2_MPOK_MASK (1 << 2)
|
||||||
|
#define MAX77620_LDO_CFG2_ADE_MASK (1 << 1)
|
||||||
|
#define MAX77620_LDO_CFG2_ADE_DISABLE 0
|
||||||
|
#define MAX77620_LDO_CFG2_ADE_ENABLE (1 << 1)
|
||||||
|
#define MAX77620_LDO_CFG2_SS_MASK (1 << 0)
|
||||||
|
#define MAX77620_LDO_CFG2_SS_FAST (1 << 0)
|
||||||
|
#define MAX77620_LDO_CFG2_SS_SLOW 0
|
||||||
|
|
||||||
|
#define MAX77620_REG_LDO_CFG3 0x35
|
||||||
|
#define MAX77620_TRACK4_MASK (1 << 5)
|
||||||
|
#define MAX77620_TRACK4_SHIFT 5
|
||||||
|
|
||||||
|
#define MAX77620_LDO_SLEW_RATE_MASK 0x1
|
||||||
|
|
||||||
|
#define MAX77620_REG_GPIO0 0x36
|
||||||
|
#define MAX77620_REG_GPIO1 0x37
|
||||||
|
#define MAX77620_REG_GPIO2 0x38
|
||||||
|
#define MAX77620_REG_GPIO3 0x39
|
||||||
|
#define MAX77620_REG_GPIO4 0x3A
|
||||||
|
#define MAX77620_REG_GPIO5 0x3B
|
||||||
|
#define MAX77620_REG_GPIO6 0x3C
|
||||||
|
#define MAX77620_REG_GPIO7 0x3D
|
||||||
|
#define MAX77620_REG_PUE_GPIO 0x3E
|
||||||
|
#define MAX77620_REG_PDE_GPIO 0x3F
|
||||||
|
#define MAX77620_REG_AME_GPIO 0x40
|
||||||
|
|
||||||
|
#define MAX77620_REG_ONOFFCNFG1 0x41
|
||||||
|
#define MAX77620_ONOFFCNFG1_SFT_RST (1 << 7)
|
||||||
|
#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38
|
||||||
|
#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3
|
||||||
|
#define MAX77620_ONOFFCNFG1_SLPEN (1 << 2)
|
||||||
|
#define MAX77620_ONOFFCNFG1_PWR_OFF (1 << 1)
|
||||||
|
#define MAX20024_ONOFFCNFG1_CLRSE 0x18
|
||||||
|
|
||||||
|
#define MAX77620_REG_ONOFFCNFG2 0x42
|
||||||
|
#define MAX77620_ONOFFCNFG2_SFT_RST_WK (1 << 7)
|
||||||
|
#define MAX77620_ONOFFCNFG2_WD_RST_WK (1 << 6)
|
||||||
|
#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK (1 << 5)
|
||||||
|
#define MAX77620_ONOFFCNFG2_WK_ALARM1 (1 << 2)
|
||||||
|
#define MAX77620_ONOFFCNFG2_WK_EN0 (1 << 0)
|
||||||
|
|
||||||
|
/* FPS Registers */
|
||||||
|
#define MAX77620_REG_FPS_CFG0 0x43
|
||||||
|
#define MAX77620_REG_FPS_CFG1 0x44
|
||||||
|
#define MAX77620_REG_FPS_CFG2 0x45
|
||||||
|
#define MAX77620_REG_FPS_LDO0 0x46
|
||||||
|
#define MAX77620_REG_FPS_LDO1 0x47
|
||||||
|
#define MAX77620_REG_FPS_LDO2 0x48
|
||||||
|
#define MAX77620_REG_FPS_LDO3 0x49
|
||||||
|
#define MAX77620_REG_FPS_LDO4 0x4A
|
||||||
|
#define MAX77620_REG_FPS_LDO5 0x4B
|
||||||
|
#define MAX77620_REG_FPS_LDO6 0x4C
|
||||||
|
#define MAX77620_REG_FPS_LDO7 0x4D
|
||||||
|
#define MAX77620_REG_FPS_LDO8 0x4E
|
||||||
|
#define MAX77620_REG_FPS_SD0 0x4F
|
||||||
|
#define MAX77620_REG_FPS_SD1 0x50
|
||||||
|
#define MAX77620_REG_FPS_SD2 0x51
|
||||||
|
#define MAX77620_REG_FPS_SD3 0x52
|
||||||
|
#define MAX77620_REG_FPS_SD4 0x53
|
||||||
|
#define MAX77620_REG_FPS_NONE 0
|
||||||
|
#define MAX77620_FPS_SRC_MASK 0xC0
|
||||||
|
#define MAX77620_FPS_SRC_SHIFT 6
|
||||||
|
#define MAX77620_FPS_PU_PERIOD_MASK 0x38
|
||||||
|
#define MAX77620_FPS_PU_PERIOD_SHIFT 3
|
||||||
|
#define MAX77620_FPS_PD_PERIOD_MASK 0x07
|
||||||
|
#define MAX77620_FPS_PD_PERIOD_SHIFT 0
|
||||||
|
|
||||||
|
/* Minimum and maximum FPS period time (in microseconds) are
|
||||||
|
* different for MAX77620 and Max20024.
|
||||||
|
*/
|
||||||
|
#define MAX77620_FPS_COUNT 3
|
||||||
|
|
||||||
|
#define MAX77620_FPS_PERIOD_MIN_US 40
|
||||||
|
#define MAX20024_FPS_PERIOD_MIN_US 20
|
||||||
|
|
||||||
|
#define MAX77620_FPS_PERIOD_MAX_US 2560
|
||||||
|
#define MAX20024_FPS_PERIOD_MAX_US 5120
|
||||||
|
|
||||||
|
#define MAX77620_REG_FPS_GPIO1 0x54
|
||||||
|
#define MAX77620_REG_FPS_GPIO2 0x55
|
||||||
|
#define MAX77620_REG_FPS_GPIO3 0x56
|
||||||
|
#define MAX77620_FPS_TIME_PERIOD_MASK 0x38
|
||||||
|
#define MAX77620_FPS_TIME_PERIOD_SHIFT 3
|
||||||
|
#define MAX77620_FPS_EN_SRC_MASK 0x06
|
||||||
|
#define MAX77620_FPS_EN_SRC_SHIFT 1
|
||||||
|
#define MAX77620_FPS_ENFPS_SW_MASK 0x01
|
||||||
|
#define MAX77620_FPS_ENFPS_SW 0x01
|
||||||
|
|
||||||
|
#define MAX77620_REG_FPS_RSO 0x57
|
||||||
|
#define MAX77620_REG_CID0 0x58
|
||||||
|
#define MAX77620_REG_CID1 0x59
|
||||||
|
#define MAX77620_REG_CID2 0x5A
|
||||||
|
#define MAX77620_REG_CID3 0x5B
|
||||||
|
#define MAX77620_REG_CID4 0x5C
|
||||||
|
#define MAX77620_REG_CID5 0x5D
|
||||||
|
|
||||||
|
#define MAX77620_REG_DVSSD4 0x5E
|
||||||
|
#define MAX20024_REG_MAX_ADD 0x70
|
||||||
|
|
||||||
|
#define MAX77620_CID_DIDM_MASK 0xF0
|
||||||
|
#define MAX77620_CID_DIDM_SHIFT 4
|
||||||
|
|
||||||
|
/* CNCG2SD */
|
||||||
|
#define MAX77620_SD_CNF2_ROVS_EN_SD1 (1 << 1)
|
||||||
|
#define MAX77620_SD_CNF2_ROVS_EN_SD0 (1 << 2)
|
||||||
|
|
||||||
|
/* Device Identification Metal */
|
||||||
|
#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
|
||||||
|
/* Device Indentification OTP */
|
||||||
|
#define MAX77620_CID5_DIDO(n) ((n) & 0xF)
|
||||||
|
|
||||||
|
/* SD CNFG1 */
|
||||||
|
#define MAX77620_SD_SR_MASK 0xC0
|
||||||
|
#define MAX77620_SD_SR_SHIFT 6
|
||||||
|
#define MAX77620_SD_POWER_MODE_MASK 0x30
|
||||||
|
#define MAX77620_SD_POWER_MODE_SHIFT 4
|
||||||
|
#define MAX77620_SD_CFG1_ADE_MASK (1 << 3)
|
||||||
|
#define MAX77620_SD_CFG1_ADE_DISABLE 0
|
||||||
|
#define MAX77620_SD_CFG1_ADE_ENABLE (1 << 3)
|
||||||
|
#define MAX77620_SD_FPWM_MASK 0x04
|
||||||
|
#define MAX77620_SD_FPWM_SHIFT 2
|
||||||
|
#define MAX77620_SD_FSRADE_MASK 0x01
|
||||||
|
#define MAX77620_SD_FSRADE_SHIFT 0
|
||||||
|
#define MAX77620_SD_CFG1_FPWM_SD_MASK (1 << 2)
|
||||||
|
#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0
|
||||||
|
#define MAX77620_SD_CFG1_FPWM_SD_FPWM (1 << 2)
|
||||||
|
#define MAX20024_SD_CFG1_MPOK_MASK (1 << 1)
|
||||||
|
#define MAX77620_SD_CFG1_FSRADE_SD_MASK (1 << 0)
|
||||||
|
#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0
|
||||||
|
#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE (1 << 0)
|
||||||
|
|
||||||
|
#define MAX77620_CNFG_GPIO_DRV_MASK (1 << 0)
|
||||||
|
#define MAX77620_CNFG_GPIO_DRV_PUSHPULL (1 << 0)
|
||||||
|
#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0
|
||||||
|
#define MAX77620_CNFG_GPIO_DIR_MASK (1 << 1)
|
||||||
|
#define MAX77620_CNFG_GPIO_DIR_INPUT (1 << 1)
|
||||||
|
#define MAX77620_CNFG_GPIO_DIR_OUTPUT 0
|
||||||
|
#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK (1 << 2)
|
||||||
|
#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK (1 << 3)
|
||||||
|
#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH (1 << 3)
|
||||||
|
#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0
|
||||||
|
#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4)
|
||||||
|
#define MAX77620_CNFG_GPIO_INT_FALLING (1 << 4)
|
||||||
|
#define MAX77620_CNFG_GPIO_INT_RISING (1 << 5)
|
||||||
|
#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6)
|
||||||
|
#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6)
|
||||||
|
#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6)
|
||||||
|
#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6)
|
||||||
|
#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6)
|
||||||
|
|
||||||
|
#define MAX77620_IRQ_LVL2_GPIO_EDGE0 (1 << 0)
|
||||||
|
#define MAX77620_IRQ_LVL2_GPIO_EDGE1 (1 << 1)
|
||||||
|
#define MAX77620_IRQ_LVL2_GPIO_EDGE2 (1 << 2)
|
||||||
|
#define MAX77620_IRQ_LVL2_GPIO_EDGE3 (1 << 3)
|
||||||
|
#define MAX77620_IRQ_LVL2_GPIO_EDGE4 (1 << 4)
|
||||||
|
#define MAX77620_IRQ_LVL2_GPIO_EDGE5 (1 << 5)
|
||||||
|
#define MAX77620_IRQ_LVL2_GPIO_EDGE6 (1 << 6)
|
||||||
|
#define MAX77620_IRQ_LVL2_GPIO_EDGE7 (1 << 7)
|
||||||
|
|
||||||
|
/* Interrupts */
|
||||||
|
enum {
|
||||||
|
MAX77620_IRQ_TOP_GLBL, /* Low-Battery */
|
||||||
|
MAX77620_IRQ_TOP_SD, /* SD power fail */
|
||||||
|
MAX77620_IRQ_TOP_LDO, /* LDO power fail */
|
||||||
|
MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */
|
||||||
|
MAX77620_IRQ_TOP_RTC, /* RTC */
|
||||||
|
MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */
|
||||||
|
MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */
|
||||||
|
MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */
|
||||||
|
MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */
|
||||||
|
MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* GPIOs */
|
||||||
|
enum {
|
||||||
|
MAX77620_GPIO0,
|
||||||
|
MAX77620_GPIO1,
|
||||||
|
MAX77620_GPIO2,
|
||||||
|
MAX77620_GPIO3,
|
||||||
|
MAX77620_GPIO4,
|
||||||
|
MAX77620_GPIO5,
|
||||||
|
MAX77620_GPIO6,
|
||||||
|
MAX77620_GPIO7,
|
||||||
|
MAX77620_GPIO_NR,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* FPS Source */
|
||||||
|
enum max77620_fps_src {
|
||||||
|
MAX77620_FPS_SRC_0,
|
||||||
|
MAX77620_FPS_SRC_1,
|
||||||
|
MAX77620_FPS_SRC_2,
|
||||||
|
MAX77620_FPS_SRC_NONE,
|
||||||
|
MAX77620_FPS_SRC_DEF,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum max77620_chip_id {
|
||||||
|
MAX77620,
|
||||||
|
MAX20024,
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* _MFD_MAX77620_H_ */
|
165
source/power/max7762x.c
Normal file
165
source/power/max7762x.c
Normal file
@ -0,0 +1,165 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (c) 2019 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "max7762x.h"
|
||||||
|
#include "max77620.h"
|
||||||
|
#include "../soc/i2c.h"
|
||||||
|
#include "../utils/util.h"
|
||||||
|
|
||||||
|
#define REGULATOR_SD 0
|
||||||
|
#define REGULATOR_LDO 1
|
||||||
|
|
||||||
|
typedef struct _max77620_regulator_t
|
||||||
|
{
|
||||||
|
u8 type;
|
||||||
|
const char *name;
|
||||||
|
u8 reg_sd;
|
||||||
|
|
||||||
|
u32 mv_step;
|
||||||
|
u32 mv_min;
|
||||||
|
u32 mv_default;
|
||||||
|
u32 mv_max;
|
||||||
|
|
||||||
|
u8 volt_addr;
|
||||||
|
u8 cfg_addr;
|
||||||
|
|
||||||
|
u8 volt_mask;
|
||||||
|
u8 enable_mask;
|
||||||
|
u8 enable_shift;
|
||||||
|
u8 status_mask;
|
||||||
|
|
||||||
|
u8 fps_addr;
|
||||||
|
u8 fps_src;
|
||||||
|
u8 pd_period;
|
||||||
|
u8 pu_period;
|
||||||
|
} max77620_regulator_t;
|
||||||
|
|
||||||
|
static const max77620_regulator_t _pmic_regulators[] = {
|
||||||
|
{ REGULATOR_SD, "sd0", 0x16, 12500, 600000, 625000, 1400000, MAX77620_REG_SD0, MAX77620_REG_SD0_CFG, MAX77620_SD0_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK, MAX77620_SD_POWER_MODE_SHIFT, 0x80, MAX77620_REG_FPS_SD0, 1, 7, 1 },
|
||||||
|
{ REGULATOR_SD, "sd1", 0x17, 12500, 600000, 1125000, 1125000, MAX77620_REG_SD1, MAX77620_REG_SD1_CFG, MAX77620_SD1_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK, MAX77620_SD_POWER_MODE_SHIFT, 0x40, MAX77620_REG_FPS_SD1, 0, 1, 5 },
|
||||||
|
{ REGULATOR_SD, "sd2", 0x18, 12500, 600000, 1325000, 1350000, MAX77620_REG_SD2, MAX77620_REG_SD2_CFG, MAX77620_SDX_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK, MAX77620_SD_POWER_MODE_SHIFT, 0x20, MAX77620_REG_FPS_SD2, 1, 5, 2 },
|
||||||
|
{ REGULATOR_SD, "sd3", 0x19, 12500, 600000, 1800000, 1800000, MAX77620_REG_SD3, MAX77620_REG_SD3_CFG, MAX77620_SDX_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK, MAX77620_SD_POWER_MODE_SHIFT, 0x10, MAX77620_REG_FPS_SD3, 0, 3, 3 },
|
||||||
|
{ REGULATOR_LDO, "ldo0", 0x00, 25000, 800000, 1200000, 1200000, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO0, 3, 7, 0 },
|
||||||
|
{ REGULATOR_LDO, "ldo1", 0x00, 25000, 800000, 1050000, 1050000, MAX77620_REG_LDO1_CFG, MAX77620_REG_LDO1_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO1, 3, 7, 0 },
|
||||||
|
{ REGULATOR_LDO, "ldo2", 0x00, 50000, 800000, 1800000, 3300000, MAX77620_REG_LDO2_CFG, MAX77620_REG_LDO2_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO2, 3, 7, 0 },
|
||||||
|
{ REGULATOR_LDO, "ldo3", 0x00, 50000, 800000, 3100000, 3100000, MAX77620_REG_LDO3_CFG, MAX77620_REG_LDO3_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO3, 3, 7, 0 },
|
||||||
|
{ REGULATOR_LDO, "ldo4", 0x00, 12500, 800000, 850000, 850000, MAX77620_REG_LDO4_CFG, MAX77620_REG_LDO4_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO4, 0, 7, 1 },
|
||||||
|
{ REGULATOR_LDO, "ldo5", 0x00, 50000, 800000, 1800000, 1800000, MAX77620_REG_LDO5_CFG, MAX77620_REG_LDO5_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO5, 3, 7, 0 },
|
||||||
|
{ REGULATOR_LDO, "ldo6", 0x00, 50000, 800000, 2900000, 2900000, MAX77620_REG_LDO6_CFG, MAX77620_REG_LDO6_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO6, 3, 7, 0 },
|
||||||
|
{ REGULATOR_LDO, "ldo7", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO7, 1, 4, 3 },
|
||||||
|
{ REGULATOR_LDO, "ldo8", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00, MAX77620_REG_FPS_LDO8, 3, 7, 0 }
|
||||||
|
};
|
||||||
|
|
||||||
|
int max77620_regulator_get_status(u32 id)
|
||||||
|
{
|
||||||
|
if (id > REGULATOR_MAX)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||||
|
|
||||||
|
if (reg->type == REGULATOR_SD)
|
||||||
|
return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_STATSD) & reg->status_mask) ? 0 : 1;
|
||||||
|
return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg->cfg_addr) & 8) ? 1 : 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int max77620_regulator_config_fps(u32 id)
|
||||||
|
{
|
||||||
|
if (id > REGULATOR_MAX)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||||
|
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, reg->fps_addr,
|
||||||
|
(reg->fps_src << MAX77620_FPS_SRC_SHIFT) | (reg->pu_period << MAX77620_FPS_PU_PERIOD_SHIFT) | (reg->pd_period));
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int max77620_regulator_set_voltage(u32 id, u32 mv)
|
||||||
|
{
|
||||||
|
if (id > REGULATOR_MAX)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||||
|
|
||||||
|
if (mv < reg->mv_min || mv > reg->mv_max)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
u32 mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step;
|
||||||
|
u8 val = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg->volt_addr);
|
||||||
|
val = (val & ~reg->volt_mask) | (mult & reg->volt_mask);
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, reg->volt_addr, val);
|
||||||
|
usleep(1000);
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int max77620_regulator_enable(u32 id, int enable)
|
||||||
|
{
|
||||||
|
if (id > REGULATOR_MAX)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||||
|
|
||||||
|
u32 addr = reg->type == REGULATOR_SD ? reg->cfg_addr : reg->volt_addr;
|
||||||
|
u8 val = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, addr);
|
||||||
|
if (enable)
|
||||||
|
val = (val & ~reg->enable_mask) | ((MAX77620_POWER_MODE_NORMAL << reg->enable_shift) & reg->enable_mask);
|
||||||
|
else
|
||||||
|
val &= ~reg->enable_mask;
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, addr, val);
|
||||||
|
usleep(1000);
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int max77620_regulator_set_volt_and_flags(u32 id, u32 mv, u8 flags)
|
||||||
|
{
|
||||||
|
if (id > REGULATOR_MAX)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||||
|
|
||||||
|
if (mv < reg->mv_min || mv > reg->mv_max)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
u32 mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step;
|
||||||
|
u8 val = ((flags << reg->enable_shift) & ~reg->volt_mask) | (mult & reg->volt_mask);
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, reg->volt_addr, val);
|
||||||
|
usleep(1000);
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void max77620_config_default()
|
||||||
|
{
|
||||||
|
for (u32 i = 1; i <= REGULATOR_MAX; i++)
|
||||||
|
{
|
||||||
|
i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CID4);
|
||||||
|
max77620_regulator_config_fps(i);
|
||||||
|
max77620_regulator_set_voltage(i, _pmic_regulators[i].mv_default);
|
||||||
|
if (_pmic_regulators[i].fps_src != MAX77620_FPS_SRC_NONE)
|
||||||
|
max77620_regulator_enable(i, 1);
|
||||||
|
}
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD_CFG2, 4);
|
||||||
|
}
|
||||||
|
|
||||||
|
void max77620_low_battery_monitor_config()
|
||||||
|
{
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CNFGGLBL1,
|
||||||
|
MAX77620_CNFGGLBL1_LBDAC_EN | MAX77620_CNFGGLBL1_LBHYST_N | MAX77620_CNFGGLBL1_LBDAC_N);
|
||||||
|
}
|
116
source/power/max7762x.h
Normal file
116
source/power/max7762x.h
Normal file
@ -0,0 +1,116 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (c) 2019 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _MAX7762X_H_
|
||||||
|
#define _MAX7762X_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Switch Power domains (max77620):
|
||||||
|
* Name | Usage | uV step | uV min | uV default | uV max | Init
|
||||||
|
*-------+---------------+---------+--------+------------+---------+------------------
|
||||||
|
* sd0 | core | 12500 | 600000 | 625000 | 1400000 | 1.125V (pkg1.1)
|
||||||
|
* sd1 | SDRAM | 12500 | 600000 | 1125000 | 1125000 | 1.1V (pkg1.1)
|
||||||
|
* sd2 | ldo{0-1, 7-8} | 12500 | 600000 | 1325000 | 1350000 | 1.325V (pcv)
|
||||||
|
* sd3 | 1.8V general | 12500 | 600000 | 1800000 | 1800000 |
|
||||||
|
* ldo0 | Display Panel | 25000 | 800000 | 1200000 | 1200000 | 1.2V (pkg1.1)
|
||||||
|
* ldo1 | XUSB, PCIE | 25000 | 800000 | 1050000 | 1050000 | 1.05V (pcv)
|
||||||
|
* ldo2 | SDMMC1 | 50000 | 800000 | 1800000 | 3300000 |
|
||||||
|
* ldo3 | GC ASIC | 50000 | 800000 | 3100000 | 3100000 | 3.1V (pcv)
|
||||||
|
* ldo4 | RTC | 12500 | 800000 | 850000 | 850000 |
|
||||||
|
* ldo5 | GC ASIC | 50000 | 800000 | 1800000 | 1800000 | 1.8V (pcv)
|
||||||
|
* ldo6 | Touch, ALS | 50000 | 800000 | 2900000 | 2900000 | 2.9V
|
||||||
|
* ldo7 | XUSB | 50000 | 800000 | 1050000 | 1050000 |
|
||||||
|
* ldo8 | XUSB, DC | 50000 | 800000 | 1050000 | 1050000 |
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MAX77620_AME_GPIO: control GPIO modes (bits 0 - 7 correspond to GPIO0 - GPIO7); 0 -> GPIO, 1 -> alt-mode
|
||||||
|
* MAX77620_REG_GPIOx: 0x9 sets output and enable
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*! MAX77620 partitions. */
|
||||||
|
#define REGULATOR_SD0 0
|
||||||
|
#define REGULATOR_SD1 1
|
||||||
|
#define REGULATOR_SD2 2
|
||||||
|
#define REGULATOR_SD3 3
|
||||||
|
#define REGULATOR_LDO0 4
|
||||||
|
#define REGULATOR_LDO1 5
|
||||||
|
#define REGULATOR_LDO2 6
|
||||||
|
#define REGULATOR_LDO3 7
|
||||||
|
#define REGULATOR_LDO4 8
|
||||||
|
#define REGULATOR_LDO5 9
|
||||||
|
#define REGULATOR_LDO6 10
|
||||||
|
#define REGULATOR_LDO7 11
|
||||||
|
#define REGULATOR_LDO8 12
|
||||||
|
#define REGULATOR_MAX 12
|
||||||
|
|
||||||
|
#define MAX77621_CPU_I2C_ADDR 0x1B
|
||||||
|
#define MAX77621_GPU_I2C_ADDR 0x1C
|
||||||
|
|
||||||
|
#define MAX77621_VOUT_REG 0
|
||||||
|
#define MAX77621_VOUT_DVC_REG 1
|
||||||
|
#define MAX77621_CONTROL1_REG 2
|
||||||
|
#define MAX77621_CONTROL2_REG 3
|
||||||
|
|
||||||
|
/* MAX77621_VOUT */
|
||||||
|
#define MAX77621_VOUT_ENABLE (1 << 7)
|
||||||
|
#define MAX77621_VOUT_MASK 0x7F
|
||||||
|
|
||||||
|
/* MAX77621_VOUT_DVC_DVS */
|
||||||
|
#define MAX77621_DVS_VOUT_MASK 0x7F
|
||||||
|
|
||||||
|
/* MAX77621_CONTROL1 */
|
||||||
|
#define MAX77621_SNS_ENABLE (1 << 7)
|
||||||
|
#define MAX77621_FPWM_EN_M (1 << 6)
|
||||||
|
#define MAX77621_NFSR_ENABLE (1 << 5)
|
||||||
|
#define MAX77621_AD_ENABLE (1 << 4)
|
||||||
|
#define MAX77621_BIAS_ENABLE (1 << 3)
|
||||||
|
#define MAX77621_FREQSHIFT_9PER (1 << 2)
|
||||||
|
|
||||||
|
#define MAX77621_RAMP_12mV_PER_US 0x0
|
||||||
|
#define MAX77621_RAMP_25mV_PER_US 0x1
|
||||||
|
#define MAX77621_RAMP_50mV_PER_US 0x2
|
||||||
|
#define MAX77621_RAMP_200mV_PER_US 0x3
|
||||||
|
#define MAX77621_RAMP_MASK 0x3
|
||||||
|
|
||||||
|
/* MAX77621_CONTROL2 */
|
||||||
|
#define MAX77621_WDTMR_ENABLE (1 << 6)
|
||||||
|
#define MAX77621_DISCH_ENBABLE (1 << 5)
|
||||||
|
#define MAX77621_FT_ENABLE (1 << 4)
|
||||||
|
#define MAX77621_T_JUNCTION_120 (1 << 7)
|
||||||
|
|
||||||
|
#define MAX77621_CKKADV_TRIP_DISABLE 0xC
|
||||||
|
#define MAX77621_CKKADV_TRIP_75mV_PER_US 0x0
|
||||||
|
#define MAX77621_CKKADV_TRIP_150mV_PER_US 0x4
|
||||||
|
#define MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS 0x8
|
||||||
|
|
||||||
|
#define MAX77621_INDUCTOR_MIN_30_PER 0x0
|
||||||
|
#define MAX77621_INDUCTOR_NOMINAL 0x1
|
||||||
|
#define MAX77621_INDUCTOR_PLUS_30_PER 0x2
|
||||||
|
#define MAX77621_INDUCTOR_PLUS_60_PER 0x3
|
||||||
|
|
||||||
|
int max77620_regulator_get_status(u32 id);
|
||||||
|
int max77620_regulator_config_fps(u32 id);
|
||||||
|
int max77620_regulator_set_voltage(u32 id, u32 mv);
|
||||||
|
int max77620_regulator_enable(u32 id, int enable);
|
||||||
|
int max77620_regulator_set_volt_and_flags(u32 id, u32 mv, u8 flags);
|
||||||
|
void max77620_config_default();
|
||||||
|
void max77620_low_battery_monitor_config();
|
||||||
|
|
||||||
|
#endif
|
77
source/rtc/max77620-rtc.c
Normal file
77
source/rtc/max77620-rtc.c
Normal file
@ -0,0 +1,77 @@
|
|||||||
|
/*
|
||||||
|
* PMIC Real Time Clock driver for Nintendo Switch's MAX77620-RTC
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "max77620-rtc.h"
|
||||||
|
#include "../soc/i2c.h"
|
||||||
|
#include "../utils/util.h"
|
||||||
|
|
||||||
|
void max77620_rtc_get_time(rtc_time_t *time)
|
||||||
|
{
|
||||||
|
u8 val = 0;
|
||||||
|
|
||||||
|
// Update RTC regs from RTC clock.
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_READ_UPDATE);
|
||||||
|
|
||||||
|
// Get control reg config.
|
||||||
|
val = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_CONTROL_REG);
|
||||||
|
// TODO: Check for binary format also?
|
||||||
|
|
||||||
|
// Get time.
|
||||||
|
time->sec = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_SEC_REG) & 0x7F;
|
||||||
|
time->min = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_MIN_REG) & 0x7F;
|
||||||
|
|
||||||
|
time->hour = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_HOUR_REG) & 0x1F;
|
||||||
|
|
||||||
|
if (!(val & MAX77620_RTC_24H) && time->hour & MAX77620_RTC_HOUR_PM_MASK)
|
||||||
|
time->hour = (time->hour & 0xF) + 12;
|
||||||
|
|
||||||
|
// Get day of week. 1: Monday to 7: Sunday.
|
||||||
|
time->weekday = 0;
|
||||||
|
val = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_WEEKDAY_REG);
|
||||||
|
for (int i = 0; i < 8; i++)
|
||||||
|
{
|
||||||
|
time->weekday++;
|
||||||
|
if (val & 1)
|
||||||
|
break;
|
||||||
|
val >>= 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Get date.
|
||||||
|
time->date = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_DATE_REG) & 0x1f;
|
||||||
|
time->month = (i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_MONTH_REG) & 0xF) - 1;
|
||||||
|
time->year = (i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_YEAR_REG) & 0x7F) + 2000;
|
||||||
|
}
|
||||||
|
|
||||||
|
void max77620_rtc_stop_alarm()
|
||||||
|
{
|
||||||
|
u8 val = 0;
|
||||||
|
|
||||||
|
// Update RTC regs from RTC clock.
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_READ_UPDATE);
|
||||||
|
|
||||||
|
// Stop alarm for both ALARM1 and ALARM2. Horizon uses ALARM2.
|
||||||
|
for (int i = 0; i < (MAX77620_RTC_NR_TIME_REGS * 2); i++)
|
||||||
|
{
|
||||||
|
val = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_SEC_REG + i);
|
||||||
|
val &= ~MAX77620_RTC_ALARM_EN_MASK;
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_SEC_REG + i, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
// Update RTC clock from RTC regs.
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_WRITE_UPDATE);
|
||||||
|
}
|
75
source/rtc/max77620-rtc.h
Normal file
75
source/rtc/max77620-rtc.h
Normal file
@ -0,0 +1,75 @@
|
|||||||
|
/*
|
||||||
|
* PMIC Real Time Clock driver for Nintendo Switch's MAX77620-RTC
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _MFD_MAX77620_RTC_H_
|
||||||
|
#define _MFD_MAX77620_RTC_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
#define MAX77620_RTC_I2C_ADDR 0x68
|
||||||
|
|
||||||
|
#define MAX77620_RTC_NR_TIME_REGS 7
|
||||||
|
|
||||||
|
#define MAX77620_RTC_CONTROLM_REG 0x02
|
||||||
|
#define MAX77620_RTC_CONTROL_REG 0x03
|
||||||
|
#define MAX77620_RTC_BIN_FORMAT (1 << 0)
|
||||||
|
#define MAX77620_RTC_24H (1 << 1)
|
||||||
|
|
||||||
|
#define MAX77620_RTC_UPDATE0_REG 0x04
|
||||||
|
#define MAX77620_RTC_WRITE_UPDATE (1 << 0)
|
||||||
|
#define MAX77620_RTC_READ_UPDATE (1 << 4)
|
||||||
|
|
||||||
|
#define MAX77620_RTC_SEC_REG 0x07
|
||||||
|
#define MAX77620_RTC_MIN_REG 0x08
|
||||||
|
#define MAX77620_RTC_HOUR_REG 0x09
|
||||||
|
#define MAX77620_RTC_HOUR_PM_MASK (1 << 6)
|
||||||
|
#define MAX77620_RTC_WEEKDAY_REG 0x0A
|
||||||
|
#define MAX77620_RTC_MONTH_REG 0x0B
|
||||||
|
#define MAX77620_RTC_YEAR_REG 0x0C
|
||||||
|
#define MAX77620_RTC_DATE_REG 0x0D
|
||||||
|
|
||||||
|
#define MAX77620_ALARM1_SEC_REG 0x0E
|
||||||
|
#define MAX77620_ALARM1_MIN_REG 0x0F
|
||||||
|
#define MAX77620_ALARM1_HOUR_REG 0x10
|
||||||
|
#define MAX77620_ALARM1_WEEKDAY_REG 0x11
|
||||||
|
#define MAX77620_ALARM1_MONTH_REG 0x12
|
||||||
|
#define MAX77620_ALARM1_YEAR_REG 0x13
|
||||||
|
#define MAX77620_ALARM1_DATE_REG 0x14
|
||||||
|
#define MAX77620_ALARM2_SEC_REG 0x15
|
||||||
|
#define MAX77620_ALARM2_MIN_REG 0x16
|
||||||
|
#define MAX77620_ALARM2_HOUR_REG 0x17
|
||||||
|
#define MAX77620_ALARM2_WEEKDAY_REG 0x18
|
||||||
|
#define MAX77620_ALARM2_MONTH_REG 0x19
|
||||||
|
#define MAX77620_ALARM2_YEAR_REG 0x1A
|
||||||
|
#define MAX77620_ALARM2_DATE_REG 0x1B
|
||||||
|
#define MAX77620_RTC_ALARM_EN_MASK (1 << 7)
|
||||||
|
|
||||||
|
typedef struct _rtc_time_t {
|
||||||
|
u8 weekday;
|
||||||
|
u8 sec;
|
||||||
|
u8 min;
|
||||||
|
u8 hour;
|
||||||
|
u8 date;
|
||||||
|
u8 month;
|
||||||
|
u16 year;
|
||||||
|
} rtc_time_t;
|
||||||
|
|
||||||
|
void max77620_rtc_get_time(rtc_time_t *time);
|
||||||
|
void max77620_rtc_stop_alarm();
|
||||||
|
|
||||||
|
#endif /* _MFD_MAX77620_RTC_H_ */
|
393
source/sec/se.c
Normal file
393
source/sec/se.c
Normal file
@ -0,0 +1,393 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (c) 2018 CTCaer
|
||||||
|
* Copyright (c) 2018 Atmosphère-NX
|
||||||
|
* Copyright (c) 2019 shchmue
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include "../sec/se.h"
|
||||||
|
#include "../mem/heap.h"
|
||||||
|
#include "../soc/t210.h"
|
||||||
|
#include "../sec/se_t210.h"
|
||||||
|
#include "../utils/util.h"
|
||||||
|
|
||||||
|
typedef struct _se_ll_t
|
||||||
|
{
|
||||||
|
vu32 num;
|
||||||
|
vu32 addr;
|
||||||
|
vu32 size;
|
||||||
|
} se_ll_t;
|
||||||
|
|
||||||
|
static void _gf256_mul_x(void *block)
|
||||||
|
{
|
||||||
|
u8 *pdata = (u8 *)block;
|
||||||
|
u32 carry = 0;
|
||||||
|
|
||||||
|
for (int i = 0xF; i >= 0; i--)
|
||||||
|
{
|
||||||
|
u8 b = pdata[i];
|
||||||
|
pdata[i] = (b << 1) | carry;
|
||||||
|
carry = b >> 7;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (carry)
|
||||||
|
pdata[0xF] ^= 0x87;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _gf256_mul_x_le(void *block)
|
||||||
|
{
|
||||||
|
u8 *pdata = (u8 *)block;
|
||||||
|
u32 carry = 0;
|
||||||
|
|
||||||
|
for (u32 i = 0; i < 0x10; i++)
|
||||||
|
{
|
||||||
|
u8 b = pdata[i];
|
||||||
|
pdata[i] = (b << 1) | carry;
|
||||||
|
carry = b >> 7;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (carry)
|
||||||
|
pdata[0x0] ^= 0x87;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _se_ll_init(se_ll_t *ll, u32 addr, u32 size)
|
||||||
|
{
|
||||||
|
ll->num = 0;
|
||||||
|
ll->addr = addr;
|
||||||
|
ll->size = size;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _se_ll_set(se_ll_t *dst, se_ll_t *src)
|
||||||
|
{
|
||||||
|
SE(SE_IN_LL_ADDR_REG_OFFSET) = (u32)src;
|
||||||
|
SE(SE_OUT_LL_ADDR_REG_OFFSET) = (u32)dst;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int _se_wait()
|
||||||
|
{
|
||||||
|
while (!(SE(SE_INT_STATUS_REG_OFFSET) & SE_INT_OP_DONE(INT_SET)))
|
||||||
|
;
|
||||||
|
if (SE(SE_INT_STATUS_REG_OFFSET) & SE_INT_ERROR(INT_SET) ||
|
||||||
|
SE(SE_STATUS_0) & 3 ||
|
||||||
|
SE(SE_ERR_STATUS_0) != 0)
|
||||||
|
return 0;
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int _se_execute(u32 op, void *dst, u32 dst_size, const void *src, u32 src_size)
|
||||||
|
{
|
||||||
|
se_ll_t *ll_dst = NULL, *ll_src = NULL;
|
||||||
|
|
||||||
|
if (dst)
|
||||||
|
{
|
||||||
|
ll_dst = (se_ll_t *)malloc(sizeof(se_ll_t));
|
||||||
|
_se_ll_init(ll_dst, (u32)dst, dst_size);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (src)
|
||||||
|
{
|
||||||
|
ll_src = (se_ll_t *)malloc(sizeof(se_ll_t));
|
||||||
|
_se_ll_init(ll_src, (u32)src, src_size);
|
||||||
|
}
|
||||||
|
|
||||||
|
_se_ll_set(ll_dst, ll_src);
|
||||||
|
|
||||||
|
SE(SE_ERR_STATUS_0) = SE(SE_ERR_STATUS_0);
|
||||||
|
SE(SE_INT_STATUS_REG_OFFSET) = SE(SE_INT_STATUS_REG_OFFSET);
|
||||||
|
SE(SE_OPERATION_REG_OFFSET) = SE_OPERATION(op);
|
||||||
|
|
||||||
|
int res = _se_wait();
|
||||||
|
|
||||||
|
if (src)
|
||||||
|
free(ll_src);
|
||||||
|
if (dst)
|
||||||
|
free(ll_dst);
|
||||||
|
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int _se_execute_one_block(u32 op, void *dst, u32 dst_size, const void *src, u32 src_size)
|
||||||
|
{
|
||||||
|
if (!src || !dst)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
u8 *block = (u8 *)malloc(0x10);
|
||||||
|
memset(block, 0, 0x10);
|
||||||
|
|
||||||
|
SE(SE_BLOCK_COUNT_REG_OFFSET) = 0;
|
||||||
|
|
||||||
|
memcpy(block, src, src_size);
|
||||||
|
int res = _se_execute(op, block, 0x10, block, 0x10);
|
||||||
|
memcpy(dst, block, dst_size);
|
||||||
|
|
||||||
|
free(block);
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _se_aes_ctr_set(void *ctr)
|
||||||
|
{
|
||||||
|
u32 *data = (u32 *)ctr;
|
||||||
|
for (u32 i = 0; i < 4; i++)
|
||||||
|
SE(SE_CRYPTO_CTR_REG_OFFSET + 4 * i) = data[i];
|
||||||
|
}
|
||||||
|
|
||||||
|
void se_rsa_acc_ctrl(u32 rs, u32 flags)
|
||||||
|
{
|
||||||
|
if (flags & 0x7F)
|
||||||
|
SE(SE_RSA_KEYTABLE_ACCESS_REG_OFFSET + 4 * rs) = (((flags >> 4) & 4) | (flags & 3)) ^ 7;
|
||||||
|
if (flags & 0x80)
|
||||||
|
SE(SE_RSA_KEYTABLE_ACCESS_LOCK_OFFSET) &= ~(1 << rs);
|
||||||
|
}
|
||||||
|
|
||||||
|
void se_key_acc_ctrl(u32 ks, u32 flags)
|
||||||
|
{
|
||||||
|
if (flags & 0x7F)
|
||||||
|
SE(SE_KEY_TABLE_ACCESS_REG_OFFSET + 4 * ks) = ~flags;
|
||||||
|
if (flags & 0x80)
|
||||||
|
SE(SE_KEY_TABLE_ACCESS_LOCK_OFFSET) &= ~(1 << ks);
|
||||||
|
}
|
||||||
|
|
||||||
|
void se_aes_key_set(u32 ks, const void *key, u32 size)
|
||||||
|
{
|
||||||
|
u32 *data = (u32 *)key;
|
||||||
|
for (u32 i = 0; i < size / 4; i++)
|
||||||
|
{
|
||||||
|
SE(SE_KEYTABLE_REG_OFFSET) = SE_KEYTABLE_SLOT(ks) | i;
|
||||||
|
SE(SE_KEYTABLE_DATA0_REG_OFFSET) = data[i];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void se_aes_key_read(u32 ks, void *key, u32 size)
|
||||||
|
{
|
||||||
|
u32 *data = (u32 *)key;
|
||||||
|
for (u32 i = 0; i < size / 4; i++)
|
||||||
|
{
|
||||||
|
SE(SE_KEYTABLE_REG_OFFSET) = SE_KEYTABLE_SLOT(ks) | i;
|
||||||
|
data[i] = SE(SE_KEYTABLE_DATA0_REG_OFFSET);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void se_aes_key_clear(u32 ks)
|
||||||
|
{
|
||||||
|
for (u32 i = 0; i < TEGRA_SE_AES_MAX_KEY_SIZE / 4; i++)
|
||||||
|
{
|
||||||
|
SE(SE_KEYTABLE_REG_OFFSET) = SE_KEYTABLE_SLOT(ks) | i;
|
||||||
|
SE(SE_KEYTABLE_DATA0_REG_OFFSET) = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void se_aes_key_iv_clear(u32 ks)
|
||||||
|
{
|
||||||
|
for (u32 i = 0; i < TEGRA_SE_AES_MAX_KEY_SIZE / 4; i++)
|
||||||
|
{
|
||||||
|
SE(SE_KEYTABLE_REG_OFFSET) = SE_KEYTABLE_SLOT(ks) | 8 | i;
|
||||||
|
SE(SE_KEYTABLE_DATA0_REG_OFFSET) = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
int se_aes_unwrap_key(u32 ks_dst, u32 ks_src, const void *input)
|
||||||
|
{
|
||||||
|
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_KEYTAB);
|
||||||
|
SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks_src) | SE_CRYPTO_CORE_SEL(CORE_DECRYPT);
|
||||||
|
SE(SE_BLOCK_COUNT_REG_OFFSET) = 0;
|
||||||
|
SE(SE_CRYPTO_KEYTABLE_DST_REG_OFFSET) = SE_CRYPTO_KEYTABLE_DST_KEY_INDEX(ks_dst);
|
||||||
|
|
||||||
|
return _se_execute(OP_START, NULL, 0, input, 0x10);
|
||||||
|
}
|
||||||
|
|
||||||
|
int se_aes_crypt_ecb(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size)
|
||||||
|
{
|
||||||
|
if (enc)
|
||||||
|
{
|
||||||
|
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
|
||||||
|
SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_MEMORY);
|
||||||
|
SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_DECRYPT);
|
||||||
|
}
|
||||||
|
SE(SE_BLOCK_COUNT_REG_OFFSET) = (src_size >> 4) - 1;
|
||||||
|
return _se_execute(OP_START, dst, dst_size, src, src_size);
|
||||||
|
}
|
||||||
|
|
||||||
|
int se_aes_crypt_block_ecb(u32 ks, u32 enc, void *dst, const void *src)
|
||||||
|
{
|
||||||
|
if (enc)
|
||||||
|
{
|
||||||
|
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
|
||||||
|
SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_MEMORY);
|
||||||
|
SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_DECRYPT);
|
||||||
|
}
|
||||||
|
SE(SE_BLOCK_COUNT_REG_OFFSET) = 0;
|
||||||
|
return _se_execute(OP_START, dst, 0x10, src, 0x10);
|
||||||
|
}
|
||||||
|
|
||||||
|
int se_aes_crypt_ctr(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size, void *ctr)
|
||||||
|
{
|
||||||
|
SE(SE_SPARE_0_REG_OFFSET) = 1;
|
||||||
|
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
|
||||||
|
SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) |
|
||||||
|
SE_CRYPTO_XOR_POS(XOR_BOTTOM) | SE_CRYPTO_INPUT_SEL(INPUT_LNR_CTR) | SE_CRYPTO_CTR_VAL(1);
|
||||||
|
_se_aes_ctr_set(ctr);
|
||||||
|
|
||||||
|
u32 src_size_aligned = src_size & 0xFFFFFFF0;
|
||||||
|
u32 src_size_delta = src_size & 0xF;
|
||||||
|
|
||||||
|
if (src_size_aligned)
|
||||||
|
{
|
||||||
|
SE(SE_BLOCK_COUNT_REG_OFFSET) = (src_size >> 4) - 1;
|
||||||
|
if (!_se_execute(OP_START, dst, dst_size, src, src_size_aligned))
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (src_size - src_size_aligned && src_size_aligned < dst_size)
|
||||||
|
return _se_execute_one_block(OP_START, dst + src_size_aligned,
|
||||||
|
MIN(src_size_delta, dst_size - src_size_aligned),
|
||||||
|
src + src_size_aligned, src_size_delta);
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int se_aes_xts_crypt_sec(u32 ks1, u32 ks2, u32 enc, u64 sec, void *dst, const void *src, u32 secsize)
|
||||||
|
{
|
||||||
|
int res = 0;
|
||||||
|
u8 *tweak = (u8 *)malloc(0x10);
|
||||||
|
u8 *pdst = (u8 *)dst;
|
||||||
|
u8 *psrc = (u8 *)src;
|
||||||
|
|
||||||
|
//Generate tweak.
|
||||||
|
for (int i = 0xF; i >= 0; i--)
|
||||||
|
{
|
||||||
|
tweak[i] = sec & 0xFF;
|
||||||
|
sec >>= 8;
|
||||||
|
}
|
||||||
|
if (!se_aes_crypt_block_ecb(ks1, 1, tweak, tweak))
|
||||||
|
goto out;
|
||||||
|
|
||||||
|
//We are assuming a 0x10-aligned sector size in this implementation.
|
||||||
|
for (u32 i = 0; i < secsize / 0x10; i++)
|
||||||
|
{
|
||||||
|
for (u32 j = 0; j < 0x10; j++)
|
||||||
|
pdst[j] = psrc[j] ^ tweak[j];
|
||||||
|
if (!se_aes_crypt_block_ecb(ks2, enc, pdst, pdst))
|
||||||
|
goto out;
|
||||||
|
for (u32 j = 0; j < 0x10; j++)
|
||||||
|
pdst[j] = pdst[j] ^ tweak[j];
|
||||||
|
_gf256_mul_x_le(tweak);
|
||||||
|
psrc += 0x10;
|
||||||
|
pdst += 0x10;
|
||||||
|
}
|
||||||
|
|
||||||
|
res = 1;
|
||||||
|
|
||||||
|
out:;
|
||||||
|
free(tweak);
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
int se_aes_xts_crypt(u32 ks1, u32 ks2, u32 enc, u64 sec, void *dst, const void *src, u32 secsize, u32 num_secs)
|
||||||
|
{
|
||||||
|
u8 *pdst = (u8 *)dst;
|
||||||
|
u8 *psrc = (u8 *)src;
|
||||||
|
|
||||||
|
for (u32 i = 0; i < num_secs; i++)
|
||||||
|
if (!se_aes_xts_crypt_sec(ks1, ks2, enc, sec + i, pdst + secsize * i, psrc + secsize * i, secsize))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
// se_aes_cmac() was derived from Atmosphère's se_compute_aes_cmac
|
||||||
|
int se_aes_cmac(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size)
|
||||||
|
{
|
||||||
|
int res = 0;
|
||||||
|
u8 *key = (u8 *)calloc(0x10, 1);
|
||||||
|
u8 *last_block = (u8 *)calloc(0x10, 1);
|
||||||
|
|
||||||
|
// generate derived key
|
||||||
|
if (!se_aes_crypt_block_ecb(ks, 1, key, key))
|
||||||
|
goto out;
|
||||||
|
_gf256_mul_x(key);
|
||||||
|
if (src_size & 0xF)
|
||||||
|
_gf256_mul_x(key);
|
||||||
|
|
||||||
|
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_HASHREG);
|
||||||
|
SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | 0x145;
|
||||||
|
se_aes_key_iv_clear(ks);
|
||||||
|
|
||||||
|
u32 num_blocks = (src_size + 0xf) >> 4;
|
||||||
|
if (num_blocks > 1) {
|
||||||
|
SE(SE_BLOCK_COUNT_REG_OFFSET) = num_blocks - 2;
|
||||||
|
if (!_se_execute(OP_START, NULL, 0, src, src_size))
|
||||||
|
goto out;
|
||||||
|
SE(SE_CRYPTO_REG_OFFSET) |= SE_CRYPTO_IV_SEL(IV_UPDATED);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (src_size & 0xf) {
|
||||||
|
memcpy(last_block, src + (src_size & ~0xf), src_size & 0xf);
|
||||||
|
last_block[src_size & 0xf] = 0x80;
|
||||||
|
} else if (src_size >= 0x10) {
|
||||||
|
memcpy(last_block, src + src_size - 0x10, 0x10);
|
||||||
|
}
|
||||||
|
|
||||||
|
for (u32 i = 0; i < 0x10; i++)
|
||||||
|
last_block[i] ^= key[i];
|
||||||
|
|
||||||
|
SE(SE_BLOCK_COUNT_REG_OFFSET) = 0;
|
||||||
|
res = _se_execute(OP_START, NULL, 0, last_block, 0x10);
|
||||||
|
|
||||||
|
u32 *dst32 = (u32 *)dst;
|
||||||
|
for (u32 i = 0; i < (dst_size >> 2); i++)
|
||||||
|
dst32[i] = SE(SE_HASH_RESULT_REG_OFFSET + (i << 2));
|
||||||
|
|
||||||
|
out:;
|
||||||
|
free(key);
|
||||||
|
free(last_block);
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
// se_calc_sha256() was derived from Atmosphère's se_calculate_sha256.
|
||||||
|
int se_calc_sha256(void *dst, const void *src, u32 src_size)
|
||||||
|
{
|
||||||
|
int res;
|
||||||
|
// Setup config for SHA256, size = BITS(src_size).
|
||||||
|
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_MODE(MODE_SHA256) | SE_CONFIG_ENC_ALG(ALG_SHA) | SE_CONFIG_DST(DST_HASHREG);
|
||||||
|
SE(SE_SHA_CONFIG_REG_OFFSET) = 1;
|
||||||
|
SE(SE_SHA_MSG_LENGTH_REG_OFFSET) = (u32)(src_size << 3);
|
||||||
|
SE(0x208) = 0;
|
||||||
|
SE(0x20C) = 0;
|
||||||
|
SE(0x210) = 0;
|
||||||
|
SE(SE_SHA_MSG_LEFT_REG_OFFSET) = (u32)(src_size << 3);
|
||||||
|
SE(0x218) = 0;
|
||||||
|
SE(0x21C) = 0;
|
||||||
|
SE(0x220) = 0;
|
||||||
|
|
||||||
|
// Trigger the operation.
|
||||||
|
res = _se_execute(OP_START, NULL, 0, src, src_size);
|
||||||
|
|
||||||
|
// Copy output hash.
|
||||||
|
u32 *dst32 = (u32 *)dst;
|
||||||
|
for (u32 i = 0; i < 8; i++)
|
||||||
|
dst32[i] = byte_swap_32(SE(SE_HASH_RESULT_REG_OFFSET + (i << 2)));
|
||||||
|
|
||||||
|
return res;
|
||||||
|
}
|
35
source/sec/se.h
Normal file
35
source/sec/se.h
Normal file
@ -0,0 +1,35 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _SE_H_
|
||||||
|
#define _SE_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
void se_rsa_acc_ctrl(u32 rs, u32 flags);
|
||||||
|
void se_key_acc_ctrl(u32 ks, u32 flags);
|
||||||
|
void se_aes_key_set(u32 ks, const void *key, u32 size);
|
||||||
|
void se_aes_key_read(u32 ks, void *key, u32 size);
|
||||||
|
void se_aes_key_clear(u32 ks);
|
||||||
|
int se_aes_unwrap_key(u32 ks_dst, u32 ks_src, const void *input);
|
||||||
|
int se_aes_crypt_ecb(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size);
|
||||||
|
int se_aes_crypt_block_ecb(u32 ks, u32 enc, void *dst, const void *src);
|
||||||
|
int se_aes_crypt_ctr(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size, void *ctr);
|
||||||
|
int se_aes_xts_crypt_sec(u32 ks1, u32 ks2, u32 enc, u64 sec, void *dst, const void *src, u32 secsize);
|
||||||
|
int se_aes_xts_crypt(u32 ks1, u32 ks2, u32 enc, u64 sec, void *dst, const void *src, u32 secsize, u32 num_secs);
|
||||||
|
int se_aes_cmac(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size);
|
||||||
|
int se_calc_sha256(void *dst, const void *src, u32 src_size);
|
||||||
|
#endif
|
357
source/sec/se_t210.h
Normal file
357
source/sec/se_t210.h
Normal file
@ -0,0 +1,357 @@
|
|||||||
|
/*
|
||||||
|
* Driver for Tegra Security Engine
|
||||||
|
*
|
||||||
|
* Copyright (c) 2011-2013, NVIDIA Corporation. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License along
|
||||||
|
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _CRYPTO_TEGRA_SE_H
|
||||||
|
#define _CRYPTO_TEGRA_SE_H
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
#define TEGRA_SE_CRA_PRIORITY 300
|
||||||
|
#define TEGRA_SE_COMPOSITE_PRIORITY 400
|
||||||
|
#define TEGRA_SE_CRYPTO_QUEUE_LENGTH 50
|
||||||
|
#define SE_MAX_SRC_SG_COUNT 50
|
||||||
|
#define SE_MAX_DST_SG_COUNT 50
|
||||||
|
|
||||||
|
#define TEGRA_SE_KEYSLOT_COUNT 16
|
||||||
|
#define SE_MAX_LAST_BLOCK_SIZE 0xFFFFF
|
||||||
|
|
||||||
|
/* SE register definitions */
|
||||||
|
#define SE_SECURITY_0 0x000
|
||||||
|
#define SE_KEY_SCHED_READ_SHIFT 3
|
||||||
|
|
||||||
|
#define SE_CONFIG_REG_OFFSET 0x014
|
||||||
|
#define SE_CONFIG_ENC_ALG_SHIFT 12
|
||||||
|
#define SE_CONFIG_DEC_ALG_SHIFT 8
|
||||||
|
#define ALG_AES_ENC 1
|
||||||
|
#define ALG_RNG 2
|
||||||
|
#define ALG_SHA 3
|
||||||
|
#define ALG_RSA 4
|
||||||
|
#define ALG_NOP 0
|
||||||
|
#define ALG_AES_DEC 1
|
||||||
|
#define SE_CONFIG_ENC_ALG(x) (x << SE_CONFIG_ENC_ALG_SHIFT)
|
||||||
|
#define SE_CONFIG_DEC_ALG(x) (x << SE_CONFIG_DEC_ALG_SHIFT)
|
||||||
|
#define SE_CONFIG_DST_SHIFT 2
|
||||||
|
#define DST_MEMORY 0
|
||||||
|
#define DST_HASHREG 1
|
||||||
|
#define DST_KEYTAB 2
|
||||||
|
#define DST_SRK 3
|
||||||
|
#define DST_RSAREG 4
|
||||||
|
#define SE_CONFIG_DST(x) (x << SE_CONFIG_DST_SHIFT)
|
||||||
|
#define SE_CONFIG_ENC_MODE_SHIFT 24
|
||||||
|
#define SE_CONFIG_DEC_MODE_SHIFT 16
|
||||||
|
#define MODE_KEY128 0
|
||||||
|
#define MODE_KEY192 1
|
||||||
|
#define MODE_KEY256 2
|
||||||
|
#define MODE_SHA1 0
|
||||||
|
#define MODE_SHA224 4
|
||||||
|
#define MODE_SHA256 5
|
||||||
|
#define MODE_SHA384 6
|
||||||
|
#define MODE_SHA512 7
|
||||||
|
#define SE_CONFIG_ENC_MODE(x) (x << SE_CONFIG_ENC_MODE_SHIFT)
|
||||||
|
#define SE_CONFIG_DEC_MODE(x) (x << SE_CONFIG_DEC_MODE_SHIFT)
|
||||||
|
|
||||||
|
#define SE_RNG_CONFIG_REG_OFFSET 0x340
|
||||||
|
#define DRBG_MODE_SHIFT 0
|
||||||
|
#define DRBG_MODE_NORMAL 0
|
||||||
|
#define DRBG_MODE_FORCE_INSTANTION 1
|
||||||
|
#define DRBG_MODE_FORCE_RESEED 2
|
||||||
|
#define SE_RNG_CONFIG_MODE(x) (x << DRBG_MODE_SHIFT)
|
||||||
|
|
||||||
|
#define SE_RNG_SRC_CONFIG_REG_OFFSET 0x344
|
||||||
|
#define DRBG_RO_ENT_SRC_SHIFT 1
|
||||||
|
#define DRBG_RO_ENT_SRC_ENABLE 1
|
||||||
|
#define DRBG_RO_ENT_SRC_DISABLE 0
|
||||||
|
#define SE_RNG_SRC_CONFIG_RO_ENT_SRC(x) (x << DRBG_RO_ENT_SRC_SHIFT)
|
||||||
|
#define DRBG_RO_ENT_SRC_LOCK_SHIFT 0
|
||||||
|
#define DRBG_RO_ENT_SRC_LOCK_ENABLE 1
|
||||||
|
#define DRBG_RO_ENT_SRC_LOCK_DISABLE 0
|
||||||
|
#define SE_RNG_SRC_CONFIG_RO_ENT_SRC_LOCK(x) (x << DRBG_RO_ENT_SRC_LOCK_SHIFT)
|
||||||
|
|
||||||
|
#define DRBG_SRC_SHIFT 2
|
||||||
|
#define DRBG_SRC_NONE 0
|
||||||
|
#define DRBG_SRC_ENTROPY 1
|
||||||
|
#define DRBG_SRC_LFSR 2
|
||||||
|
#define SE_RNG_CONFIG_SRC(x) (x << DRBG_SRC_SHIFT)
|
||||||
|
|
||||||
|
#define SE_RNG_RESEED_INTERVAL_REG_OFFSET 0x348
|
||||||
|
|
||||||
|
#define SE_KEYTABLE_REG_OFFSET 0x31c
|
||||||
|
#define SE_KEYTABLE_SLOT_SHIFT 4
|
||||||
|
#define SE_KEYTABLE_SLOT(x) (x << SE_KEYTABLE_SLOT_SHIFT)
|
||||||
|
#define SE_KEYTABLE_QUAD_SHIFT 2
|
||||||
|
#define QUAD_KEYS_128 0
|
||||||
|
#define QUAD_KEYS_192 1
|
||||||
|
#define QUAD_KEYS_256 1
|
||||||
|
#define QUAD_ORG_IV 2
|
||||||
|
#define QUAD_UPDTD_IV 3
|
||||||
|
#define SE_KEYTABLE_QUAD(x) (x << SE_KEYTABLE_QUAD_SHIFT)
|
||||||
|
#define SE_KEYTABLE_OP_TYPE_SHIFT 9
|
||||||
|
#define OP_READ 0
|
||||||
|
#define OP_WRITE 1
|
||||||
|
#define SE_KEYTABLE_OP_TYPE(x) (x << SE_KEYTABLE_OP_TYPE_SHIFT)
|
||||||
|
#define SE_KEYTABLE_TABLE_SEL_SHIFT 8
|
||||||
|
#define TABLE_KEYIV 0
|
||||||
|
#define TABLE_SCHEDULE 1
|
||||||
|
#define SE_KEYTABLE_TABLE_SEL(x) (x << SE_KEYTABLE_TABLE_SEL_SHIFT)
|
||||||
|
#define SE_KEYTABLE_PKT_SHIFT 0
|
||||||
|
#define SE_KEYTABLE_PKT(x) (x << SE_KEYTABLE_PKT_SHIFT)
|
||||||
|
|
||||||
|
#define SE_OP_DONE_SHIFT 4
|
||||||
|
#define OP_DONE 1
|
||||||
|
#define SE_OP_DONE(x, y) ((x) && (y << SE_OP_DONE_SHIFT))
|
||||||
|
|
||||||
|
#define SE_CRYPTO_REG_OFFSET 0x304
|
||||||
|
#define SE_CRYPTO_HASH_SHIFT 0
|
||||||
|
#define HASH_DISABLE 0
|
||||||
|
#define HASH_ENABLE 1
|
||||||
|
#define SE_CRYPTO_HASH(x) (x << SE_CRYPTO_HASH_SHIFT)
|
||||||
|
#define SE_CRYPTO_XOR_POS_SHIFT 1
|
||||||
|
#define XOR_BYPASS 0
|
||||||
|
#define XOR_TOP 2
|
||||||
|
#define XOR_BOTTOM 3
|
||||||
|
#define SE_CRYPTO_XOR_POS(x) (x << SE_CRYPTO_XOR_POS_SHIFT)
|
||||||
|
#define SE_CRYPTO_INPUT_SEL_SHIFT 3
|
||||||
|
#define INPUT_AHB 0
|
||||||
|
#define INPUT_RANDOM 1
|
||||||
|
#define INPUT_AESOUT 2
|
||||||
|
#define INPUT_LNR_CTR 3
|
||||||
|
#define SE_CRYPTO_INPUT_SEL(x) (x << SE_CRYPTO_INPUT_SEL_SHIFT)
|
||||||
|
#define SE_CRYPTO_VCTRAM_SEL_SHIFT 5
|
||||||
|
#define VCTRAM_AHB 0
|
||||||
|
#define VCTRAM_AESOUT 2
|
||||||
|
#define VCTRAM_PREVAHB 3
|
||||||
|
#define SE_CRYPTO_VCTRAM_SEL(x) (x << SE_CRYPTO_VCTRAM_SEL_SHIFT)
|
||||||
|
#define SE_CRYPTO_IV_SEL_SHIFT 7
|
||||||
|
#define IV_ORIGINAL 0
|
||||||
|
#define IV_UPDATED 1
|
||||||
|
#define SE_CRYPTO_IV_SEL(x) (x << SE_CRYPTO_IV_SEL_SHIFT)
|
||||||
|
#define SE_CRYPTO_CORE_SEL_SHIFT 8
|
||||||
|
#define CORE_DECRYPT 0
|
||||||
|
#define CORE_ENCRYPT 1
|
||||||
|
#define SE_CRYPTO_CORE_SEL(x) (x << SE_CRYPTO_CORE_SEL_SHIFT)
|
||||||
|
#define SE_CRYPTO_CTR_VAL_SHIFT 11
|
||||||
|
#define SE_CRYPTO_CTR_VAL(x) (x << SE_CRYPTO_CTR_VAL_SHIFT)
|
||||||
|
#define SE_CRYPTO_KEY_INDEX_SHIFT 24
|
||||||
|
#define SE_CRYPTO_KEY_INDEX(x) (x << SE_CRYPTO_KEY_INDEX_SHIFT)
|
||||||
|
#define SE_CRYPTO_CTR_CNTN_SHIFT 11
|
||||||
|
#define SE_CRYPTO_CTR_CNTN(x) (x << SE_CRYPTO_CTR_CNTN_SHIFT)
|
||||||
|
|
||||||
|
#define SE_CRYPTO_CTR_REG_COUNT 4
|
||||||
|
#define SE_CRYPTO_CTR_REG_OFFSET 0x308
|
||||||
|
|
||||||
|
#define SE_OPERATION_REG_OFFSET 0x008
|
||||||
|
#define SE_OPERATION_SHIFT 0
|
||||||
|
#define OP_ABORT 0
|
||||||
|
#define OP_START 1
|
||||||
|
#define OP_RESTART 2
|
||||||
|
#define OP_CTX_SAVE 3
|
||||||
|
#define OP_RESTART_IN 4
|
||||||
|
#define SE_OPERATION(x) (x << SE_OPERATION_SHIFT)
|
||||||
|
|
||||||
|
#define SE_CONTEXT_SAVE_CONFIG_REG_OFFSET 0x070
|
||||||
|
#define SE_CONTEXT_SAVE_WORD_QUAD_SHIFT 0
|
||||||
|
#define KEYS_0_3 0
|
||||||
|
#define KEYS_4_7 1
|
||||||
|
#define ORIG_IV 2
|
||||||
|
#define UPD_IV 3
|
||||||
|
#define SE_CONTEXT_SAVE_WORD_QUAD(x) (x << SE_CONTEXT_SAVE_WORD_QUAD_SHIFT)
|
||||||
|
|
||||||
|
#define SE_CONTEXT_SAVE_KEY_INDEX_SHIFT 8
|
||||||
|
#define SE_CONTEXT_SAVE_KEY_INDEX(x) (x << SE_CONTEXT_SAVE_KEY_INDEX_SHIFT)
|
||||||
|
|
||||||
|
#define SE_CONTEXT_SAVAE_STICKY_WORD_QUAD_SHIFT 24
|
||||||
|
#define STICKY_0_3 0
|
||||||
|
#define STICKY_4_7 1
|
||||||
|
#define SE_CONTEXT_SAVE_STICKY_WORD_QUAD(x) \
|
||||||
|
(x << SE_CONTEXT_SAVAE_STICKY_WORD_QUAD_SHIFT)
|
||||||
|
|
||||||
|
#define SE_CONTEXT_SAVE_SRC_SHIFT 29
|
||||||
|
#define STICKY_BITS 0
|
||||||
|
#define KEYTABLE 2
|
||||||
|
#define MEM 4
|
||||||
|
#define SRK 6
|
||||||
|
|
||||||
|
#define RSA_KEYTABLE 1
|
||||||
|
#define SE_CONTEXT_SAVE_SRC(x) (x << SE_CONTEXT_SAVE_SRC_SHIFT)
|
||||||
|
|
||||||
|
#define SE_CONTEXT_SAVE_RSA_KEY_INDEX_SHIFT 16
|
||||||
|
#define SE_CONTEXT_SAVE_RSA_KEY_INDEX(x) \
|
||||||
|
(x << SE_CONTEXT_SAVE_RSA_KEY_INDEX_SHIFT)
|
||||||
|
|
||||||
|
#define SE_CONTEXT_RSA_WORD_QUAD_SHIFT 12
|
||||||
|
#define SE_CONTEXT_RSA_WORD_QUAD(x) \
|
||||||
|
(x << SE_CONTEXT_RSA_WORD_QUAD_SHIFT)
|
||||||
|
|
||||||
|
#define SE_INT_ENABLE_REG_OFFSET 0x00c
|
||||||
|
#define SE_INT_STATUS_REG_OFFSET 0x010
|
||||||
|
#define INT_DISABLE 0
|
||||||
|
#define INT_ENABLE 1
|
||||||
|
#define INT_UNSET 0
|
||||||
|
#define INT_SET 1
|
||||||
|
#define SE_INT_OP_DONE_SHIFT 4
|
||||||
|
#define SE_INT_OP_DONE(x) (x << SE_INT_OP_DONE_SHIFT)
|
||||||
|
#define SE_INT_ERROR_SHIFT 16
|
||||||
|
#define SE_INT_ERROR(x) (x << SE_INT_ERROR_SHIFT)
|
||||||
|
#define SE_STATUS_0 0x800
|
||||||
|
#define SE_ERR_STATUS_0 0x804
|
||||||
|
|
||||||
|
#define SE_CRYPTO_KEYTABLE_DST_REG_OFFSET 0X330
|
||||||
|
#define SE_CRYPTO_KEYTABLE_DST_WORD_QUAD_SHIFT 0
|
||||||
|
#define SE_CRYPTO_KEYTABLE_DST_WORD_QUAD(x) \
|
||||||
|
(x << SE_CRYPTO_KEYTABLE_DST_WORD_QUAD_SHIFT)
|
||||||
|
|
||||||
|
#define SE_KEY_INDEX_SHIFT 8
|
||||||
|
#define SE_CRYPTO_KEYTABLE_DST_KEY_INDEX(x) (x << SE_KEY_INDEX_SHIFT)
|
||||||
|
|
||||||
|
#define SE_IN_LL_ADDR_REG_OFFSET 0x018
|
||||||
|
#define SE_OUT_LL_ADDR_REG_OFFSET 0x024
|
||||||
|
|
||||||
|
#define SE_KEYTABLE_DATA0_REG_OFFSET 0x320
|
||||||
|
#define SE_KEYTABLE_REG_MAX_DATA 16
|
||||||
|
|
||||||
|
#define SE_BLOCK_COUNT_REG_OFFSET 0x318
|
||||||
|
|
||||||
|
#define SE_SPARE_0_REG_OFFSET 0x80c
|
||||||
|
|
||||||
|
#define SE_SHA_CONFIG_REG_OFFSET 0x200
|
||||||
|
#define SHA_DISABLE 0
|
||||||
|
#define SHA_ENABLE 1
|
||||||
|
|
||||||
|
#define SE_SHA_MSG_LENGTH_REG_OFFSET 0x204
|
||||||
|
#define SE_SHA_MSG_LEFT_REG_OFFSET 0x214
|
||||||
|
|
||||||
|
#define SE_HASH_RESULT_REG_COUNT 16
|
||||||
|
#define SE_HASH_RESULT_REG_OFFSET 0x030
|
||||||
|
#define TEGRA_SE_KEY_256_SIZE 32
|
||||||
|
#define TEGRA_SE_KEY_192_SIZE 24
|
||||||
|
#define TEGRA_SE_KEY_128_SIZE 16
|
||||||
|
#define TEGRA_SE_AES_BLOCK_SIZE 16
|
||||||
|
#define TEGRA_SE_AES_MIN_KEY_SIZE 16
|
||||||
|
#define TEGRA_SE_AES_MAX_KEY_SIZE 32
|
||||||
|
#define TEGRA_SE_AES_IV_SIZE 16
|
||||||
|
#define TEGRA_SE_RNG_IV_SIZE 16
|
||||||
|
#define TEGRA_SE_RNG_DT_SIZE 16
|
||||||
|
#define TEGRA_SE_RNG_KEY_SIZE 16
|
||||||
|
#define TEGRA_SE_RNG_SEED_SIZE (TEGRA_SE_RNG_IV_SIZE + \
|
||||||
|
TEGRA_SE_RNG_KEY_SIZE + \
|
||||||
|
TEGRA_SE_RNG_DT_SIZE)
|
||||||
|
|
||||||
|
#define TEGRA_SE_AES_CMAC_DIGEST_SIZE 16
|
||||||
|
#define TEGRA_SE_RSA512_DIGEST_SIZE 64
|
||||||
|
#define TEGRA_SE_RSA1024_DIGEST_SIZE 128
|
||||||
|
#define TEGRA_SE_RSA1536_DIGEST_SIZE 192
|
||||||
|
#define TEGRA_SE_RSA2048_DIGEST_SIZE 256
|
||||||
|
|
||||||
|
#define SE_KEY_TABLE_ACCESS_LOCK_OFFSET 0x280
|
||||||
|
#define SE_KEY_TABLE_ACCESS_REG_OFFSET 0x284
|
||||||
|
#define SE_KEY_READ_DISABLE_SHIFT 0
|
||||||
|
#define SE_KEY_UPDATE_DISABLE_SHIFT 1
|
||||||
|
|
||||||
|
#define SE_CONTEXT_BUFER_SIZE 1072
|
||||||
|
#define SE_CONTEXT_DRBG_BUFER_SIZE 2112
|
||||||
|
|
||||||
|
#define SE_CONTEXT_SAVE_RANDOM_DATA_OFFSET 0
|
||||||
|
#define SE_CONTEXT_SAVE_RANDOM_DATA_SIZE 16
|
||||||
|
#define SE_CONTEXT_SAVE_STICKY_BITS_OFFSET \
|
||||||
|
(SE_CONTEXT_SAVE_RANDOM_DATA_OFFSET + SE_CONTEXT_SAVE_RANDOM_DATA_SIZE)
|
||||||
|
#define SE_CONTEXT_SAVE_STICKY_BITS_SIZE 16
|
||||||
|
|
||||||
|
#define SE_CONTEXT_SAVE_KEYS_OFFSET (SE_CONTEXT_SAVE_STICKY_BITS_OFFSET + \
|
||||||
|
SE_CONTEXT_SAVE_STICKY_BITS_SIZE)
|
||||||
|
#define SE11_CONTEXT_SAVE_KEYS_OFFSET (SE_CONTEXT_SAVE_STICKY_BITS_OFFSET + \
|
||||||
|
SE_CONTEXT_SAVE_STICKY_BITS_SIZE + \
|
||||||
|
SE_CONTEXT_SAVE_STICKY_BITS_SIZE)
|
||||||
|
|
||||||
|
#define SE_CONTEXT_SAVE_KEY_LENGTH 512
|
||||||
|
#define SE_CONTEXT_ORIGINAL_IV_OFFSET (SE_CONTEXT_SAVE_KEYS_OFFSET + \
|
||||||
|
SE_CONTEXT_SAVE_KEY_LENGTH)
|
||||||
|
#define SE11_CONTEXT_ORIGINAL_IV_OFFSET (SE11_CONTEXT_SAVE_KEYS_OFFSET + \
|
||||||
|
SE_CONTEXT_SAVE_KEY_LENGTH)
|
||||||
|
|
||||||
|
#define SE_CONTEXT_ORIGINAL_IV_LENGTH 256
|
||||||
|
|
||||||
|
#define SE_CONTEXT_UPDATED_IV_OFFSET (SE_CONTEXT_ORIGINAL_IV_OFFSET + \
|
||||||
|
SE_CONTEXT_ORIGINAL_IV_LENGTH)
|
||||||
|
#define SE11_CONTEXT_UPDATED_IV_OFFSET (SE11_CONTEXT_ORIGINAL_IV_OFFSET + \
|
||||||
|
SE_CONTEXT_ORIGINAL_IV_LENGTH)
|
||||||
|
|
||||||
|
#define SE_CONTEXT_UPDATED_IV_LENGTH 256
|
||||||
|
|
||||||
|
#define SE_CONTEXT_SAVE_KNOWN_PATTERN_OFFSET (SE_CONTEXT_UPDATED_IV_OFFSET + \
|
||||||
|
SE_CONTEXT_UPDATED_IV_LENGTH)
|
||||||
|
#define SE11_CONTEXT_SAVE_KNOWN_PATTERN_OFFSET \
|
||||||
|
(SE11_CONTEXT_UPDATED_IV_OFFSET + \
|
||||||
|
SE_CONTEXT_UPDATED_IV_LENGTH)
|
||||||
|
|
||||||
|
#define SE_CONTEXT_SAVE_RSA_KEYS_OFFSET SE11_CONTEXT_SAVE_KNOWN_PATTERN_OFFSET
|
||||||
|
|
||||||
|
#define SE_CONTEXT_SAVE_RSA_KEY_LENGTH 1024
|
||||||
|
|
||||||
|
#define SE_CONTEXT_SAVE_RSA_KNOWN_PATTERN_OFFSET \
|
||||||
|
(SE_CONTEXT_SAVE_RSA_KEYS_OFFSET + SE_CONTEXT_SAVE_RSA_KEY_LENGTH)
|
||||||
|
|
||||||
|
#define SE_CONTEXT_KNOWN_PATTERN_SIZE 16
|
||||||
|
|
||||||
|
#define TEGRA_SE_RSA_KEYSLOT_COUNT 2
|
||||||
|
|
||||||
|
#define SE_RSA_KEYTABLE_ACCESS_LOCK_OFFSET 0x40C
|
||||||
|
#define SE_RSA_KEYTABLE_ACCESS_REG_OFFSET 0x410
|
||||||
|
|
||||||
|
#define SE_RSA_KEYTABLE_ADDR 0x420
|
||||||
|
#define SE_RSA_KEYTABLE_DATA 0x424
|
||||||
|
#define SE_RSA_OUTPUT 0x428
|
||||||
|
|
||||||
|
#define RSA_KEY_READ 0
|
||||||
|
#define RSA_KEY_WRITE 1
|
||||||
|
#define SE_RSA_KEY_OP_SHIFT 10
|
||||||
|
#define SE_RSA_KEY_OP(x) (x << SE_RSA_KEY_OP_SHIFT)
|
||||||
|
|
||||||
|
#define RSA_KEY_INPUT_MODE_REG 0
|
||||||
|
#define RSA_KEY_INPUT_MODE_DMA 1
|
||||||
|
#define RSA_KEY_INPUT_MODE_SHIFT 8
|
||||||
|
#define RSA_KEY_INPUT_MODE(x) (x << RSA_KEY_INPUT_MODE_SHIFT)
|
||||||
|
|
||||||
|
#define RSA_KEY_SLOT_ONE 0
|
||||||
|
#define RSA_KEY_SLOT_TW0 1
|
||||||
|
#define RSA_KEY_NUM_SHIFT 7
|
||||||
|
#define RSA_KEY_NUM(x) (x << RSA_KEY_NUM_SHIFT)
|
||||||
|
|
||||||
|
#define RSA_KEY_TYPE_EXP 0
|
||||||
|
#define RSA_KEY_TYPE_MOD 1
|
||||||
|
#define RSA_KEY_TYPE_SHIFT 6
|
||||||
|
#define RSA_KEY_TYPE(x) (x << RSA_KEY_TYPE_SHIFT)
|
||||||
|
|
||||||
|
#define SE_RSA_KEY_SIZE_REG_OFFSET 0x404
|
||||||
|
#define SE_RSA_EXP_SIZE_REG_OFFSET 0x408
|
||||||
|
|
||||||
|
#define RSA_KEY_SLOT_SHIFT 24
|
||||||
|
#define RSA_KEY_SLOT(x) (x << RSA_KEY_SLOT_SHIFT)
|
||||||
|
#define SE_RSA_CONFIG 0x400
|
||||||
|
|
||||||
|
#define RSA_KEY_PKT_WORD_ADDR_SHIFT 0
|
||||||
|
#define RSA_KEY_PKT_WORD_ADDR(x) (x << RSA_KEY_PKT_WORD_ADDR_SHIFT)
|
||||||
|
|
||||||
|
#define RSA_KEY_WORD_ADDR_SHIFT 0
|
||||||
|
#define RSA_KEY_WORD_ADDR(x) (x << RSA_KEY_WORD_ADDR_SHIFT)
|
||||||
|
|
||||||
|
#define SE_RSA_KEYTABLE_PKT_SHIFT 0
|
||||||
|
#define SE_RSA_KEYTABLE_PKT(x) (x << SE_RSA_KEYTABLE_PKT_SHIFT)
|
||||||
|
|
||||||
|
#endif /* _CRYPTO_TEGRA_SE_H */
|
278
source/sec/tsec.c
Normal file
278
source/sec/tsec.c
Normal file
@ -0,0 +1,278 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (c) 2018-2019 CTCaer
|
||||||
|
* Copyright (c) 2018 balika011
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include "../sec/tsec.h"
|
||||||
|
#include "../sec/tsec_t210.h"
|
||||||
|
#include "../sec/se_t210.h"
|
||||||
|
#include "../soc/clock.h"
|
||||||
|
#include "../soc/smmu.h"
|
||||||
|
#include "../soc/t210.h"
|
||||||
|
#include "../mem/heap.h"
|
||||||
|
#include "../mem/mc.h"
|
||||||
|
#include "../utils/util.h"
|
||||||
|
|
||||||
|
/* #include "../gfx/gfx.h"
|
||||||
|
extern gfx_con_t gfx_con; */
|
||||||
|
|
||||||
|
static int _tsec_dma_wait_idle()
|
||||||
|
{
|
||||||
|
u32 timeout = get_tmr_ms() + 10000;
|
||||||
|
|
||||||
|
while (!(TSEC(TSEC_DMATRFCMD) & TSEC_DMATRFCMD_IDLE))
|
||||||
|
if (get_tmr_ms() > timeout)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int _tsec_dma_pa_to_internal_100(int not_imem, int i_offset, int pa_offset)
|
||||||
|
{
|
||||||
|
u32 cmd;
|
||||||
|
|
||||||
|
if (not_imem)
|
||||||
|
cmd = TSEC_DMATRFCMD_SIZE_256B; // DMA 256 bytes
|
||||||
|
else
|
||||||
|
cmd = TSEC_DMATRFCMD_IMEM; // DMA IMEM (Instruction memmory)
|
||||||
|
|
||||||
|
TSEC(TSEC_DMATRFMOFFS) = i_offset;
|
||||||
|
TSEC(TSEC_DMATRFFBOFFS) = pa_offset;
|
||||||
|
TSEC(TSEC_DMATRFCMD) = cmd;
|
||||||
|
|
||||||
|
return _tsec_dma_wait_idle();
|
||||||
|
}
|
||||||
|
|
||||||
|
int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
|
||||||
|
{
|
||||||
|
int res = 0;
|
||||||
|
u8 *fwbuf = NULL;
|
||||||
|
u32 *pdir, *car, *fuse, *pmc, *flowctrl, *se, *mc, *iram, *evec;
|
||||||
|
u32 *pkg11_magic_off;
|
||||||
|
|
||||||
|
//Enable clocks.
|
||||||
|
clock_enable_host1x();
|
||||||
|
clock_enable_tsec();
|
||||||
|
clock_enable_sor_safe();
|
||||||
|
clock_enable_sor0();
|
||||||
|
clock_enable_sor1();
|
||||||
|
clock_enable_kfuse();
|
||||||
|
|
||||||
|
//Configure Falcon.
|
||||||
|
TSEC(TSEC_DMACTL) = 0;
|
||||||
|
TSEC(TSEC_IRQMSET) =
|
||||||
|
TSEC_IRQMSET_EXT(0xFF) |
|
||||||
|
TSEC_IRQMSET_WDTMR |
|
||||||
|
TSEC_IRQMSET_HALT |
|
||||||
|
TSEC_IRQMSET_EXTERR |
|
||||||
|
TSEC_IRQMSET_SWGEN0 |
|
||||||
|
TSEC_IRQMSET_SWGEN1;
|
||||||
|
TSEC(TSEC_IRQDEST) =
|
||||||
|
TSEC_IRQDEST_EXT(0xFF) |
|
||||||
|
TSEC_IRQDEST_HALT |
|
||||||
|
TSEC_IRQDEST_EXTERR |
|
||||||
|
TSEC_IRQDEST_SWGEN0 |
|
||||||
|
TSEC_IRQDEST_SWGEN1;
|
||||||
|
TSEC(TSEC_ITFEN) = TSEC_ITFEN_CTXEN | TSEC_ITFEN_MTHDEN;
|
||||||
|
if (!_tsec_dma_wait_idle())
|
||||||
|
{
|
||||||
|
res = -1;
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
|
|
||||||
|
//Load firmware or emulate memio environment for newer TSEC fw.
|
||||||
|
if (kb == KB_FIRMWARE_VERSION_620)
|
||||||
|
TSEC(TSEC_DMATRFBASE) = (u32)tsec_ctxt->fw >> 8;
|
||||||
|
else
|
||||||
|
{
|
||||||
|
fwbuf = (u8 *)malloc(0x4000);
|
||||||
|
u8 *fwbuf_aligned = (u8 *)ALIGN((u32)fwbuf, 0x100);
|
||||||
|
memcpy(fwbuf_aligned, tsec_ctxt->fw, tsec_ctxt->size);
|
||||||
|
TSEC(TSEC_DMATRFBASE) = (u32)fwbuf_aligned >> 8;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (u32 addr = 0; addr < tsec_ctxt->size; addr += 0x100)
|
||||||
|
{
|
||||||
|
if (!_tsec_dma_pa_to_internal_100(false, addr, addr))
|
||||||
|
{
|
||||||
|
res = -2;
|
||||||
|
goto out_free;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (kb == KB_FIRMWARE_VERSION_620)
|
||||||
|
{
|
||||||
|
// Init SMMU translation for TSEC.
|
||||||
|
pdir = smmu_init_for_tsec();
|
||||||
|
smmu_init(tsec_ctxt->secmon_base);
|
||||||
|
// Enable SMMU
|
||||||
|
if (!smmu_is_used())
|
||||||
|
smmu_enable();
|
||||||
|
|
||||||
|
// Clock reset controller.
|
||||||
|
car = page_alloc(1);
|
||||||
|
memcpy(car, (void *)CLOCK_BASE, 0x1000);
|
||||||
|
car[CLK_RST_CONTROLLER_CLK_SOURCE_TSEC / 4] = 2;
|
||||||
|
smmu_map(pdir, CLOCK_BASE, (u32)car, 1, _WRITABLE | _READABLE | _NONSECURE);
|
||||||
|
|
||||||
|
// Fuse driver.
|
||||||
|
fuse = page_alloc(1);
|
||||||
|
memcpy((void *)&fuse[0x800/4], (void *)FUSE_BASE, 0x400);
|
||||||
|
fuse[0x82C / 4] = 0;
|
||||||
|
fuse[0x9E0 / 4] = (1 << (kb + 2)) - 1;
|
||||||
|
fuse[0x9E4 / 4] = (1 << (kb + 2)) - 1;
|
||||||
|
smmu_map(pdir, (FUSE_BASE - 0x800), (u32)fuse, 1, _READABLE | _NONSECURE);
|
||||||
|
|
||||||
|
// Power management controller.
|
||||||
|
pmc = page_alloc(1);
|
||||||
|
smmu_map(pdir, RTC_BASE, (u32)pmc, 1, _READABLE | _NONSECURE);
|
||||||
|
|
||||||
|
// Flow control.
|
||||||
|
flowctrl = page_alloc(1);
|
||||||
|
smmu_map(pdir, FLOW_CTLR_BASE, (u32)flowctrl, 1, _WRITABLE | _NONSECURE);
|
||||||
|
|
||||||
|
// Security engine.
|
||||||
|
se = page_alloc(1);
|
||||||
|
memcpy(se, (void *)SE_BASE, 0x1000);
|
||||||
|
smmu_map(pdir, SE_BASE, (u32)se, 1, _READABLE | _WRITABLE | _NONSECURE);
|
||||||
|
|
||||||
|
// Memory controller.
|
||||||
|
mc = page_alloc(1);
|
||||||
|
memcpy(mc, (void *)MC_BASE, 0x1000);
|
||||||
|
mc[MC_IRAM_BOM / 4] = 0;
|
||||||
|
mc[MC_IRAM_TOM / 4] = 0x80000000;
|
||||||
|
smmu_map(pdir, MC_BASE, (u32)mc, 1, _READABLE | _NONSECURE);
|
||||||
|
|
||||||
|
// IRAM
|
||||||
|
iram = page_alloc(0x30);
|
||||||
|
memcpy(iram, tsec_ctxt->pkg1, 0x30000);
|
||||||
|
// PKG1.1 magic offset.
|
||||||
|
pkg11_magic_off = (u32 *)(iram + ((tsec_ctxt->pkg11_off + 0x20) / 4));
|
||||||
|
smmu_map(pdir, 0x40010000, (u32)iram, 0x30, _READABLE | _WRITABLE | _NONSECURE);
|
||||||
|
|
||||||
|
// Exception vectors
|
||||||
|
evec = page_alloc(1);
|
||||||
|
smmu_map(pdir, EXCP_VEC_BASE, (u32)evec, 1, _READABLE | _WRITABLE | _NONSECURE);
|
||||||
|
}
|
||||||
|
|
||||||
|
//Execute firmware.
|
||||||
|
HOST1X(0x3300) = 0x34C2E1DA;
|
||||||
|
TSEC(TSEC_STATUS) = 0;
|
||||||
|
TSEC(TSEC_BOOTKEYVER) = 1; // HOS uses key version 1.
|
||||||
|
TSEC(TSEC_BOOTVEC) = 0;
|
||||||
|
TSEC(TSEC_CPUCTL) = TSEC_CPUCTL_STARTCPU;
|
||||||
|
|
||||||
|
if (kb == KB_FIRMWARE_VERSION_620)
|
||||||
|
{
|
||||||
|
u32 start = get_tmr_us();
|
||||||
|
u32 k = se[SE_KEYTABLE_DATA0_REG_OFFSET / 4];
|
||||||
|
u32 key[16] = {0};
|
||||||
|
u32 kidx = 0;
|
||||||
|
|
||||||
|
while (*pkg11_magic_off != HOS_PKG11_MAGIC)
|
||||||
|
{
|
||||||
|
smmu_flush_all();
|
||||||
|
|
||||||
|
if (k == se[SE_KEYTABLE_DATA0_REG_OFFSET / 4])
|
||||||
|
continue;
|
||||||
|
k = se[SE_KEYTABLE_DATA0_REG_OFFSET / 4];
|
||||||
|
key[kidx++] = k;
|
||||||
|
|
||||||
|
// Failsafe.
|
||||||
|
if ((u32)get_tmr_us() - start > 125000)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (kidx != 8)
|
||||||
|
{
|
||||||
|
res = -6;
|
||||||
|
smmu_deinit_for_tsec();
|
||||||
|
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Give some extra time to make sure PKG1.1 is decrypted.
|
||||||
|
msleep(50);
|
||||||
|
|
||||||
|
memcpy(tsec_keys, &key, 0x20);
|
||||||
|
memcpy(tsec_ctxt->pkg1, iram, 0x30000);
|
||||||
|
|
||||||
|
smmu_deinit_for_tsec();
|
||||||
|
|
||||||
|
// for (int i = 0; i < kidx; i++)
|
||||||
|
// gfx_printf(&gfx_con, "key %08X\n", key[i]);
|
||||||
|
|
||||||
|
// gfx_printf(&gfx_con, "cpuctl (%08X) mbox (%08X)\n", TSEC(TSEC_CPUCTL), TSEC(TSEC_STATUS));
|
||||||
|
|
||||||
|
// u32 errst = MC(MC_ERR_STATUS);
|
||||||
|
// gfx_printf(&gfx_con, " MC %08X %08X %08X\n", MC(MC_INTSTATUS), errst, MC(MC_ERR_ADR));
|
||||||
|
// gfx_printf(&gfx_con, " type: %02X\n", errst >> 28);
|
||||||
|
// gfx_printf(&gfx_con, " smmu: %02X\n", (errst >> 25) & 3);
|
||||||
|
// gfx_printf(&gfx_con, " dir: %s\n", (errst >> 16) & 1 ? "W" : "R");
|
||||||
|
// gfx_printf(&gfx_con, " cid: %02x\n", errst & 0xFF);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if (!_tsec_dma_wait_idle())
|
||||||
|
{
|
||||||
|
res = -3;
|
||||||
|
goto out_free;
|
||||||
|
}
|
||||||
|
u32 timeout = get_tmr_ms() + 2000;
|
||||||
|
while (!TSEC(TSEC_STATUS))
|
||||||
|
if (get_tmr_ms() > timeout)
|
||||||
|
{
|
||||||
|
res = -4;
|
||||||
|
goto out_free;
|
||||||
|
}
|
||||||
|
if (TSEC(TSEC_STATUS) != 0xB0B0B0B0)
|
||||||
|
{
|
||||||
|
res = -5;
|
||||||
|
goto out_free;
|
||||||
|
}
|
||||||
|
|
||||||
|
//Fetch result.
|
||||||
|
HOST1X(0x3300) = 0;
|
||||||
|
u32 buf[4];
|
||||||
|
buf[0] = SOR1(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB);
|
||||||
|
buf[1] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB);
|
||||||
|
buf[2] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB);
|
||||||
|
buf[3] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB);
|
||||||
|
SOR1(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB) = 0;
|
||||||
|
SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB) = 0;
|
||||||
|
SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB) = 0;
|
||||||
|
SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB) = 0;
|
||||||
|
|
||||||
|
memcpy(tsec_keys, &buf, 0x10);
|
||||||
|
}
|
||||||
|
|
||||||
|
out_free:;
|
||||||
|
free(fwbuf);
|
||||||
|
|
||||||
|
out:;
|
||||||
|
|
||||||
|
//Disable clocks.
|
||||||
|
clock_disable_kfuse();
|
||||||
|
clock_disable_sor1();
|
||||||
|
clock_disable_sor0();
|
||||||
|
clock_disable_sor_safe();
|
||||||
|
clock_disable_tsec();
|
||||||
|
clock_disable_host1x();
|
||||||
|
|
||||||
|
return res;
|
||||||
|
}
|
34
source/sec/tsec.h
Normal file
34
source/sec/tsec.h
Normal file
@ -0,0 +1,34 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (c) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _TSEC_H_
|
||||||
|
#define _TSEC_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
typedef struct _tsec_ctxt_t
|
||||||
|
{
|
||||||
|
void *fw;
|
||||||
|
u32 size;
|
||||||
|
void *pkg1;
|
||||||
|
u32 pkg11_off;
|
||||||
|
u32 secmon_base;
|
||||||
|
} tsec_ctxt_t;
|
||||||
|
|
||||||
|
int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt);
|
||||||
|
|
||||||
|
#endif
|
50
source/sec/tsec_t210.h
Normal file
50
source/sec/tsec_t210.h
Normal file
@ -0,0 +1,50 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _TSEC_T210_H_
|
||||||
|
#define _TSEC_T210_H_
|
||||||
|
|
||||||
|
#define TSEC_BOOTKEYVER 0x1040
|
||||||
|
#define TSEC_STATUS 0x1044
|
||||||
|
#define TSEC_ITFEN 0x1048
|
||||||
|
#define TSEC_ITFEN_CTXEN (1 << 0)
|
||||||
|
#define TSEC_ITFEN_MTHDEN (1 << 1)
|
||||||
|
#define TSEC_IRQMSET 0x1010
|
||||||
|
#define TSEC_IRQMSET_WDTMR (1 << 1)
|
||||||
|
#define TSEC_IRQMSET_HALT (1 << 4)
|
||||||
|
#define TSEC_IRQMSET_EXTERR (1 << 5)
|
||||||
|
#define TSEC_IRQMSET_SWGEN0 (1 << 6)
|
||||||
|
#define TSEC_IRQMSET_SWGEN1 (1 << 7)
|
||||||
|
#define TSEC_IRQMSET_EXT(val) (((val) & 0xFF) << 8)
|
||||||
|
#define TSEC_IRQDEST 0x101C
|
||||||
|
#define TSEC_IRQDEST_HALT (1 << 4)
|
||||||
|
#define TSEC_IRQDEST_EXTERR (1 << 5)
|
||||||
|
#define TSEC_IRQDEST_SWGEN0 (1 << 6)
|
||||||
|
#define TSEC_IRQDEST_SWGEN1 (1 << 7)
|
||||||
|
#define TSEC_IRQDEST_EXT(val) (((val) & 0xFF) << 8)
|
||||||
|
#define TSEC_CPUCTL 0x1100
|
||||||
|
#define TSEC_CPUCTL_STARTCPU (1 << 1)
|
||||||
|
#define TSEC_BOOTVEC 0x1104
|
||||||
|
#define TSEC_DMACTL 0x110C
|
||||||
|
#define TSEC_DMATRFBASE 0x1110
|
||||||
|
#define TSEC_DMATRFMOFFS 0x1114
|
||||||
|
#define TSEC_DMATRFCMD 0x1118
|
||||||
|
#define TSEC_DMATRFCMD_IDLE (1 << 1)
|
||||||
|
#define TSEC_DMATRFCMD_IMEM (1 << 4)
|
||||||
|
#define TSEC_DMATRFCMD_SIZE_256B (6 << 8)
|
||||||
|
#define TSEC_DMATRFFBOFFS 0x111C
|
||||||
|
|
||||||
|
#endif
|
507
source/soc/clock.c
Normal file
507
source/soc/clock.c
Normal file
@ -0,0 +1,507 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "../soc/clock.h"
|
||||||
|
#include "../soc/t210.h"
|
||||||
|
#include "../utils/util.h"
|
||||||
|
#include "../storage/sdmmc.h"
|
||||||
|
|
||||||
|
/* clock_t: reset, enable, source, index, clk_src, clk_div */
|
||||||
|
|
||||||
|
static const clock_t _clock_uart[] = {
|
||||||
|
/* UART A */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA, 6, 0, 0 },
|
||||||
|
/* UART B */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB, 7, 0, 0 },
|
||||||
|
/* UART C */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC, 0x17, 0, 0 },
|
||||||
|
/* UART D */ { 0 },
|
||||||
|
/* UART E */ { 0 }
|
||||||
|
};
|
||||||
|
|
||||||
|
static const clock_t _clock_i2c[] = {
|
||||||
|
/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 0xC, 6, 0 },
|
||||||
|
/* I2C2 */ { 0 },
|
||||||
|
/* I2C3 */ { 0 },
|
||||||
|
/* I2C4 */ { 0 },
|
||||||
|
/* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 0xF, 6, 0 },
|
||||||
|
/* I2C6 */ { 0 }
|
||||||
|
};
|
||||||
|
|
||||||
|
static clock_t _clock_se = {
|
||||||
|
CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, 0x1F, 0, 0
|
||||||
|
};
|
||||||
|
static clock_t _clock_unk2 = {
|
||||||
|
CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE, 0x1E, 0, 0
|
||||||
|
};
|
||||||
|
|
||||||
|
static clock_t _clock_host1x = {
|
||||||
|
CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, 0x1C, 4, 3
|
||||||
|
};
|
||||||
|
static clock_t _clock_tsec = {
|
||||||
|
CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, 0x13, 0, 2
|
||||||
|
};
|
||||||
|
static clock_t _clock_sor_safe = {
|
||||||
|
CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE, 0x1E, 0, 0
|
||||||
|
};
|
||||||
|
static clock_t _clock_sor0 = {
|
||||||
|
CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NO_SOURCE, 0x16, 0, 0
|
||||||
|
};
|
||||||
|
static clock_t _clock_sor1 = {
|
||||||
|
CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, 0x17, 0, 2
|
||||||
|
};
|
||||||
|
static clock_t _clock_kfuse = {
|
||||||
|
CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, 8, 0, 0
|
||||||
|
};
|
||||||
|
|
||||||
|
static clock_t _clock_cl_dvfs = {
|
||||||
|
CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE, 0x1B, 0, 0
|
||||||
|
};
|
||||||
|
static clock_t _clock_coresight = {
|
||||||
|
CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, 9, 0, 4
|
||||||
|
};
|
||||||
|
|
||||||
|
static clock_t _clock_pwm = {
|
||||||
|
CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 0x11, 6, 4
|
||||||
|
};
|
||||||
|
|
||||||
|
void clock_enable(const clock_t *clk)
|
||||||
|
{
|
||||||
|
// Put clock into reset.
|
||||||
|
CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index);
|
||||||
|
// Disable.
|
||||||
|
CLOCK(clk->enable) &= ~(1 << clk->index);
|
||||||
|
// Configure clock source if required.
|
||||||
|
if (clk->source)
|
||||||
|
CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29);
|
||||||
|
// Enable.
|
||||||
|
CLOCK(clk->enable) = (CLOCK(clk->enable) & ~(1 << clk->index)) | (1 << clk->index);
|
||||||
|
// Take clock off reset.
|
||||||
|
CLOCK(clk->reset) &= ~(1 << clk->index);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_disable(const clock_t *clk)
|
||||||
|
{
|
||||||
|
// Put clock into reset.
|
||||||
|
CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index);
|
||||||
|
// Disable.
|
||||||
|
CLOCK(clk->enable) &= ~(1 << clk->index);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_enable_fuse(bool enable)
|
||||||
|
{
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) = (CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) & 0xEFFFFFFF) | ((enable & 1) << 28);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_enable_uart(u32 idx)
|
||||||
|
{
|
||||||
|
clock_enable(&_clock_uart[idx]);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_enable_i2c(u32 idx)
|
||||||
|
{
|
||||||
|
clock_enable(&_clock_i2c[idx]);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_disable_i2c(u32 idx)
|
||||||
|
{
|
||||||
|
clock_disable(&_clock_i2c[idx]);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_enable_se()
|
||||||
|
{
|
||||||
|
clock_enable(&_clock_se);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_enable_unk2()
|
||||||
|
{
|
||||||
|
clock_enable(&_clock_unk2);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_enable_host1x()
|
||||||
|
{
|
||||||
|
clock_enable(&_clock_host1x);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_disable_host1x()
|
||||||
|
{
|
||||||
|
clock_disable(&_clock_host1x);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_enable_tsec()
|
||||||
|
{
|
||||||
|
clock_enable(&_clock_tsec);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_disable_tsec()
|
||||||
|
{
|
||||||
|
clock_disable(&_clock_tsec);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_enable_sor_safe()
|
||||||
|
{
|
||||||
|
clock_enable(&_clock_sor_safe);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_disable_sor_safe()
|
||||||
|
{
|
||||||
|
clock_disable(&_clock_sor_safe);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_enable_sor0()
|
||||||
|
{
|
||||||
|
clock_enable(&_clock_sor0);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_disable_sor0()
|
||||||
|
{
|
||||||
|
clock_disable(&_clock_sor0);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_enable_sor1()
|
||||||
|
{
|
||||||
|
clock_enable(&_clock_sor1);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_disable_sor1()
|
||||||
|
{
|
||||||
|
clock_disable(&_clock_sor1);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_enable_kfuse()
|
||||||
|
{
|
||||||
|
//clock_enable(&_clock_kfuse);
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) = (CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) & 0xFFFFFEFF) | 0x100;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) &= 0xFFFFFEFF;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) & 0xFFFFFEFF) | 0x100;
|
||||||
|
usleep(10);
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) &= 0xFFFFFEFF;
|
||||||
|
usleep(20);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_disable_kfuse()
|
||||||
|
{
|
||||||
|
clock_disable(&_clock_kfuse);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_enable_cl_dvfs()
|
||||||
|
{
|
||||||
|
clock_enable(&_clock_cl_dvfs);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_disable_cl_dvfs()
|
||||||
|
{
|
||||||
|
clock_disable(&_clock_cl_dvfs);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_enable_coresight()
|
||||||
|
{
|
||||||
|
clock_enable(&_clock_coresight);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_disable_coresight()
|
||||||
|
{
|
||||||
|
clock_disable(&_clock_coresight);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_enable_pwm()
|
||||||
|
{
|
||||||
|
clock_enable(&_clock_pwm);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_disable_pwm()
|
||||||
|
{
|
||||||
|
clock_disable(&_clock_pwm);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define L_SWR_SDMMC1_RST (1 << 14)
|
||||||
|
#define L_SWR_SDMMC2_RST (1 << 9)
|
||||||
|
#define L_SWR_SDMMC4_RST (1 << 15)
|
||||||
|
#define U_SWR_SDMMC3_RST (1 << 5)
|
||||||
|
|
||||||
|
#define L_CLK_ENB_SDMMC1 (1 << 14)
|
||||||
|
#define L_CLK_ENB_SDMMC2 (1 << 9)
|
||||||
|
#define L_CLK_ENB_SDMMC4 (1 << 15)
|
||||||
|
#define U_CLK_ENB_SDMMC3 (1 << 5)
|
||||||
|
|
||||||
|
#define L_SET_SDMMC1_RST (1 << 14)
|
||||||
|
#define L_SET_SDMMC2_RST (1 << 9)
|
||||||
|
#define L_SET_SDMMC4_RST (1 << 15)
|
||||||
|
#define U_SET_SDMMC3_RST (1 << 5)
|
||||||
|
|
||||||
|
#define L_CLR_SDMMC1_RST (1 << 14)
|
||||||
|
#define L_CLR_SDMMC2_RST (1 << 9)
|
||||||
|
#define L_CLR_SDMMC4_RST (1 << 15)
|
||||||
|
#define U_CLR_SDMMC3_RST (1 << 5)
|
||||||
|
|
||||||
|
#define L_SET_CLK_ENB_SDMMC1 (1 << 14)
|
||||||
|
#define L_SET_CLK_ENB_SDMMC2 (1 << 9)
|
||||||
|
#define L_SET_CLK_ENB_SDMMC4 (1 << 15)
|
||||||
|
#define U_SET_CLK_ENB_SDMMC3 (1 << 5)
|
||||||
|
|
||||||
|
#define L_CLR_CLK_ENB_SDMMC1 (1 << 14)
|
||||||
|
#define L_CLR_CLK_ENB_SDMMC2 (1 << 9)
|
||||||
|
#define L_CLR_CLK_ENB_SDMMC4 (1 << 15)
|
||||||
|
#define U_CLR_CLK_ENB_SDMMC3 (1 << 5)
|
||||||
|
|
||||||
|
static int _clock_sdmmc_is_reset(u32 id)
|
||||||
|
{
|
||||||
|
switch (id)
|
||||||
|
{
|
||||||
|
case SDMMC_1:
|
||||||
|
return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC1_RST;
|
||||||
|
case SDMMC_2:
|
||||||
|
return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC2_RST;
|
||||||
|
case SDMMC_3:
|
||||||
|
return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_U) & U_SWR_SDMMC3_RST;
|
||||||
|
case SDMMC_4:
|
||||||
|
return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC4_RST;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _clock_sdmmc_set_reset(u32 id)
|
||||||
|
{
|
||||||
|
switch (id)
|
||||||
|
{
|
||||||
|
case SDMMC_1:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC1_RST;
|
||||||
|
case SDMMC_2:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC2_RST;
|
||||||
|
case SDMMC_3:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_SET) = U_SET_SDMMC3_RST;
|
||||||
|
case SDMMC_4:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC4_RST;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _clock_sdmmc_clear_reset(u32 id)
|
||||||
|
{
|
||||||
|
switch (id)
|
||||||
|
{
|
||||||
|
case SDMMC_1:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC1_RST;
|
||||||
|
case SDMMC_2:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC2_RST;
|
||||||
|
case SDMMC_3:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_CLR) = U_CLR_SDMMC3_RST;
|
||||||
|
case SDMMC_4:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC4_RST;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static int _clock_sdmmc_is_enabled(u32 id)
|
||||||
|
{
|
||||||
|
switch (id)
|
||||||
|
{
|
||||||
|
case SDMMC_1:
|
||||||
|
return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC1;
|
||||||
|
case SDMMC_2:
|
||||||
|
return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC2;
|
||||||
|
case SDMMC_3:
|
||||||
|
return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) & U_CLK_ENB_SDMMC3;
|
||||||
|
case SDMMC_4:
|
||||||
|
return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC4;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _clock_sdmmc_set_enable(u32 id)
|
||||||
|
{
|
||||||
|
switch (id)
|
||||||
|
{
|
||||||
|
case SDMMC_1:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC1;
|
||||||
|
case SDMMC_2:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC2;
|
||||||
|
case SDMMC_3:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_SET) = U_SET_CLK_ENB_SDMMC3;
|
||||||
|
case SDMMC_4:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC4;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _clock_sdmmc_clear_enable(u32 id)
|
||||||
|
{
|
||||||
|
switch (id)
|
||||||
|
{
|
||||||
|
case SDMMC_1:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC1;
|
||||||
|
case SDMMC_2:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC2;
|
||||||
|
case SDMMC_3:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_CLR) = U_CLR_CLK_ENB_SDMMC3;
|
||||||
|
case SDMMC_4:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC4;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static u32 _clock_sdmmc_table[8] = { 0 };
|
||||||
|
|
||||||
|
static int _clock_sdmmc_config_clock_source_inner(u32 *pout, u32 id, u32 val)
|
||||||
|
{
|
||||||
|
u32 divisor = 0;
|
||||||
|
u32 source = 0;
|
||||||
|
|
||||||
|
switch (val)
|
||||||
|
{
|
||||||
|
case 25000:
|
||||||
|
*pout = 24728;
|
||||||
|
divisor = 31;
|
||||||
|
break;
|
||||||
|
case 26000:
|
||||||
|
*pout = 25500;
|
||||||
|
divisor = 30;
|
||||||
|
break;
|
||||||
|
case 40800:
|
||||||
|
*pout = 40800;
|
||||||
|
divisor = 18;
|
||||||
|
break;
|
||||||
|
case 50000:
|
||||||
|
*pout = 48000;
|
||||||
|
divisor = 15;
|
||||||
|
break;
|
||||||
|
case 52000:
|
||||||
|
*pout = 51000;
|
||||||
|
divisor = 14;
|
||||||
|
break;
|
||||||
|
case 100000:
|
||||||
|
*pout = 90667;
|
||||||
|
divisor = 7;
|
||||||
|
break;
|
||||||
|
case 200000:
|
||||||
|
*pout = 163200;
|
||||||
|
divisor = 3;
|
||||||
|
break;
|
||||||
|
case 208000:
|
||||||
|
*pout = 204000;
|
||||||
|
divisor = 2;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
*pout = 24728;
|
||||||
|
divisor = 31;
|
||||||
|
}
|
||||||
|
|
||||||
|
_clock_sdmmc_table[2 * id] = val;
|
||||||
|
_clock_sdmmc_table[2 * id + 1] = *pout;
|
||||||
|
|
||||||
|
switch (id)
|
||||||
|
{
|
||||||
|
case SDMMC_1:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1) = source | divisor;
|
||||||
|
break;
|
||||||
|
case SDMMC_2:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2) = source | divisor;
|
||||||
|
break;
|
||||||
|
case SDMMC_3:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3) = source | divisor;
|
||||||
|
break;
|
||||||
|
case SDMMC_4:
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4) = source | divisor;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val)
|
||||||
|
{
|
||||||
|
if (_clock_sdmmc_table[2 * id] == val)
|
||||||
|
{
|
||||||
|
*pout = _clock_sdmmc_table[2 * id + 1];
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
int is_enabled = _clock_sdmmc_is_enabled(id);
|
||||||
|
if (is_enabled)
|
||||||
|
_clock_sdmmc_clear_enable(id);
|
||||||
|
_clock_sdmmc_config_clock_source_inner(pout, id, val);
|
||||||
|
if (is_enabled)
|
||||||
|
_clock_sdmmc_set_enable(id);
|
||||||
|
_clock_sdmmc_is_reset(id);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_sdmmc_get_params(u32 *pout, u16 *pdivisor, u32 type)
|
||||||
|
{
|
||||||
|
switch (type)
|
||||||
|
{
|
||||||
|
case 0:
|
||||||
|
*pout = 26000;
|
||||||
|
*pdivisor = 66;
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
*pout = 26000;
|
||||||
|
*pdivisor = 1;
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
*pout = 52000;
|
||||||
|
*pdivisor = 1;
|
||||||
|
break;
|
||||||
|
case 3:
|
||||||
|
case 4:
|
||||||
|
case 11:
|
||||||
|
*pout = 200000;
|
||||||
|
*pdivisor = 1;
|
||||||
|
break;
|
||||||
|
case 5:
|
||||||
|
*pout = 25000;
|
||||||
|
*pdivisor = 64;
|
||||||
|
case 6:
|
||||||
|
case 8:
|
||||||
|
*pout = 25000;
|
||||||
|
*pdivisor = 1;
|
||||||
|
break;
|
||||||
|
case 7:
|
||||||
|
*pout = 50000;
|
||||||
|
*pdivisor = 1;
|
||||||
|
case 10:
|
||||||
|
*pout = 100000;
|
||||||
|
*pdivisor = 1;
|
||||||
|
case 13:
|
||||||
|
*pout = 40800;
|
||||||
|
*pdivisor = 1;
|
||||||
|
break;
|
||||||
|
case 14:
|
||||||
|
*pout = 200000;
|
||||||
|
*pdivisor = 2;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
int clock_sdmmc_is_not_reset_and_enabled(u32 id)
|
||||||
|
{
|
||||||
|
return !_clock_sdmmc_is_reset(id) && _clock_sdmmc_is_enabled(id);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_sdmmc_enable(u32 id, u32 val)
|
||||||
|
{
|
||||||
|
u32 div = 0;
|
||||||
|
|
||||||
|
if (_clock_sdmmc_is_enabled(id))
|
||||||
|
_clock_sdmmc_clear_enable(id);
|
||||||
|
_clock_sdmmc_set_reset(id);
|
||||||
|
_clock_sdmmc_config_clock_source_inner(&div, id, val);
|
||||||
|
_clock_sdmmc_set_enable(id);
|
||||||
|
_clock_sdmmc_is_reset(id);
|
||||||
|
usleep((100000 + div - 1) / div);
|
||||||
|
_clock_sdmmc_clear_reset(id);
|
||||||
|
_clock_sdmmc_is_reset(id);
|
||||||
|
}
|
||||||
|
|
||||||
|
void clock_sdmmc_disable(u32 id)
|
||||||
|
{
|
||||||
|
_clock_sdmmc_set_reset(id);
|
||||||
|
_clock_sdmmc_clear_enable(id);
|
||||||
|
_clock_sdmmc_is_reset(id);
|
||||||
|
}
|
167
source/soc/clock.h
Normal file
167
source/soc/clock.h
Normal file
@ -0,0 +1,167 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _CLOCK_H_
|
||||||
|
#define _CLOCK_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
/*! Clock registers. */
|
||||||
|
#define CLK_RST_CONTROLLER_RST_SOURCE 0x0
|
||||||
|
#define CLK_RST_CONTROLLER_RST_DEVICES_L 0x4
|
||||||
|
#define CLK_RST_CONTROLLER_RST_DEVICES_H 0x8
|
||||||
|
#define CLK_RST_CONTROLLER_RST_DEVICES_U 0xC
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L 0x10
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H 0x14
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U 0x18
|
||||||
|
#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY 0x20
|
||||||
|
#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER 0x24
|
||||||
|
#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY 0x28
|
||||||
|
#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER 0x2C
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30
|
||||||
|
#define CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48
|
||||||
|
#define CLK_RST_CONTROLLER_OSC_CTRL 0x50
|
||||||
|
#define CLK_RST_CONTROLLER_PLLC_BASE 0x80
|
||||||
|
#define CLK_RST_CONTROLLER_PLLC_MISC 0x88
|
||||||
|
#define CLK_RST_CONTROLLER_PLLM_BASE 0x90
|
||||||
|
#define CLK_RST_CONTROLLER_PLLM_MISC1 0x98
|
||||||
|
#define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C
|
||||||
|
#define CLK_RST_CONTROLLER_PLLP_BASE 0xA0
|
||||||
|
#define CLK_RST_CONTROLLER_PLLD_BASE 0xD0
|
||||||
|
#define CLK_RST_CONTROLLER_PLLX_BASE 0xE0
|
||||||
|
#define CLK_RST_CONTROLLER_PLLX_MISC 0xE4
|
||||||
|
#define CLK_RST_CONTROLLER_PLLE_BASE 0xE8
|
||||||
|
#define CLK_RST_CONTROLLER_PLLE_MISC 0xEC
|
||||||
|
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA 0xF8
|
||||||
|
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB 0xFC
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM 0x110
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 0x124
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 0x128
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI 0x148
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 0x150
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 0x154
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 0x164
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA 0x178
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB 0x17C
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X 0x180
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC 0x1A0
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 0x1B8
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 0x1BC
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE 0x1D4
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC 0x1F4
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_ENB_X_CLR 0x288
|
||||||
|
#define CLK_RST_CONTROLLER_RST_DEVICES_X 0x28C
|
||||||
|
#define CLK_RST_CONTROLLER_RST_DEV_X_SET 0x290
|
||||||
|
#define CLK_RST_CONTROLLER_RST_DEV_X_CLR 0x294
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_Y 0x298
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_ENB_Y_SET 0x29C
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_ENB_Y_CLR 0x2A0
|
||||||
|
#define CLK_RST_CONTROLLER_RST_DEVICES_Y 0x2A4
|
||||||
|
#define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2A8
|
||||||
|
#define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2AC
|
||||||
|
#define CLK_RST_CONTROLLER_RST_DEV_L_SET 0x300
|
||||||
|
#define CLK_RST_CONTROLLER_RST_DEV_L_CLR 0x304
|
||||||
|
#define CLK_RST_CONTROLLER_RST_DEV_H_SET 0x308
|
||||||
|
#define CLK_RST_CONTROLLER_RST_DEV_H_CLR 0x30C
|
||||||
|
#define CLK_RST_CONTROLLER_RST_DEV_U_SET 0x310
|
||||||
|
#define CLK_RST_CONTROLLER_RST_DEV_U_CLR 0x314
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_ENB_L_SET 0x320
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR 0x324
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_ENB_H_SET 0x328
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR 0x32C
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_ENB_U_SET 0x330
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR 0x334
|
||||||
|
#define CLK_RST_CONTROLLER_RST_DEVICES_V 0x358
|
||||||
|
#define CLK_RST_CONTROLLER_RST_DEVICES_W 0x35C
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_V 0x360
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_W 0x364
|
||||||
|
#define CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2 0x388
|
||||||
|
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC 0x3A0
|
||||||
|
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3A4
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT 0x3B4
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE 0x42C
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_ENB_W_CLR 0x44C
|
||||||
|
#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET 0x450
|
||||||
|
#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR 0x454
|
||||||
|
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2 0x488
|
||||||
|
#define CLK_RST_CONTROLLER_PLLE_AUX 0x48C
|
||||||
|
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S0 0x4A0
|
||||||
|
#define CLK_RST_CONTROLLER_PLLX_MISC_3 0x518
|
||||||
|
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE 0x554
|
||||||
|
#define CLK_RST_CONTROLLER_SPARE_REG0 0x55C
|
||||||
|
#define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP 0x620
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIP_CAL 0x66C
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM 0x694
|
||||||
|
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0
|
||||||
|
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER 0x704
|
||||||
|
|
||||||
|
#define CLK_NO_SOURCE 0x0
|
||||||
|
|
||||||
|
/*! Generic clock descriptor. */
|
||||||
|
typedef struct _clock_t
|
||||||
|
{
|
||||||
|
u32 reset;
|
||||||
|
u32 enable;
|
||||||
|
u32 source;
|
||||||
|
u8 index;
|
||||||
|
u8 clk_src;
|
||||||
|
u8 clk_div;
|
||||||
|
} clock_t;
|
||||||
|
|
||||||
|
/*! Generic clock enable/disable. */
|
||||||
|
void clock_enable(const clock_t *clk);
|
||||||
|
void clock_disable(const clock_t *clk);
|
||||||
|
|
||||||
|
/*! Clock control for specific hardware portions. */
|
||||||
|
void clock_enable_fuse(bool enable);
|
||||||
|
void clock_enable_uart(u32 idx);
|
||||||
|
void clock_enable_i2c(u32 idx);
|
||||||
|
void clock_disable_i2c(u32 idx);
|
||||||
|
void clock_enable_se();
|
||||||
|
void clock_enable_unk2();
|
||||||
|
void clock_enable_host1x();
|
||||||
|
void clock_disable_host1x();
|
||||||
|
void clock_enable_tsec();
|
||||||
|
void clock_disable_tsec();
|
||||||
|
void clock_enable_sor_safe();
|
||||||
|
void clock_disable_sor_safe();
|
||||||
|
void clock_enable_sor0();
|
||||||
|
void clock_disable_sor0();
|
||||||
|
void clock_enable_sor1();
|
||||||
|
void clock_disable_sor1();
|
||||||
|
void clock_enable_kfuse();
|
||||||
|
void clock_disable_kfuse();
|
||||||
|
void clock_enable_cl_dvfs();
|
||||||
|
void clock_disable_cl_dvfs();
|
||||||
|
void clock_enable_coresight();
|
||||||
|
void clock_disable_coresight();
|
||||||
|
void clock_enable_pwm();
|
||||||
|
void clock_disable_pwm();
|
||||||
|
void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val);
|
||||||
|
void clock_sdmmc_get_params(u32 *pout, u16 *pdivisor, u32 type);
|
||||||
|
int clock_sdmmc_is_not_reset_and_enabled(u32 id);
|
||||||
|
void clock_sdmmc_enable(u32 id, u32 val);
|
||||||
|
void clock_sdmmc_disable(u32 id);
|
||||||
|
|
||||||
|
#endif
|
133
source/soc/cluster.c
Normal file
133
source/soc/cluster.c
Normal file
@ -0,0 +1,133 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "../soc/cluster.h"
|
||||||
|
#include "../soc/i2c.h"
|
||||||
|
#include "../soc/clock.h"
|
||||||
|
#include "../utils/util.h"
|
||||||
|
#include "../soc/pmc.h"
|
||||||
|
#include "../soc/t210.h"
|
||||||
|
#include "../power/max77620.h"
|
||||||
|
#include "../power/max7762x.h"
|
||||||
|
|
||||||
|
void _cluster_enable_power()
|
||||||
|
{
|
||||||
|
u8 tmp = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO); // Get current pinmuxing
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO, tmp & ~(1 << 5)); // Disable GPIO5 pinmuxing.
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, MAX77620_CNFG_GPIO_DRV_PUSHPULL | MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH);
|
||||||
|
|
||||||
|
// Enable cores power.
|
||||||
|
// 1-3.x: MAX77621_NFSR_ENABLE.
|
||||||
|
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG,
|
||||||
|
MAX77621_AD_ENABLE | MAX77621_NFSR_ENABLE | MAX77621_SNS_ENABLE);
|
||||||
|
// 1.0.0-3.x: MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL.
|
||||||
|
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG,
|
||||||
|
MAX77621_T_JUNCTION_120 | MAX77621_WDTMR_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US| MAX77621_INDUCTOR_NOMINAL);
|
||||||
|
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_ENABLE | 0x37);
|
||||||
|
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVC_REG, MAX77621_VOUT_ENABLE | 0x37);
|
||||||
|
}
|
||||||
|
|
||||||
|
int _cluster_pmc_enable_partition(u32 part, u32 toggle, bool enable)
|
||||||
|
{
|
||||||
|
// Check if the partition has already been turned on.
|
||||||
|
if (enable && PMC(APBDEV_PMC_PWRGATE_STATUS) & part)
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
u32 i = 5001;
|
||||||
|
while (PMC(APBDEV_PMC_PWRGATE_TOGGLE) & 0x100)
|
||||||
|
{
|
||||||
|
usleep(1);
|
||||||
|
i--;
|
||||||
|
if (i < 1)
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
PMC(APBDEV_PMC_PWRGATE_TOGGLE) = toggle | (enable ? 0x100 : 0);
|
||||||
|
|
||||||
|
i = 5001;
|
||||||
|
while (i > 0)
|
||||||
|
{
|
||||||
|
if (PMC(APBDEV_PMC_PWRGATE_STATUS) & part)
|
||||||
|
break;
|
||||||
|
usleep(1);
|
||||||
|
i--;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void cluster_boot_cpu0(u32 entry)
|
||||||
|
{
|
||||||
|
// Set ACTIVE_CLUSER to FAST.
|
||||||
|
FLOW_CTLR(FLOW_CTLR_BPMP_CLUSTER_CONTROL) &= 0xFFFFFFFE;
|
||||||
|
|
||||||
|
_cluster_enable_power();
|
||||||
|
|
||||||
|
if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x40000000))
|
||||||
|
{
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= 0xFFFFFFF7;
|
||||||
|
usleep(2);
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x80404E02;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x404E02;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) = (CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) & 0xFFFBFFFF) | 0x40000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x40404E02;
|
||||||
|
}
|
||||||
|
while (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x8000000))
|
||||||
|
;
|
||||||
|
|
||||||
|
// Configure MSELECT source and enable clock.
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) & 0x1FFFFF00) | 6;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) & 0xFFFFFFF7) | 8;
|
||||||
|
|
||||||
|
// Configure initial CPU clock frequency and enable clock.
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CCLK_BURST_POLICY) = 0x20008888;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER) = 0x80000000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = 1;
|
||||||
|
|
||||||
|
clock_enable_coresight();
|
||||||
|
|
||||||
|
// CAR2PMC_CPU_ACK_WIDTH should be set to 0.
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2) &= 0xFFFFF000;
|
||||||
|
|
||||||
|
// Enable CPU rail.
|
||||||
|
_cluster_pmc_enable_partition(1, 0, true);
|
||||||
|
// Enable cluster 0 non-CPU.
|
||||||
|
_cluster_pmc_enable_partition(0x8000, 15, true);
|
||||||
|
// Enable CE0.
|
||||||
|
_cluster_pmc_enable_partition(0x4000, 14, true);
|
||||||
|
|
||||||
|
// Request and wait for RAM repair.
|
||||||
|
FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) = 1;
|
||||||
|
while (!(FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) & 2))
|
||||||
|
;
|
||||||
|
|
||||||
|
EXCP_VEC(EVP_CPU_RESET_VECTOR) = 0;
|
||||||
|
|
||||||
|
// Set reset vector.
|
||||||
|
SB(SB_AA64_RESET_LOW) = entry | 1;
|
||||||
|
SB(SB_AA64_RESET_HIGH) = 0;
|
||||||
|
// Non-secure reset vector write disable.
|
||||||
|
SB(SB_CSR) = 2;
|
||||||
|
(void)SB(SB_CSR);
|
||||||
|
|
||||||
|
// Clear MSELECT reset.
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_V) &= 0xFFFFFFF7;
|
||||||
|
// Clear NONCPU reset.
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x20000000;
|
||||||
|
// Clear CPU0 reset.
|
||||||
|
// < 5.x: 0x411F000F, Clear CPU{0,1,2,3} POR and CORE, CX0, L2, and DBG reset.
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x41010001;
|
||||||
|
}
|
37
source/soc/cluster.h
Normal file
37
source/soc/cluster.h
Normal file
@ -0,0 +1,37 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _CLUSTER_H_
|
||||||
|
#define _CLUSTER_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
/*! Flow controller registers. */
|
||||||
|
#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
|
||||||
|
#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
|
||||||
|
#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C
|
||||||
|
#define FLOW_CTLR_HALT_CPU3_EVENTS 0x24
|
||||||
|
#define FLOW_CTLR_HALT_COP_EVENTS 0x4
|
||||||
|
#define FLOW_CTLR_CPU0_CSR 0x8
|
||||||
|
#define FLOW_CTLR_CPU1_CSR 0x18
|
||||||
|
#define FLOW_CTLR_CPU2_CSR 0x20
|
||||||
|
#define FLOW_CTLR_CPU3_CSR 0x28
|
||||||
|
#define FLOW_CTLR_RAM_REPAIR 0x40
|
||||||
|
#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98
|
||||||
|
|
||||||
|
void cluster_boot_cpu0(u32 entry);
|
||||||
|
|
||||||
|
#endif
|
325
source/soc/fuse.c
Normal file
325
source/soc/fuse.c
Normal file
@ -0,0 +1,325 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (c) 2018 shuffle2
|
||||||
|
* Copyright (c) 2018 balika011
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include "../soc/fuse.h"
|
||||||
|
#include "../soc/t210.h"
|
||||||
|
|
||||||
|
#define ARRAYSIZE(x) (sizeof(x) / sizeof(*x))
|
||||||
|
|
||||||
|
static const u32 evp_thunk_template[] = {
|
||||||
|
0xe92d0007, // STMFD SP!, {R0-R2}
|
||||||
|
0xe1a0200e, // MOV R2, LR
|
||||||
|
0xe2422002, // SUB R2, R2, #2
|
||||||
|
0xe5922000, // LDR R2, [R2]
|
||||||
|
0xe20220ff, // AND R2, R2, #0xFF
|
||||||
|
0xe1a02082, // MOV R2, R2,LSL#1
|
||||||
|
0xe59f001c, // LDR R0, =evp_thunk_template
|
||||||
|
0xe59f101c, // LDR R1, =thunk_end
|
||||||
|
0xe0411000, // SUB R1, R1, R0
|
||||||
|
0xe59f0018, // LDR R0, =iram_evp_thunks
|
||||||
|
0xe0800001, // ADD R0, R0, R1
|
||||||
|
0xe0822000, // ADD R2, R2, R0
|
||||||
|
0xe3822001, // ORR R2, R2, #1
|
||||||
|
0xe8bd0003, // LDMFD SP!, {R0,R1}
|
||||||
|
0xe12fff12, // BX R2
|
||||||
|
0x001007b0, // off_1007EC DCD evp_thunk_template
|
||||||
|
0x001007f8, // off_1007F0 DCD thunk_end
|
||||||
|
0x40004c30, // off_1007F4 DCD iram_evp_thunks
|
||||||
|
// thunk_end is here
|
||||||
|
};
|
||||||
|
static const u32 evp_thunk_template_len = sizeof(evp_thunk_template);
|
||||||
|
|
||||||
|
// treated as 12bit values
|
||||||
|
static const u32 hash_vals[] = {1, 2, 4, 8, 0, 3, 5, 6, 7, 9, 10, 11};
|
||||||
|
|
||||||
|
void fuse_disable_program()
|
||||||
|
{
|
||||||
|
FUSE(FUSE_DISABLEREGPROGRAM) = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 fuse_read_odm(u32 idx)
|
||||||
|
{
|
||||||
|
return FUSE(FUSE_RESERVED_ODMX(idx));
|
||||||
|
}
|
||||||
|
|
||||||
|
void fuse_wait_idle()
|
||||||
|
{
|
||||||
|
u32 ctrl;
|
||||||
|
do
|
||||||
|
{
|
||||||
|
ctrl = FUSE(FUSE_CTRL);
|
||||||
|
} while (((ctrl >> 16) & 0x1f) != 4);
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 parity32_even(u32 *words, u32 count)
|
||||||
|
{
|
||||||
|
u32 acc = words[0];
|
||||||
|
for (u32 i = 1; i < count; i++)
|
||||||
|
{
|
||||||
|
acc ^= words[i];
|
||||||
|
}
|
||||||
|
u32 lo = ((acc & 0xffff) ^ (acc >> 16)) & 0xff;
|
||||||
|
u32 hi = ((acc & 0xffff) ^ (acc >> 16)) >> 8;
|
||||||
|
u32 x = hi ^ lo;
|
||||||
|
lo = ((x & 0xf) ^ (x >> 4)) & 3;
|
||||||
|
hi = ((x & 0xf) ^ (x >> 4)) >> 2;
|
||||||
|
x = hi ^ lo;
|
||||||
|
|
||||||
|
return (x & 1) ^ (x >> 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
int patch_hash_one(u32 *word)
|
||||||
|
{
|
||||||
|
u32 bits20_31 = *word & 0xfff00000;
|
||||||
|
u32 parity_bit = parity32_even(&bits20_31, 1);
|
||||||
|
u32 hash = 0;
|
||||||
|
for (u32 i = 0; i < 12; i++)
|
||||||
|
{
|
||||||
|
if (*word & (1 << (20 + i)))
|
||||||
|
{
|
||||||
|
hash ^= hash_vals[i];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (hash == 0)
|
||||||
|
{
|
||||||
|
if (parity_bit == 0)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
*word ^= 1 << 24;
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
if (parity_bit == 0)
|
||||||
|
{
|
||||||
|
return 3;
|
||||||
|
}
|
||||||
|
for (u32 i = 0; i < ARRAYSIZE(hash_vals); i++)
|
||||||
|
{
|
||||||
|
if (hash_vals[i] == hash)
|
||||||
|
{
|
||||||
|
*word ^= 1 << (20 + i);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 2;
|
||||||
|
}
|
||||||
|
|
||||||
|
int patch_hash_multi(u32 *words, u32 count)
|
||||||
|
{
|
||||||
|
u32 parity_bit = parity32_even(words, count);
|
||||||
|
u32 bits0_14 = words[0] & 0x7fff;
|
||||||
|
u32 bit15 = words[0] & 0x8000;
|
||||||
|
u32 bits16_19 = words[0] & 0xf0000;
|
||||||
|
|
||||||
|
u32 hash = 0;
|
||||||
|
words[0] = bits16_19;
|
||||||
|
for (u32 i = 0; i < count; i++)
|
||||||
|
{
|
||||||
|
u32 w = words[i];
|
||||||
|
if (w)
|
||||||
|
{
|
||||||
|
for (u32 bitpos = 0; bitpos < 32; bitpos++)
|
||||||
|
{
|
||||||
|
if ((w >> bitpos) & 1)
|
||||||
|
{
|
||||||
|
hash ^= 0x4000 + i * 32 + bitpos;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
hash ^= bits0_14;
|
||||||
|
// stupid but this is what original code does.
|
||||||
|
// equivalent to original words[0] &= 0xfff00000
|
||||||
|
words[0] = bits16_19 ^ bit15 ^ bits0_14;
|
||||||
|
|
||||||
|
if (hash == 0)
|
||||||
|
{
|
||||||
|
if (parity_bit == 0)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
words[0] ^= 0x8000;
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
if (parity_bit == 0)
|
||||||
|
{
|
||||||
|
return 3;
|
||||||
|
}
|
||||||
|
u32 bitcount = hash - 0x4000;
|
||||||
|
if (bitcount < 16 || bitcount >= count * 32)
|
||||||
|
{
|
||||||
|
u32 num_set = 0;
|
||||||
|
for (u32 bitpos = 0; bitpos < 15; bitpos++)
|
||||||
|
{
|
||||||
|
if ((hash >> bitpos) & 1)
|
||||||
|
{
|
||||||
|
num_set++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (num_set != 1)
|
||||||
|
{
|
||||||
|
return 2;
|
||||||
|
}
|
||||||
|
words[0] ^= hash;
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
words[bitcount / 32] ^= 1 << (hash & 0x1f);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int fuse_read_ipatch(void (*ipatch)(u32 offset, u32 value))
|
||||||
|
{
|
||||||
|
u32 words[80];
|
||||||
|
u32 word_count;
|
||||||
|
u32 word_addr;
|
||||||
|
u32 word0 = 0;
|
||||||
|
u32 total_read = 0;
|
||||||
|
|
||||||
|
word_count = FUSE(FUSE_FIRST_BOOTROM_PATCH_SIZE);
|
||||||
|
word_count &= 0x7f;
|
||||||
|
word_addr = 191;
|
||||||
|
|
||||||
|
while (word_count)
|
||||||
|
{
|
||||||
|
total_read += word_count;
|
||||||
|
if (total_read >= ARRAYSIZE(words))
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (u32 i = 0; i < word_count; i++)
|
||||||
|
{
|
||||||
|
FUSE(FUSE_ADDR) = word_addr--;
|
||||||
|
FUSE(FUSE_CTRL) = (FUSE(FUSE_ADDR) & ~FUSE_CMD_MASK) | FUSE_READ;
|
||||||
|
fuse_wait_idle();
|
||||||
|
words[i] = FUSE(FUSE_RDATA);
|
||||||
|
}
|
||||||
|
|
||||||
|
word0 = words[0];
|
||||||
|
if (patch_hash_multi(words, word_count) >= 2)
|
||||||
|
{
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
u32 ipatch_count = (words[0] >> 16) & 0xf;
|
||||||
|
if (ipatch_count)
|
||||||
|
{
|
||||||
|
for (u32 i = 0; i < ipatch_count; i++)
|
||||||
|
{
|
||||||
|
u32 word = words[i + 1];
|
||||||
|
u32 addr = (word >> 16) * 2;
|
||||||
|
u32 data = word & 0xffff;
|
||||||
|
|
||||||
|
ipatch(addr, data);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
words[0] = word0;
|
||||||
|
if ((word0 >> 25) == 0)
|
||||||
|
break;
|
||||||
|
if (patch_hash_one(&word0) >= 2)
|
||||||
|
{
|
||||||
|
return 3;
|
||||||
|
}
|
||||||
|
word_count = word0 >> 25;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int fuse_read_evp_thunk(u32 *iram_evp_thunks, u32 *iram_evp_thunks_len)
|
||||||
|
{
|
||||||
|
u32 words[80];
|
||||||
|
u32 word_count;
|
||||||
|
u32 word_addr;
|
||||||
|
u32 word0 = 0;
|
||||||
|
u32 total_read = 0;
|
||||||
|
int evp_thunk_written = 0;
|
||||||
|
void *evp_thunk_dst_addr = 0;
|
||||||
|
|
||||||
|
memset(iram_evp_thunks, 0, *iram_evp_thunks_len);
|
||||||
|
|
||||||
|
word_count = FUSE(FUSE_FIRST_BOOTROM_PATCH_SIZE);
|
||||||
|
word_count &= 0x7f;
|
||||||
|
word_addr = 191;
|
||||||
|
|
||||||
|
while (word_count)
|
||||||
|
{
|
||||||
|
total_read += word_count;
|
||||||
|
if (total_read >= ARRAYSIZE(words))
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (u32 i = 0; i < word_count; i++)
|
||||||
|
{
|
||||||
|
FUSE(FUSE_ADDR) = word_addr--;
|
||||||
|
FUSE(FUSE_CTRL) = (FUSE(FUSE_ADDR) & ~FUSE_CMD_MASK) | FUSE_READ;
|
||||||
|
fuse_wait_idle();
|
||||||
|
words[i] = FUSE(FUSE_RDATA);
|
||||||
|
}
|
||||||
|
|
||||||
|
word0 = words[0];
|
||||||
|
if (patch_hash_multi(words, word_count) >= 2)
|
||||||
|
{
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
u32 ipatch_count = (words[0] >> 16) & 0xf;
|
||||||
|
u32 insn_count = word_count - ipatch_count - 1;
|
||||||
|
if (insn_count)
|
||||||
|
{
|
||||||
|
if (!evp_thunk_written)
|
||||||
|
{
|
||||||
|
evp_thunk_dst_addr = (void *)iram_evp_thunks;
|
||||||
|
|
||||||
|
memcpy(evp_thunk_dst_addr, (void *)evp_thunk_template, evp_thunk_template_len);
|
||||||
|
evp_thunk_dst_addr += evp_thunk_template_len;
|
||||||
|
evp_thunk_written = 1;
|
||||||
|
*iram_evp_thunks_len = evp_thunk_template_len;
|
||||||
|
|
||||||
|
//write32(TEGRA_EXCEPTION_VECTORS_BASE + 0x208, iram_evp_thunks);
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 thunk_patch_len = insn_count * sizeof(u32);
|
||||||
|
memcpy(evp_thunk_dst_addr, &words[ipatch_count + 1], thunk_patch_len);
|
||||||
|
evp_thunk_dst_addr += thunk_patch_len;
|
||||||
|
*iram_evp_thunks_len += thunk_patch_len;
|
||||||
|
}
|
||||||
|
words[0] = word0;
|
||||||
|
if ((word0 >> 25) == 0)
|
||||||
|
break;
|
||||||
|
if (patch_hash_one(&word0) >= 2)
|
||||||
|
{
|
||||||
|
return 3;
|
||||||
|
}
|
||||||
|
word_count = word0 >> 25;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void read_raw_ipatch_fuses(u32 *words)
|
||||||
|
{
|
||||||
|
for (u32 i = 0; i < 0x100; i++)
|
||||||
|
{
|
||||||
|
FUSE(FUSE_ADDR) = i;
|
||||||
|
FUSE(FUSE_CTRL) = (FUSE(FUSE_ADDR) & ~FUSE_CMD_MASK) | FUSE_READ;
|
||||||
|
fuse_wait_idle();
|
||||||
|
words[i] = FUSE(FUSE_RDATA);
|
||||||
|
}
|
||||||
|
}
|
62
source/soc/fuse.h
Normal file
62
source/soc/fuse.h
Normal file
@ -0,0 +1,62 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (c) 2018 shuffle2
|
||||||
|
* Copyright (c) 2018 balika011
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _FUSE_H_
|
||||||
|
#define _FUSE_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
/*! Fuse registers. */
|
||||||
|
#define FUSE_CTRL 0x0
|
||||||
|
#define FUSE_ADDR 0x4
|
||||||
|
#define FUSE_RDATA 0x8
|
||||||
|
#define FUSE_WDATA 0xC
|
||||||
|
#define FUSE_TIME_RD1 0x10
|
||||||
|
#define FUSE_TIME_RD2 0x14
|
||||||
|
#define FUSE_TIME_PGM1 0x18
|
||||||
|
#define FUSE_TIME_PGM2 0x1C
|
||||||
|
#define FUSE_PRIV2INTFC 0x20
|
||||||
|
#define FUSE_FUSEBYPASS 0x24
|
||||||
|
#define FUSE_PRIVATEKEYDISABLE 0x28
|
||||||
|
#define FUSE_DISABLEREGPROGRAM 0x2C
|
||||||
|
#define FUSE_WRITE_ACCESS_SW 0x30
|
||||||
|
#define FUSE_PWR_GOOD_SW 0x34
|
||||||
|
#define FUSE_SKU_INFO 0x110
|
||||||
|
#define FUSE_FIRST_BOOTROM_PATCH_SIZE 0x19c
|
||||||
|
#define FUSE_PRIVATE_KEY0 0x1A4
|
||||||
|
#define FUSE_PRIVATE_KEY1 0x1A8
|
||||||
|
#define FUSE_PRIVATE_KEY2 0x1AC
|
||||||
|
#define FUSE_PRIVATE_KEY3 0x1B0
|
||||||
|
|
||||||
|
/*! Fuse commands. */
|
||||||
|
#define FUSE_READ 0x1
|
||||||
|
#define FUSE_WRITE 0x2
|
||||||
|
#define FUSE_SENSE 0x3
|
||||||
|
#define FUSE_CMD_MASK 0x3
|
||||||
|
|
||||||
|
/*! Fuse cache registers. */
|
||||||
|
#define FUSE_RESERVED_ODMX(x) (0x1C8 + 4 * (x))
|
||||||
|
|
||||||
|
void fuse_disable_program();
|
||||||
|
u32 fuse_read_odm(u32 idx);
|
||||||
|
void fuse_wait_idle();
|
||||||
|
int fuse_read_ipatch(void (*ipatch)(u32 offset, u32 value));
|
||||||
|
int fuse_read_evp_thunk(u32 *iram_evp_thunks, u32 *iram_evp_thunks_len);
|
||||||
|
void read_raw_ipatch_fuses(u32 *words);
|
||||||
|
|
||||||
|
#endif
|
94
source/soc/gpio.c
Normal file
94
source/soc/gpio.c
Normal file
@ -0,0 +1,94 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "../soc/gpio.h"
|
||||||
|
#include "../soc/t210.h"
|
||||||
|
|
||||||
|
static const u16 _gpio_cnf[31] = {
|
||||||
|
0x000, 0x004, 0x008, 0x00C,
|
||||||
|
0x100, 0x104, 0x108, 0x10C,
|
||||||
|
0x200, 0x204, 0x208, 0x20C,
|
||||||
|
0x300, 0x304, 0x308, 0x30C,
|
||||||
|
0x400, 0x404, 0x408, 0x40C,
|
||||||
|
0x500, 0x504, 0x508, 0x50C,
|
||||||
|
0x600, 0x604, 0x608, 0x60C,
|
||||||
|
0x700, 0x704, 0x708
|
||||||
|
};
|
||||||
|
|
||||||
|
static const u16 _gpio_oe[31] = {
|
||||||
|
0x010, 0x014, 0x018, 0x01C,
|
||||||
|
0x110, 0x114, 0x118, 0x11C,
|
||||||
|
0x210, 0x214, 0x218, 0x21C,
|
||||||
|
0x310, 0x314, 0x318, 0x31C,
|
||||||
|
0x410, 0x414, 0x418, 0x41C,
|
||||||
|
0x510, 0x514, 0x518, 0x51C,
|
||||||
|
0x610, 0x614, 0x618, 0x61C,
|
||||||
|
0x710, 0x714, 0x718
|
||||||
|
};
|
||||||
|
|
||||||
|
static const u16 _gpio_out[31] = {
|
||||||
|
0x020, 0x024, 0x028, 0x02C,
|
||||||
|
0x120, 0x124, 0x128, 0x12C,
|
||||||
|
0x220, 0x224, 0x228, 0x22C,
|
||||||
|
0x320, 0x324, 0x328, 0x32C,
|
||||||
|
0x420, 0x424, 0x428, 0x42C,
|
||||||
|
0x520, 0x524, 0x528, 0x52C,
|
||||||
|
0x620, 0x624, 0x628, 0x62C,
|
||||||
|
0x720, 0x724, 0x728
|
||||||
|
};
|
||||||
|
|
||||||
|
static const u16 _gpio_in[31] = {
|
||||||
|
0x030, 0x034, 0x038, 0x03C,
|
||||||
|
0x130, 0x134, 0x138, 0x13C,
|
||||||
|
0x230, 0x234, 0x238, 0x23C,
|
||||||
|
0x330, 0x334, 0x338, 0x33C,
|
||||||
|
0x430, 0x434, 0x438, 0x43C,
|
||||||
|
0x530, 0x534, 0x538, 0x53C,
|
||||||
|
0x630, 0x634, 0x638, 0x63C,
|
||||||
|
0x730, 0x734, 0x738
|
||||||
|
};
|
||||||
|
|
||||||
|
void gpio_config(u32 port, u32 pins, int mode)
|
||||||
|
{
|
||||||
|
if (mode)
|
||||||
|
GPIO(_gpio_cnf[port]) |= pins;
|
||||||
|
else
|
||||||
|
GPIO(_gpio_cnf[port]) &= ~pins;
|
||||||
|
(void)GPIO(_gpio_cnf[port]);
|
||||||
|
}
|
||||||
|
|
||||||
|
void gpio_output_enable(u32 port, u32 pins, int enable)
|
||||||
|
{
|
||||||
|
if (enable)
|
||||||
|
GPIO(_gpio_oe[port]) |= pins;
|
||||||
|
else
|
||||||
|
GPIO(_gpio_oe[port]) &= ~pins;
|
||||||
|
(void)GPIO(_gpio_oe[port]);
|
||||||
|
}
|
||||||
|
|
||||||
|
void gpio_write(u32 port, u32 pins, int high)
|
||||||
|
{
|
||||||
|
if (high)
|
||||||
|
GPIO(_gpio_out[port]) |= pins;
|
||||||
|
else
|
||||||
|
GPIO(_gpio_out[port]) &= ~pins;
|
||||||
|
(void)GPIO(_gpio_out[port]);
|
||||||
|
}
|
||||||
|
|
||||||
|
int gpio_read(u32 port, u32 pins)
|
||||||
|
{
|
||||||
|
return (GPIO(_gpio_in[port]) & pins) ? 1 : 0;
|
||||||
|
}
|
77
source/soc/gpio.h
Normal file
77
source/soc/gpio.h
Normal file
@ -0,0 +1,77 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _GPIO_H_
|
||||||
|
#define _GPIO_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
#define GPIO_MODE_SPIO 0
|
||||||
|
#define GPIO_MODE_GPIO 1
|
||||||
|
#define GPIO_OUTPUT_DISABLE 0
|
||||||
|
#define GPIO_OUTPUT_ENABLE 1
|
||||||
|
#define GPIO_LOW 0
|
||||||
|
#define GPIO_HIGH 1
|
||||||
|
|
||||||
|
/*! GPIO pins (0-7 for each port). */
|
||||||
|
#define GPIO_PIN_0 (1 << 0)
|
||||||
|
#define GPIO_PIN_1 (1 << 1)
|
||||||
|
#define GPIO_PIN_2 (1 << 2)
|
||||||
|
#define GPIO_PIN_3 (1 << 3)
|
||||||
|
#define GPIO_PIN_4 (1 << 4)
|
||||||
|
#define GPIO_PIN_5 (1 << 5)
|
||||||
|
#define GPIO_PIN_6 (1 << 6)
|
||||||
|
#define GPIO_PIN_7 (1 << 7)
|
||||||
|
|
||||||
|
/*! GPIO ports (A-EE). */
|
||||||
|
#define GPIO_PORT_A 0
|
||||||
|
#define GPIO_PORT_B 1
|
||||||
|
#define GPIO_PORT_C 2
|
||||||
|
#define GPIO_PORT_D 3
|
||||||
|
#define GPIO_PORT_E 4
|
||||||
|
#define GPIO_PORT_F 5
|
||||||
|
#define GPIO_PORT_G 6
|
||||||
|
#define GPIO_PORT_H 7
|
||||||
|
#define GPIO_PORT_I 8
|
||||||
|
#define GPIO_PORT_J 9
|
||||||
|
#define GPIO_PORT_K 10
|
||||||
|
#define GPIO_PORT_L 11
|
||||||
|
#define GPIO_PORT_M 12
|
||||||
|
#define GPIO_PORT_N 13
|
||||||
|
#define GPIO_PORT_O 14
|
||||||
|
#define GPIO_PORT_P 15
|
||||||
|
#define GPIO_PORT_Q 16
|
||||||
|
#define GPIO_PORT_R 17
|
||||||
|
#define GPIO_PORT_S 18
|
||||||
|
#define GPIO_PORT_T 19
|
||||||
|
#define GPIO_PORT_U 20
|
||||||
|
#define GPIO_PORT_V 21
|
||||||
|
#define GPIO_PORT_W 22
|
||||||
|
#define GPIO_PORT_X 23
|
||||||
|
#define GPIO_PORT_Y 24
|
||||||
|
#define GPIO_PORT_Z 25
|
||||||
|
#define GPIO_PORT_AA 26
|
||||||
|
#define GPIO_PORT_BB 27
|
||||||
|
#define GPIO_PORT_CC 28
|
||||||
|
#define GPIO_PORT_DD 29
|
||||||
|
#define GPIO_PORT_EE 30
|
||||||
|
|
||||||
|
void gpio_config(u32 port, u32 pins, int mode);
|
||||||
|
void gpio_output_enable(u32 port, u32 pins, int enable);
|
||||||
|
void gpio_write(u32 port, u32 pins, int high);
|
||||||
|
int gpio_read(u32 port, u32 pins);
|
||||||
|
|
||||||
|
#endif
|
271
source/soc/hw_init.c
Normal file
271
source/soc/hw_init.c
Normal file
@ -0,0 +1,271 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (c) 2018-2019 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include "hw_init.h"
|
||||||
|
#include "../gfx/di.h"
|
||||||
|
#include "../mem/mc.h"
|
||||||
|
#include "../mem/sdram.h"
|
||||||
|
#include "../power/max77620.h"
|
||||||
|
#include "../power/max7762x.h"
|
||||||
|
#include "../sec/se.h"
|
||||||
|
#include "../sec/se_t210.h"
|
||||||
|
#include "../soc/clock.h"
|
||||||
|
#include "../soc/fuse.h"
|
||||||
|
#include "../soc/gpio.h"
|
||||||
|
#include "../soc/i2c.h"
|
||||||
|
#include "../soc/pinmux.h"
|
||||||
|
#include "../soc/pmc.h"
|
||||||
|
#include "../soc/t210.h"
|
||||||
|
#include "../storage/sdmmc.h"
|
||||||
|
#include "../utils/util.h"
|
||||||
|
|
||||||
|
extern sdmmc_t sd_sdmmc;
|
||||||
|
extern boot_cfg_t *b_cfg;
|
||||||
|
|
||||||
|
void _config_oscillators()
|
||||||
|
{
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4;
|
||||||
|
SYSCTR0(SYSCTR0_CNTFID0) = 19200000;
|
||||||
|
TMR(TIMERUS_USEC_CFG) = 0x45F; // For 19.2MHz clk_m.
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x50000071;
|
||||||
|
PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81) | 0xE;
|
||||||
|
PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF) | 0x400000;
|
||||||
|
PMC(APBDEV_PMC_CNTRL2) = (PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF) | 0x1000;
|
||||||
|
PMC(APBDEV_PMC_SCRATCH188) = (PMC(APBDEV_PMC_SCRATCH188) & 0xFCFFFFFF) | 0x2000000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) &= 0xBFFFFFFF;
|
||||||
|
PMC(APBDEV_PMC_TSC_MULT) = (PMC(APBDEV_PMC_TSC_MULT) & 0xFFFF0000) | 0x249F; //0x249F = 19200000 * (16 / 32.768 kHz)
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2;
|
||||||
|
}
|
||||||
|
|
||||||
|
void _config_gpios()
|
||||||
|
{
|
||||||
|
PINMUX_AUX(PINMUX_AUX_UART2_TX) = 0;
|
||||||
|
PINMUX_AUX(PINMUX_AUX_UART3_TX) = 0;
|
||||||
|
|
||||||
|
PINMUX_AUX(PINMUX_AUX_GPIO_PE6) = PINMUX_INPUT_ENABLE;
|
||||||
|
PINMUX_AUX(PINMUX_AUX_GPIO_PH6) = PINMUX_INPUT_ENABLE;
|
||||||
|
|
||||||
|
gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_GPIO);
|
||||||
|
gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_GPIO);
|
||||||
|
gpio_output_enable(GPIO_PORT_G, GPIO_PIN_0, GPIO_OUTPUT_DISABLE);
|
||||||
|
gpio_output_enable(GPIO_PORT_D, GPIO_PIN_1, GPIO_OUTPUT_DISABLE);
|
||||||
|
gpio_output_enable(GPIO_PORT_E, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
|
||||||
|
gpio_output_enable(GPIO_PORT_H, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
|
||||||
|
|
||||||
|
pinmux_config_i2c(I2C_1);
|
||||||
|
pinmux_config_i2c(I2C_5);
|
||||||
|
pinmux_config_uart(0);
|
||||||
|
|
||||||
|
// Configure volume up/down as inputs.
|
||||||
|
gpio_config(GPIO_PORT_X, GPIO_PIN_6, GPIO_MODE_GPIO);
|
||||||
|
gpio_config(GPIO_PORT_X, GPIO_PIN_7, GPIO_MODE_GPIO);
|
||||||
|
gpio_output_enable(GPIO_PORT_X, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
|
||||||
|
gpio_output_enable(GPIO_PORT_X, GPIO_PIN_7, GPIO_OUTPUT_DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
void _config_pmc_scratch()
|
||||||
|
{
|
||||||
|
PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF;
|
||||||
|
PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE;
|
||||||
|
PMC(APBDEV_PMC_SECURE_SCRATCH21) |= 0x10;
|
||||||
|
}
|
||||||
|
|
||||||
|
void _mbist_workaround()
|
||||||
|
{
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock.
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= (1 << 6); // Enable APE clock.
|
||||||
|
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) | 0x8000) & 0xFFFFBFFF;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) |= 0x40800000u;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_CLR) = 0x40;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_CLR) = 0x40000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000;
|
||||||
|
usleep(2);
|
||||||
|
|
||||||
|
I2S(I2S1_CTRL) |= I2S_CTRL_MASTER_EN;
|
||||||
|
I2S(I2S1_CG) &= ~I2S_CG_SLCG_ENABLE;
|
||||||
|
I2S(I2S2_CTRL) |= I2S_CTRL_MASTER_EN;
|
||||||
|
I2S(I2S2_CG) &= ~I2S_CG_SLCG_ENABLE;
|
||||||
|
I2S(I2S3_CTRL) |= I2S_CTRL_MASTER_EN;
|
||||||
|
I2S(I2S3_CG) &= ~I2S_CG_SLCG_ENABLE;
|
||||||
|
I2S(I2S4_CTRL) |= I2S_CTRL_MASTER_EN;
|
||||||
|
I2S(I2S4_CG) &= ~I2S_CG_SLCG_ENABLE;
|
||||||
|
I2S(I2S5_CTRL) |= I2S_CTRL_MASTER_EN;
|
||||||
|
I2S(I2S5_CG) &= ~I2S_CG_SLCG_ENABLE;
|
||||||
|
DISPLAY_A(_DIREG(DC_COM_DSC_TOP_CTL)) |= 4;
|
||||||
|
VIC(0x8C) = 0xFFFFFFFF;
|
||||||
|
usleep(2);
|
||||||
|
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_SET) = 0x40;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_SET) = 0x40000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = 0xC0;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) = 0x80000130;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) = 0x1F00200;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = 0x80400808;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_W) = 0x402000FC;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X) = 0x23000780;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) = 0x300;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA) = 0;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB) = 0;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC) = 0;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) = 0;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE) = 0;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) &= 0x1F7FFFFF;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) &= 0xFFFF3FFF;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) & 0x1FFFFFFF) | 0x80000000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) & 0x1FFFFFFF) | 0x80000000;
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) & 0x1FFFFFFF) | 0x80000000;
|
||||||
|
}
|
||||||
|
|
||||||
|
void _config_se_brom()
|
||||||
|
{
|
||||||
|
// Skip SBK/SSK if sept was run.
|
||||||
|
if (!(b_cfg->boot_cfg & BOOT_CFG_SEPT_RUN))
|
||||||
|
{
|
||||||
|
// Bootrom part we skipped.
|
||||||
|
u32 sbk[4] = {
|
||||||
|
FUSE(FUSE_PRIVATE_KEY0),
|
||||||
|
FUSE(FUSE_PRIVATE_KEY1),
|
||||||
|
FUSE(FUSE_PRIVATE_KEY2),
|
||||||
|
FUSE(FUSE_PRIVATE_KEY3)
|
||||||
|
};
|
||||||
|
// Set SBK to slot 14.
|
||||||
|
se_aes_key_set(14, sbk, 0x10);
|
||||||
|
|
||||||
|
// Lock SBK from being read.
|
||||||
|
SE(SE_KEY_TABLE_ACCESS_REG_OFFSET + 14 * 4) = 0x7E;
|
||||||
|
|
||||||
|
// Lock SSK (although it's not set and unused anyways).
|
||||||
|
SE(SE_KEY_TABLE_ACCESS_REG_OFFSET + 15 * 4) = 0x7E;
|
||||||
|
}
|
||||||
|
|
||||||
|
// This memset needs to happen here, else TZRAM will behave weirdly later on.
|
||||||
|
memset((void *)TZRAM_BASE, 0, 0x10000);
|
||||||
|
PMC(APBDEV_PMC_CRYPTO_OP) = 0;
|
||||||
|
SE(SE_INT_STATUS_REG_OFFSET) = 0x1F;
|
||||||
|
|
||||||
|
// Clear the boot reason to avoid problems later
|
||||||
|
PMC(APBDEV_PMC_SCRATCH200) = 0x0;
|
||||||
|
PMC(APBDEV_PMC_RST_STATUS) = 0x0;
|
||||||
|
APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = (APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) & 0xF0) | (7 << 10);
|
||||||
|
}
|
||||||
|
|
||||||
|
void config_hw()
|
||||||
|
{
|
||||||
|
// Bootrom stuff we skipped by going through rcm.
|
||||||
|
_config_se_brom();
|
||||||
|
//FUSE(FUSE_PRIVATEKEYDISABLE) = 0x11;
|
||||||
|
SYSREG(AHB_AHB_SPARE_REG) &= 0xFFFFFF9F;
|
||||||
|
PMC(APBDEV_PMC_SCRATCH49) = ((PMC(APBDEV_PMC_SCRATCH49) >> 1) << 1) & 0xFFFFFFFD;
|
||||||
|
|
||||||
|
_mbist_workaround();
|
||||||
|
clock_enable_se();
|
||||||
|
|
||||||
|
// Enable fuse clock.
|
||||||
|
clock_enable_fuse(true);
|
||||||
|
// Disable fuse programming.
|
||||||
|
fuse_disable_program();
|
||||||
|
|
||||||
|
mc_enable();
|
||||||
|
|
||||||
|
_config_oscillators();
|
||||||
|
APB_MISC(APB_MISC_PP_PINMUX_GLOBAL) = 0;
|
||||||
|
_config_gpios();
|
||||||
|
|
||||||
|
clock_enable_cl_dvfs();
|
||||||
|
|
||||||
|
clock_enable_i2c(I2C_1);
|
||||||
|
clock_enable_i2c(I2C_5);
|
||||||
|
|
||||||
|
clock_enable_unk2();
|
||||||
|
|
||||||
|
i2c_init(I2C_1);
|
||||||
|
i2c_init(I2C_5);
|
||||||
|
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CNFGBBC, MAX77620_CNFGBBC_RESISTOR_1K);
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1,
|
||||||
|
(1 << 6) | (3 << MAX77620_ONOFFCNFG1_MRT_SHIFT)); // PWR delay for forced shutdown off.
|
||||||
|
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG0,
|
||||||
|
(7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG1,
|
||||||
|
(7 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (1 << MAX77620_FPS_EN_SRC_SHIFT));
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG2,
|
||||||
|
(7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
|
||||||
|
max77620_regulator_config_fps(REGULATOR_LDO4);
|
||||||
|
max77620_regulator_config_fps(REGULATOR_LDO8);
|
||||||
|
max77620_regulator_config_fps(REGULATOR_SD0);
|
||||||
|
max77620_regulator_config_fps(REGULATOR_SD1);
|
||||||
|
max77620_regulator_config_fps(REGULATOR_SD3);
|
||||||
|
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_GPIO3,
|
||||||
|
(4 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (2 << MAX77620_FPS_PD_PERIOD_SHIFT)); // 3.x+
|
||||||
|
|
||||||
|
max77620_regulator_set_voltage(REGULATOR_SD0, 1125000);
|
||||||
|
|
||||||
|
// Fix GPU after warmboot for Linux.
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, 2);
|
||||||
|
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO6, 2);
|
||||||
|
|
||||||
|
_config_pmc_scratch(); // Missing from 4.x+
|
||||||
|
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = (CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3333;
|
||||||
|
|
||||||
|
sdram_init();
|
||||||
|
// bundle lp0 fw instead of loading it from SD as hekate does
|
||||||
|
sdram_lp0_save_params(sdram_get_params_patched());
|
||||||
|
}
|
||||||
|
|
||||||
|
void reconfig_hw_workaround(bool extra_reconfig, u32 magic)
|
||||||
|
{
|
||||||
|
// Re-enable clocks to Audio Processing Engine as a workaround to hanging.
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock.
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= (1 << 6); // Enable APE clock.
|
||||||
|
|
||||||
|
if (extra_reconfig)
|
||||||
|
{
|
||||||
|
msleep(10);
|
||||||
|
PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_SDMMC1_IO_EN;
|
||||||
|
|
||||||
|
clock_disable_cl_dvfs();
|
||||||
|
|
||||||
|
// Disable Joy-con GPIOs.
|
||||||
|
gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO);
|
||||||
|
gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO);
|
||||||
|
gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_SPIO);
|
||||||
|
gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_SPIO);
|
||||||
|
}
|
||||||
|
|
||||||
|
// Power off display.
|
||||||
|
display_end();
|
||||||
|
|
||||||
|
// Enable clock to USBD and init SDMMC1 to avoid hangs with bad hw inits.
|
||||||
|
if (magic == 0xBAADF00D)
|
||||||
|
{
|
||||||
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) |= (1 << 22);
|
||||||
|
sdmmc_init(&sd_sdmmc, SDMMC_1, SDMMC_POWER_3_3, SDMMC_BUS_WIDTH_1, 5, 0);
|
||||||
|
clock_disable_cl_dvfs();
|
||||||
|
|
||||||
|
msleep(200);
|
||||||
|
}
|
||||||
|
}
|
26
source/soc/hw_init.h
Normal file
26
source/soc/hw_init.h
Normal file
@ -0,0 +1,26 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (c) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _HW_INIT_H_
|
||||||
|
#define _HW_INIT_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
void config_hw();
|
||||||
|
void reconfig_hw_workaround(bool extra_reconfig, u32 magic);
|
||||||
|
|
||||||
|
#endif
|
143
source/soc/i2c.c
Normal file
143
source/soc/i2c.c
Normal file
@ -0,0 +1,143 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include "i2c.h"
|
||||||
|
#include "../utils/util.h"
|
||||||
|
|
||||||
|
static u32 i2c_addrs[] = {
|
||||||
|
0x7000C000, 0x7000C400, 0x7000C500,
|
||||||
|
0x7000C700, 0x7000D000, 0x7000D100
|
||||||
|
};
|
||||||
|
|
||||||
|
static void _i2c_wait(vu32 *base)
|
||||||
|
{
|
||||||
|
base[I2C_CONFIG_LOAD] = 0x25;
|
||||||
|
for (u32 i = 0; i < 20; i++)
|
||||||
|
{
|
||||||
|
usleep(1);
|
||||||
|
if (!(base[I2C_CONFIG_LOAD] & 1))
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static int _i2c_send_pkt(u32 idx, u32 x, u8 *buf, u32 size)
|
||||||
|
{
|
||||||
|
if (size > 4)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
u32 tmp = 0;
|
||||||
|
memcpy(&tmp, buf, size);
|
||||||
|
|
||||||
|
vu32 *base = (vu32 *)i2c_addrs[idx];
|
||||||
|
base[I2C_CMD_ADDR0] = x << 1; //Set x (send mode).
|
||||||
|
base[I2C_CMD_DATA1] = tmp; //Set value.
|
||||||
|
base[I2C_CNFG] = (2 * size - 2) | 0x2800; //Set size and send mode.
|
||||||
|
_i2c_wait(base); //Kick transaction.
|
||||||
|
|
||||||
|
base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFFDFF) | 0x200;
|
||||||
|
while (base[I2C_STATUS] & 0x100)
|
||||||
|
;
|
||||||
|
|
||||||
|
if (base[I2C_STATUS] << 28)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int _i2c_recv_pkt(u32 idx, u8 *buf, u32 size, u32 x)
|
||||||
|
{
|
||||||
|
if (size > 8)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
vu32 *base = (vu32 *)i2c_addrs[idx];
|
||||||
|
base[I2C_CMD_ADDR0] = (x << 1) | 1; // Set x (recv mode).
|
||||||
|
base[I2C_CNFG] = (size - 1) << 1 | 0x2840; // Set size and recv mode.
|
||||||
|
_i2c_wait(base); // Kick transaction.
|
||||||
|
|
||||||
|
base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFFDFF) | 0x200;
|
||||||
|
while (base[I2C_STATUS] & 0x100)
|
||||||
|
;
|
||||||
|
|
||||||
|
if (base[I2C_STATUS] << 28)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
u32 tmp = base[I2C_CMD_DATA1]; // Get LS value.
|
||||||
|
if (size > 4)
|
||||||
|
{
|
||||||
|
memcpy(buf, &tmp, 4);
|
||||||
|
tmp = base[I2C_CMD_DATA2]; // Get MS value.
|
||||||
|
memcpy(buf + 4, &tmp, size - 4);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
memcpy(buf, &tmp, size);
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void i2c_init(u32 idx)
|
||||||
|
{
|
||||||
|
vu32 *base = (vu32 *)i2c_addrs[idx];
|
||||||
|
|
||||||
|
base[I2C_CLK_DIVISOR_REGISTER] = 0x50001;
|
||||||
|
base[I2C_BUS_CLEAR_CONFIG] = 0x90003;
|
||||||
|
_i2c_wait(base);
|
||||||
|
|
||||||
|
for (u32 i = 0; i < 10; i++)
|
||||||
|
{
|
||||||
|
usleep(20000);
|
||||||
|
if (base[INTERRUPT_STATUS_REGISTER] & 0x800)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
(vu32)base[I2C_BUS_CLEAR_STATUS];
|
||||||
|
base[INTERRUPT_STATUS_REGISTER] = base[INTERRUPT_STATUS_REGISTER];
|
||||||
|
}
|
||||||
|
|
||||||
|
int i2c_send_buf_small(u32 idx, u32 x, u32 y, u8 *buf, u32 size)
|
||||||
|
{
|
||||||
|
u8 tmp[4];
|
||||||
|
|
||||||
|
if (size > 3)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
tmp[0] = y;
|
||||||
|
memcpy(tmp + 1, buf, size);
|
||||||
|
|
||||||
|
return _i2c_send_pkt(idx, x, tmp, size + 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
int i2c_recv_buf_small(u8 *buf, u32 size, u32 idx, u32 x, u32 y)
|
||||||
|
{
|
||||||
|
int res = _i2c_send_pkt(idx, x, (u8 *)&y, 1);
|
||||||
|
if (res)
|
||||||
|
res = _i2c_recv_pkt(idx, buf, size, x);
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
int i2c_send_byte(u32 idx, u32 x, u32 y, u8 b)
|
||||||
|
{
|
||||||
|
return i2c_send_buf_small(idx, x, y, &b, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
u8 i2c_recv_byte(u32 idx, u32 x, u32 y)
|
||||||
|
{
|
||||||
|
u8 tmp = 0;
|
||||||
|
i2c_recv_buf_small(&tmp, 1, idx, x, y);
|
||||||
|
return tmp;
|
||||||
|
}
|
||||||
|
|
46
source/soc/i2c.h
Normal file
46
source/soc/i2c.h
Normal file
@ -0,0 +1,46 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _I2C_H_
|
||||||
|
#define _I2C_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
#define I2C_1 0
|
||||||
|
#define I2C_2 1
|
||||||
|
#define I2C_3 2
|
||||||
|
#define I2C_4 3
|
||||||
|
#define I2C_5 4
|
||||||
|
#define I2C_6 5
|
||||||
|
|
||||||
|
#define I2C_CNFG 0x00
|
||||||
|
#define I2C_CMD_ADDR0 0x01
|
||||||
|
#define I2C_CMD_DATA1 0x03
|
||||||
|
#define I2C_CMD_DATA2 0x04
|
||||||
|
#define I2C_STATUS 0x07
|
||||||
|
#define INTERRUPT_STATUS_REGISTER 0x1A
|
||||||
|
#define I2C_CLK_DIVISOR_REGISTER 0x1B
|
||||||
|
#define I2C_BUS_CLEAR_CONFIG 0x21
|
||||||
|
#define I2C_BUS_CLEAR_STATUS 0x22
|
||||||
|
#define I2C_CONFIG_LOAD 0x23
|
||||||
|
|
||||||
|
void i2c_init(u32 idx);
|
||||||
|
int i2c_send_buf_small(u32 idx, u32 x, u32 y, u8 *buf, u32 size);
|
||||||
|
int i2c_recv_buf_small(u8 *buf, u32 size, u32 idx, u32 x, u32 y);
|
||||||
|
int i2c_send_byte(u32 idx, u32 x, u32 y, u8 b);
|
||||||
|
u8 i2c_recv_byte(u32 idx, u32 x, u32 y);
|
||||||
|
|
||||||
|
#endif
|
32
source/soc/pinmux.c
Normal file
32
source/soc/pinmux.c
Normal file
@ -0,0 +1,32 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "../soc/pinmux.h"
|
||||||
|
#include "../soc/t210.h"
|
||||||
|
|
||||||
|
void pinmux_config_uart(u32 idx)
|
||||||
|
{
|
||||||
|
PINMUX_AUX(PINMUX_AUX_UARTX_TX(idx)) = 0;
|
||||||
|
PINMUX_AUX(PINMUX_AUX_UARTX_RX(idx)) = PINMUX_INPUT_ENABLE | PINMUX_PULL_UP;
|
||||||
|
PINMUX_AUX(PINMUX_AUX_UARTX_RTS(idx)) = 0;
|
||||||
|
PINMUX_AUX(PINMUX_AUX_UARTX_CTS(idx)) = PINMUX_INPUT_ENABLE | PINMUX_PULL_DOWN;
|
||||||
|
}
|
||||||
|
|
||||||
|
void pinmux_config_i2c(u32 idx)
|
||||||
|
{
|
||||||
|
PINMUX_AUX(PINMUX_AUX_X_I2C_SCL(idx)) = PINMUX_INPUT_ENABLE;
|
||||||
|
PINMUX_AUX(PINMUX_AUX_X_I2C_SDA(idx)) = PINMUX_INPUT_ENABLE;
|
||||||
|
}
|
89
source/soc/pinmux.h
Normal file
89
source/soc/pinmux.h
Normal file
@ -0,0 +1,89 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _PINMUX_H_
|
||||||
|
#define _PINMUX_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
/*! APB MISC registers. */
|
||||||
|
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL 0x8D4
|
||||||
|
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL 0x8D8
|
||||||
|
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98
|
||||||
|
#define APB_MISC_GP_VGPIO_GPIO_MUX_SEL 0xB74
|
||||||
|
|
||||||
|
/*! Pinmux registers. */
|
||||||
|
#define PINMUX_AUX_SDMMC1_CLK 0x00
|
||||||
|
#define PINMUX_AUX_SDMMC1_CMD 0x04
|
||||||
|
#define PINMUX_AUX_SDMMC1_DAT3 0x08
|
||||||
|
#define PINMUX_AUX_SDMMC1_DAT2 0x0C
|
||||||
|
#define PINMUX_AUX_SDMMC1_DAT1 0x10
|
||||||
|
#define PINMUX_AUX_SDMMC1_DAT0 0x14
|
||||||
|
#define PINMUX_AUX_SDMMC3_CLK 0x1C
|
||||||
|
#define PINMUX_AUX_SDMMC3_CMD 0x20
|
||||||
|
#define PINMUX_AUX_SDMMC3_DAT0 0x24
|
||||||
|
#define PINMUX_AUX_SDMMC3_DAT1 0x28
|
||||||
|
#define PINMUX_AUX_SDMMC3_DAT2 0x2C
|
||||||
|
#define PINMUX_AUX_SDMMC3_DAT3 0x30
|
||||||
|
#define PINMUX_AUX_DMIC3_CLK 0xB4
|
||||||
|
#define PINMUX_AUX_UART2_TX 0xF4
|
||||||
|
#define PINMUX_AUX_UART3_TX 0x104
|
||||||
|
#define PINMUX_AUX_WIFI_EN 0x1B4
|
||||||
|
#define PINMUX_AUX_WIFI_RST 0x1B8
|
||||||
|
#define PINMUX_AUX_NFC_EN 0x1D0
|
||||||
|
#define PINMUX_AUX_NFC_INT 0x1D4
|
||||||
|
#define PINMUX_AUX_LCD_BL_PWM 0x1FC
|
||||||
|
#define PINMUX_AUX_LCD_BL_EN 0x200
|
||||||
|
#define PINMUX_AUX_LCD_RST 0x204
|
||||||
|
#define PINMUX_AUX_GPIO_PE6 0x248
|
||||||
|
#define PINMUX_AUX_GPIO_PH6 0x250
|
||||||
|
#define PINMUX_AUX_GPIO_PZ1 0x280
|
||||||
|
/*! 0:UART-A, 1:UART-B, 3:UART-C, 3:UART-D */
|
||||||
|
#define PINMUX_AUX_UARTX_TX(x) (0xE4 + 0x10 * (x))
|
||||||
|
#define PINMUX_AUX_UARTX_RX(x) (0xE8 + 0x10 * (x))
|
||||||
|
#define PINMUX_AUX_UARTX_RTS(x) (0xEC + 0x10 * (x))
|
||||||
|
#define PINMUX_AUX_UARTX_CTS(x) (0xF0 + 0x10 * (x))
|
||||||
|
/*! 0:GEN1, 1:GEN2, 2:GEN3, 3:CAM, 4:PWR */
|
||||||
|
#define PINMUX_AUX_X_I2C_SCL(x) (0xBC + 8 * (x))
|
||||||
|
#define PINMUX_AUX_X_I2C_SDA(x) (0xC0 + 8 * (x))
|
||||||
|
|
||||||
|
#define PINMUX_FUNC_MASK (3 << 0)
|
||||||
|
|
||||||
|
#define PINMUX_PULL_MASK (3 << 2)
|
||||||
|
#define PINMUX_PULL_NONE (0 << 2)
|
||||||
|
#define PINMUX_PULL_DOWN (1 << 2)
|
||||||
|
#define PINMUX_PULL_UP (2 << 2)
|
||||||
|
|
||||||
|
#define PINMUX_TRISTATE (1 << 4)
|
||||||
|
#define PINMUX_PARKED (1 << 5)
|
||||||
|
#define PINMUX_INPUT_ENABLE (1 << 6)
|
||||||
|
#define PINMUX_LOCK (1 << 7)
|
||||||
|
#define PINMUX_LPDR (1 << 8)
|
||||||
|
#define PINMUX_HSM (1 << 9)
|
||||||
|
|
||||||
|
#define PINMUX_IO_HV (1 << 10)
|
||||||
|
#define PINMUX_OPEN_DRAIN (1 << 11)
|
||||||
|
#define PINMUX_SCHMT (1 << 12)
|
||||||
|
|
||||||
|
#define PINMUX_DRIVE_1X (0 << 13)
|
||||||
|
#define PINMUX_DRIVE_2X (1 << 13)
|
||||||
|
#define PINMUX_DRIVE_3X (2 << 13)
|
||||||
|
#define PINMUX_DRIVE_4X (3 << 13)
|
||||||
|
|
||||||
|
void pinmux_config_uart(u32 idx);
|
||||||
|
void pinmux_config_i2c(u32 idx);
|
||||||
|
|
||||||
|
#endif
|
69
source/soc/pmc.h
Normal file
69
source/soc/pmc.h
Normal file
@ -0,0 +1,69 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (c) 2018 st4rk
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _PMC_H_
|
||||||
|
#define _PMC_H_
|
||||||
|
|
||||||
|
/*! PMC registers. */
|
||||||
|
#define APBDEV_PMC_CNTRL 0x0
|
||||||
|
#define PMC_CNTRL_MAIN_RST (1 << 4)
|
||||||
|
#define APBDEV_PMC_SEC_DISABLE 0x4
|
||||||
|
#define APBDEV_PMC_PWRGATE_TOGGLE 0x30
|
||||||
|
#define APBDEV_PMC_PWRGATE_STATUS 0x38
|
||||||
|
#define APBDEV_PMC_NO_IOPOWER 0x44
|
||||||
|
#define APBDEV_PMC_SCRATCH0 0x50
|
||||||
|
#define APBDEV_PMC_SCRATCH1 0x54
|
||||||
|
#define APBDEV_PMC_SCRATCH20 0xA0
|
||||||
|
#define APBDEV_PMC_PWR_DET_VAL 0xE4
|
||||||
|
#define PMC_PWR_DET_SDMMC1_IO_EN (1 << 12)
|
||||||
|
#define APBDEV_PMC_DDR_PWR 0xE8
|
||||||
|
#define APBDEV_PMC_CRYPTO_OP 0xF4
|
||||||
|
#define APBDEV_PMC_SCRATCH33 0x120
|
||||||
|
#define APBDEV_PMC_SCRATCH40 0x13C
|
||||||
|
#define APBDEV_PMC_OSC_EDPD_OVER 0x1A4
|
||||||
|
#define APBDEV_PMC_RST_STATUS 0x1B4
|
||||||
|
#define APBDEV_PMC_IO_DPD_REQ 0x1B8
|
||||||
|
#define APBDEV_PMC_IO_DPD2_REQ 0x1C0
|
||||||
|
#define APBDEV_PMC_VDDP_SEL 0x1CC
|
||||||
|
#define APBDEV_PMC_DDR_CFG 0x1D0
|
||||||
|
#define APBDEV_PMC_SCRATCH45 0x234
|
||||||
|
#define APBDEV_PMC_SCRATCH46 0x238
|
||||||
|
#define APBDEV_PMC_SCRATCH49 0x244
|
||||||
|
#define APBDEV_PMC_TSC_MULT 0x2B4
|
||||||
|
#define APBDEV_PMC_SEC_DISABLE2 0x2C4
|
||||||
|
#define APBDEV_PMC_WEAK_BIAS 0x2C8
|
||||||
|
#define APBDEV_PMC_REG_SHORT 0x2CC
|
||||||
|
#define APBDEV_PMC_SEC_DISABLE3 0x2D8
|
||||||
|
#define APBDEV_PMC_SECURE_SCRATCH21 0x334
|
||||||
|
#define APBDEV_PMC_SECURE_SCRATCH32 0x360
|
||||||
|
#define APBDEV_PMC_SECURE_SCRATCH49 0x3A4
|
||||||
|
#define APBDEV_PMC_CNTRL2 0x440
|
||||||
|
#define APBDEV_PMC_IO_DPD3_REQ 0x45C
|
||||||
|
#define APBDEV_PMC_IO_DPD4_REQ 0x464
|
||||||
|
#define APBDEV_PMC_UTMIP_PAD_CFG1 0x4C4
|
||||||
|
#define APBDEV_PMC_UTMIP_PAD_CFG3 0x4CC
|
||||||
|
#define APBDEV_PMC_DDR_CNTRL 0x4E4
|
||||||
|
#define APBDEV_PMC_SEC_DISABLE4 0x5B0
|
||||||
|
#define APBDEV_PMC_SEC_DISABLE5 0x5B4
|
||||||
|
#define APBDEV_PMC_SEC_DISABLE6 0x5B8
|
||||||
|
#define APBDEV_PMC_SEC_DISABLE7 0x5BC
|
||||||
|
#define APBDEV_PMC_SEC_DISABLE8 0x5C0
|
||||||
|
#define APBDEV_PMC_SCRATCH188 0x810
|
||||||
|
#define APBDEV_PMC_SCRATCH190 0x818
|
||||||
|
#define APBDEV_PMC_SCRATCH200 0x840
|
||||||
|
|
||||||
|
#endif
|
564
source/soc/pmc_lp0_t210.h
Normal file
564
source/soc/pmc_lp0_t210.h
Normal file
@ -0,0 +1,564 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _TEGRA210_PMC_H_
|
||||||
|
#define _TEGRA210_PMC_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
struct tegra_pmc_regs
|
||||||
|
{
|
||||||
|
u32 cntrl;
|
||||||
|
u32 sec_disable;
|
||||||
|
u32 pmc_swrst;
|
||||||
|
u32 wake_mask;
|
||||||
|
u32 wake_lvl;
|
||||||
|
u32 wake_status;
|
||||||
|
u32 sw_wake_status;
|
||||||
|
u32 dpd_pads_oride;
|
||||||
|
u32 dpd_sample;
|
||||||
|
u32 dpd_enable;
|
||||||
|
u32 pwrgate_timer_off;
|
||||||
|
u32 clamp_status;
|
||||||
|
u32 pwrgate_toggle;
|
||||||
|
u32 remove_clamping_cmd;
|
||||||
|
u32 pwrgate_status;
|
||||||
|
u32 pwrgood_timer;
|
||||||
|
u32 blink_timer;
|
||||||
|
u32 no_iopower;
|
||||||
|
u32 pwr_det;
|
||||||
|
u32 pwr_det_latch;
|
||||||
|
u32 scratch0;
|
||||||
|
u32 scratch1;
|
||||||
|
u32 scratch2;
|
||||||
|
u32 scratch3;
|
||||||
|
u32 scratch4;
|
||||||
|
u32 scratch5;
|
||||||
|
u32 scratch6;
|
||||||
|
u32 scratch7;
|
||||||
|
u32 scratch8;
|
||||||
|
u32 scratch9;
|
||||||
|
u32 scratch10;
|
||||||
|
u32 scratch11;
|
||||||
|
u32 scratch12;
|
||||||
|
u32 scratch13;
|
||||||
|
u32 scratch14;
|
||||||
|
u32 scratch15;
|
||||||
|
u32 scratch16;
|
||||||
|
u32 scratch17;
|
||||||
|
u32 scratch18;
|
||||||
|
u32 scratch19;
|
||||||
|
u32 odmdata;
|
||||||
|
u32 scratch21;
|
||||||
|
u32 scratch22;
|
||||||
|
u32 scratch23;
|
||||||
|
u32 secure_scratch0;
|
||||||
|
u32 secure_scratch1;
|
||||||
|
u32 secure_scratch2;
|
||||||
|
u32 secure_scratch3;
|
||||||
|
u32 secure_scratch4;
|
||||||
|
u32 secure_scratch5;
|
||||||
|
u32 cpupwrgood_timer;
|
||||||
|
u32 cpupwroff_timer;
|
||||||
|
u32 pg_mask;
|
||||||
|
u32 pg_mask_1;
|
||||||
|
u32 auto_wake_lvl;
|
||||||
|
u32 auto_wake_lvl_mask;
|
||||||
|
u32 wake_delay;
|
||||||
|
u32 pwr_det_val;
|
||||||
|
u32 ddr_pwr;
|
||||||
|
u32 usb_debounce_del;
|
||||||
|
u32 usb_a0;
|
||||||
|
u32 crypto_op;
|
||||||
|
u32 pllp_wb0_override;
|
||||||
|
u32 scratch24;
|
||||||
|
u32 scratch25;
|
||||||
|
u32 scratch26;
|
||||||
|
u32 scratch27;
|
||||||
|
u32 scratch28;
|
||||||
|
u32 scratch29;
|
||||||
|
u32 scratch30;
|
||||||
|
u32 scratch31;
|
||||||
|
u32 scratch32;
|
||||||
|
u32 scratch33;
|
||||||
|
u32 scratch34;
|
||||||
|
u32 scratch35;
|
||||||
|
u32 scratch36;
|
||||||
|
u32 scratch37;
|
||||||
|
u32 scratch38;
|
||||||
|
u32 scratch39;
|
||||||
|
u32 scratch40;
|
||||||
|
u32 scratch41;
|
||||||
|
u32 scratch42;
|
||||||
|
u32 bondout_mirror[3];
|
||||||
|
u32 sys_33v_en;
|
||||||
|
u32 bondout_mirror_access;
|
||||||
|
u32 gate;
|
||||||
|
u32 wake2_mask;
|
||||||
|
u32 wake2_lvl;
|
||||||
|
u32 wake2_status;
|
||||||
|
u32 sw_wake2_status;
|
||||||
|
u32 auto_wake2_lvl_mask;
|
||||||
|
u32 pg_mask_2;
|
||||||
|
u32 pg_mask_ce1;
|
||||||
|
u32 pg_mask_ce2;
|
||||||
|
u32 pg_mask_ce3;
|
||||||
|
u32 pwrgate_timer_ce[7];
|
||||||
|
u32 pcx_edpd_cntrl;
|
||||||
|
u32 osc_edpd_over;
|
||||||
|
u32 clk_out_cntrl;
|
||||||
|
u32 sata_pwrgt;
|
||||||
|
u32 sensor_ctrl;
|
||||||
|
u32 rst_status;
|
||||||
|
u32 io_dpd_req;
|
||||||
|
u32 io_dpd_status;
|
||||||
|
u32 io_dpd2_req;
|
||||||
|
u32 io_dpd2_status;
|
||||||
|
u32 sel_dpd_tim;
|
||||||
|
u32 vddp_sel;
|
||||||
|
u32 ddr_cfg;
|
||||||
|
u32 e_no_vttgen;
|
||||||
|
u8 _rsv0[4];
|
||||||
|
u32 pllm_wb0_override_freq;
|
||||||
|
u32 test_pwrgate;
|
||||||
|
u32 pwrgate_timer_mult;
|
||||||
|
u32 dis_sel_dpd;
|
||||||
|
u32 utmip_uhsic_triggers;
|
||||||
|
u32 utmip_uhsic_saved_state;
|
||||||
|
u32 utmip_pad_cfg;
|
||||||
|
u32 utmip_term_pad_cfg;
|
||||||
|
u32 utmip_uhsic_sleep_cfg;
|
||||||
|
u32 utmip_uhsic_sleepwalk_cfg;
|
||||||
|
u32 utmip_sleepwalk_p[3];
|
||||||
|
u32 uhsic_sleepwalk_p0;
|
||||||
|
u32 utmip_uhsic_status;
|
||||||
|
u32 utmip_uhsic_fake;
|
||||||
|
u32 bondout_mirror3[5 - 3];
|
||||||
|
u32 secure_scratch6;
|
||||||
|
u32 secure_scratch7;
|
||||||
|
u32 scratch43;
|
||||||
|
u32 scratch44;
|
||||||
|
u32 scratch45;
|
||||||
|
u32 scratch46;
|
||||||
|
u32 scratch47;
|
||||||
|
u32 scratch48;
|
||||||
|
u32 scratch49;
|
||||||
|
u32 scratch50;
|
||||||
|
u32 scratch51;
|
||||||
|
u32 scratch52;
|
||||||
|
u32 scratch53;
|
||||||
|
u32 scratch54;
|
||||||
|
u32 scratch55;
|
||||||
|
u32 scratch0_eco;
|
||||||
|
u32 por_dpd_ctrl;
|
||||||
|
u32 scratch2_eco;
|
||||||
|
u32 utmip_uhsic_line_wakeup;
|
||||||
|
u32 utmip_bias_master_cntrl;
|
||||||
|
u32 utmip_master_config;
|
||||||
|
u32 td_pwrgate_inter_part_timer;
|
||||||
|
u32 utmip_uhsic2_triggers;
|
||||||
|
u32 utmip_uhsic2_saved_state;
|
||||||
|
u32 utmip_uhsic2_sleep_cfg;
|
||||||
|
u32 utmip_uhsic2_sleepwalk_cfg;
|
||||||
|
u32 uhsic2_sleepwalk_p1;
|
||||||
|
u32 utmip_uhsic2_status;
|
||||||
|
u32 utmip_uhsic2_fake;
|
||||||
|
u32 utmip_uhsic2_line_wakeup;
|
||||||
|
u32 utmip_master2_config;
|
||||||
|
u32 utmip_uhsic_rpd_cfg;
|
||||||
|
u32 pg_mask_ce0;
|
||||||
|
u32 pg_mask3[5 - 3];
|
||||||
|
u32 pllm_wb0_override2;
|
||||||
|
u32 tsc_mult;
|
||||||
|
u32 cpu_vsense_override;
|
||||||
|
u32 glb_amap_cfg;
|
||||||
|
u32 sticky_bits;
|
||||||
|
u32 sec_disable2;
|
||||||
|
u32 weak_bias;
|
||||||
|
u32 reg_short;
|
||||||
|
u32 pg_mask_andor;
|
||||||
|
u8 _rsv1[0x2c];
|
||||||
|
u32 secure_scratch8; /* offset 0x300 */
|
||||||
|
u32 secure_scratch9;
|
||||||
|
u32 secure_scratch10;
|
||||||
|
u32 secure_scratch11;
|
||||||
|
u32 secure_scratch12;
|
||||||
|
u32 secure_scratch13;
|
||||||
|
u32 secure_scratch14;
|
||||||
|
u32 secure_scratch15;
|
||||||
|
u32 secure_scratch16;
|
||||||
|
u32 secure_scratch17;
|
||||||
|
u32 secure_scratch18;
|
||||||
|
u32 secure_scratch19;
|
||||||
|
u32 secure_scratch20;
|
||||||
|
u32 secure_scratch21;
|
||||||
|
u32 secure_scratch22;
|
||||||
|
u32 secure_scratch23;
|
||||||
|
u32 secure_scratch24;
|
||||||
|
u32 secure_scratch25;
|
||||||
|
u32 secure_scratch26;
|
||||||
|
u32 secure_scratch27;
|
||||||
|
u32 secure_scratch28;
|
||||||
|
u32 secure_scratch29;
|
||||||
|
u32 secure_scratch30;
|
||||||
|
u32 secure_scratch31;
|
||||||
|
u32 secure_scratch32;
|
||||||
|
u32 secure_scratch33;
|
||||||
|
u32 secure_scratch34;
|
||||||
|
u32 secure_scratch35;
|
||||||
|
u32 secure_scratch36;
|
||||||
|
u32 secure_scratch37;
|
||||||
|
u32 secure_scratch38;
|
||||||
|
u32 secure_scratch39;
|
||||||
|
u32 secure_scratch40;
|
||||||
|
u32 secure_scratch41;
|
||||||
|
u32 secure_scratch42;
|
||||||
|
u32 secure_scratch43;
|
||||||
|
u32 secure_scratch44;
|
||||||
|
u32 secure_scratch45;
|
||||||
|
u32 secure_scratch46;
|
||||||
|
u32 secure_scratch47;
|
||||||
|
u32 secure_scratch48;
|
||||||
|
u32 secure_scratch49;
|
||||||
|
u32 secure_scratch50;
|
||||||
|
u32 secure_scratch51;
|
||||||
|
u32 secure_scratch52;
|
||||||
|
u32 secure_scratch53;
|
||||||
|
u32 secure_scratch54;
|
||||||
|
u32 secure_scratch55;
|
||||||
|
u32 secure_scratch56;
|
||||||
|
u32 secure_scratch57;
|
||||||
|
u32 secure_scratch58;
|
||||||
|
u32 secure_scratch59;
|
||||||
|
u32 secure_scratch60;
|
||||||
|
u32 secure_scratch61;
|
||||||
|
u32 secure_scratch62;
|
||||||
|
u32 secure_scratch63;
|
||||||
|
u32 secure_scratch64;
|
||||||
|
u32 secure_scratch65;
|
||||||
|
u32 secure_scratch66;
|
||||||
|
u32 secure_scratch67;
|
||||||
|
u32 secure_scratch68;
|
||||||
|
u32 secure_scratch69;
|
||||||
|
u32 secure_scratch70;
|
||||||
|
u32 secure_scratch71;
|
||||||
|
u32 secure_scratch72;
|
||||||
|
u32 secure_scratch73;
|
||||||
|
u32 secure_scratch74;
|
||||||
|
u32 secure_scratch75;
|
||||||
|
u32 secure_scratch76;
|
||||||
|
u32 secure_scratch77;
|
||||||
|
u32 secure_scratch78;
|
||||||
|
u32 secure_scratch79;
|
||||||
|
u32 _rsv0x420[8];
|
||||||
|
u32 cntrl2; /* 0x440 */
|
||||||
|
u32 _rsv0x444[2];
|
||||||
|
u32 event_counter; /* 0x44C */
|
||||||
|
u32 fuse_control;
|
||||||
|
u32 scratch1_eco;
|
||||||
|
u32 _rsv0x458[1];
|
||||||
|
u32 io_dpd3_req; /* 0x45C */
|
||||||
|
u32 io_dpd3_status;
|
||||||
|
u32 io_dpd4_req;
|
||||||
|
u32 io_dpd4_status;
|
||||||
|
u32 _rsv0x46C[30];
|
||||||
|
u32 ddr_cntrl; /* 0x4E4 */
|
||||||
|
u32 _rsv0x4E8[70];
|
||||||
|
u32 scratch56; /* 0x600 */
|
||||||
|
u32 scratch57;
|
||||||
|
u32 scratch58;
|
||||||
|
u32 scratch59;
|
||||||
|
u32 scratch60;
|
||||||
|
u32 scratch61;
|
||||||
|
u32 scratch62;
|
||||||
|
u32 scratch63;
|
||||||
|
u32 scratch64;
|
||||||
|
u32 scratch65;
|
||||||
|
u32 scratch66;
|
||||||
|
u32 scratch67;
|
||||||
|
u32 scratch68;
|
||||||
|
u32 scratch69;
|
||||||
|
u32 scratch70;
|
||||||
|
u32 scratch71;
|
||||||
|
u32 scratch72;
|
||||||
|
u32 scratch73;
|
||||||
|
u32 scratch74;
|
||||||
|
u32 scratch75;
|
||||||
|
u32 scratch76;
|
||||||
|
u32 scratch77;
|
||||||
|
u32 scratch78;
|
||||||
|
u32 scratch79;
|
||||||
|
u32 scratch80;
|
||||||
|
u32 scratch81;
|
||||||
|
u32 scratch82;
|
||||||
|
u32 scratch83;
|
||||||
|
u32 scratch84;
|
||||||
|
u32 scratch85;
|
||||||
|
u32 scratch86;
|
||||||
|
u32 scratch87;
|
||||||
|
u32 scratch88;
|
||||||
|
u32 scratch89;
|
||||||
|
u32 scratch90;
|
||||||
|
u32 scratch91;
|
||||||
|
u32 scratch92;
|
||||||
|
u32 scratch93;
|
||||||
|
u32 scratch94;
|
||||||
|
u32 scratch95;
|
||||||
|
u32 scratch96;
|
||||||
|
u32 scratch97;
|
||||||
|
u32 scratch98;
|
||||||
|
u32 scratch99;
|
||||||
|
u32 scratch100;
|
||||||
|
u32 scratch101;
|
||||||
|
u32 scratch102;
|
||||||
|
u32 scratch103;
|
||||||
|
u32 scratch104;
|
||||||
|
u32 scratch105;
|
||||||
|
u32 scratch106;
|
||||||
|
u32 scratch107;
|
||||||
|
u32 scratch108;
|
||||||
|
u32 scratch109;
|
||||||
|
u32 scratch110;
|
||||||
|
u32 scratch111;
|
||||||
|
u32 scratch112;
|
||||||
|
u32 scratch113;
|
||||||
|
u32 scratch114;
|
||||||
|
u32 scratch115;
|
||||||
|
u32 scratch116;
|
||||||
|
u32 scratch117;
|
||||||
|
u32 scratch118;
|
||||||
|
u32 scratch119;
|
||||||
|
u32 scratch120; /* 0x700 */
|
||||||
|
u32 scratch121;
|
||||||
|
u32 scratch122;
|
||||||
|
u32 scratch123;
|
||||||
|
u32 scratch124;
|
||||||
|
u32 scratch125;
|
||||||
|
u32 scratch126;
|
||||||
|
u32 scratch127;
|
||||||
|
u32 scratch128;
|
||||||
|
u32 scratch129;
|
||||||
|
u32 scratch130;
|
||||||
|
u32 scratch131;
|
||||||
|
u32 scratch132;
|
||||||
|
u32 scratch133;
|
||||||
|
u32 scratch134;
|
||||||
|
u32 scratch135;
|
||||||
|
u32 scratch136;
|
||||||
|
u32 scratch137;
|
||||||
|
u32 scratch138;
|
||||||
|
u32 scratch139;
|
||||||
|
u32 scratch140;
|
||||||
|
u32 scratch141;
|
||||||
|
u32 scratch142;
|
||||||
|
u32 scratch143;
|
||||||
|
u32 scratch144;
|
||||||
|
u32 scratch145;
|
||||||
|
u32 scratch146;
|
||||||
|
u32 scratch147;
|
||||||
|
u32 scratch148;
|
||||||
|
u32 scratch149;
|
||||||
|
u32 scratch150;
|
||||||
|
u32 scratch151;
|
||||||
|
u32 scratch152;
|
||||||
|
u32 scratch153;
|
||||||
|
u32 scratch154;
|
||||||
|
u32 scratch155;
|
||||||
|
u32 scratch156;
|
||||||
|
u32 scratch157;
|
||||||
|
u32 scratch158;
|
||||||
|
u32 scratch159;
|
||||||
|
u32 scratch160;
|
||||||
|
u32 scratch161;
|
||||||
|
u32 scratch162;
|
||||||
|
u32 scratch163;
|
||||||
|
u32 scratch164;
|
||||||
|
u32 scratch165;
|
||||||
|
u32 scratch166;
|
||||||
|
u32 scratch167;
|
||||||
|
u32 scratch168;
|
||||||
|
u32 scratch169;
|
||||||
|
u32 scratch170;
|
||||||
|
u32 scratch171;
|
||||||
|
u32 scratch172;
|
||||||
|
u32 scratch173;
|
||||||
|
u32 scratch174;
|
||||||
|
u32 scratch175;
|
||||||
|
u32 scratch176;
|
||||||
|
u32 scratch177;
|
||||||
|
u32 scratch178;
|
||||||
|
u32 scratch179;
|
||||||
|
u32 scratch180;
|
||||||
|
u32 scratch181;
|
||||||
|
u32 scratch182;
|
||||||
|
u32 scratch183;
|
||||||
|
u32 scratch184;
|
||||||
|
u32 scratch185;
|
||||||
|
u32 scratch186;
|
||||||
|
u32 scratch187;
|
||||||
|
u32 scratch188;
|
||||||
|
u32 scratch189;
|
||||||
|
u32 scratch190;
|
||||||
|
u32 scratch191;
|
||||||
|
u32 scratch192;
|
||||||
|
u32 scratch193;
|
||||||
|
u32 scratch194;
|
||||||
|
u32 scratch195;
|
||||||
|
u32 scratch196;
|
||||||
|
u32 scratch197;
|
||||||
|
u32 scratch198;
|
||||||
|
u32 scratch199;
|
||||||
|
u32 scratch200;
|
||||||
|
u32 scratch201;
|
||||||
|
u32 scratch202;
|
||||||
|
u32 scratch203;
|
||||||
|
u32 scratch204;
|
||||||
|
u32 scratch205;
|
||||||
|
u32 scratch206;
|
||||||
|
u32 scratch207;
|
||||||
|
u32 scratch208;
|
||||||
|
u32 scratch209;
|
||||||
|
u32 scratch210;
|
||||||
|
u32 scratch211;
|
||||||
|
u32 scratch212;
|
||||||
|
u32 scratch213;
|
||||||
|
u32 scratch214;
|
||||||
|
u32 scratch215;
|
||||||
|
u32 scratch216;
|
||||||
|
u32 scratch217;
|
||||||
|
u32 scratch218;
|
||||||
|
u32 scratch219;
|
||||||
|
u32 scratch220;
|
||||||
|
u32 scratch221;
|
||||||
|
u32 scratch222;
|
||||||
|
u32 scratch223;
|
||||||
|
u32 scratch224;
|
||||||
|
u32 scratch225;
|
||||||
|
u32 scratch226;
|
||||||
|
u32 scratch227;
|
||||||
|
u32 scratch228;
|
||||||
|
u32 scratch229;
|
||||||
|
u32 scratch230;
|
||||||
|
u32 scratch231;
|
||||||
|
u32 scratch232;
|
||||||
|
u32 scratch233;
|
||||||
|
u32 scratch234;
|
||||||
|
u32 scratch235;
|
||||||
|
u32 scratch236;
|
||||||
|
u32 scratch237;
|
||||||
|
u32 scratch238;
|
||||||
|
u32 scratch239;
|
||||||
|
u32 scratch240;
|
||||||
|
u32 scratch241;
|
||||||
|
u32 scratch242;
|
||||||
|
u32 scratch243;
|
||||||
|
u32 scratch244;
|
||||||
|
u32 scratch245;
|
||||||
|
u32 scratch246;
|
||||||
|
u32 scratch247;
|
||||||
|
u32 scratch248;
|
||||||
|
u32 scratch249;
|
||||||
|
u32 scratch250;
|
||||||
|
u32 scratch251;
|
||||||
|
u32 scratch252;
|
||||||
|
u32 scratch253;
|
||||||
|
u32 scratch254;
|
||||||
|
u32 scratch255;
|
||||||
|
u32 scratch256;
|
||||||
|
u32 scratch257;
|
||||||
|
u32 scratch258;
|
||||||
|
u32 scratch259;
|
||||||
|
u32 scratch260;
|
||||||
|
u32 scratch261;
|
||||||
|
u32 scratch262;
|
||||||
|
u32 scratch263;
|
||||||
|
u32 scratch264;
|
||||||
|
u32 scratch265;
|
||||||
|
u32 scratch266;
|
||||||
|
u32 scratch267;
|
||||||
|
u32 scratch268;
|
||||||
|
u32 scratch269;
|
||||||
|
u32 scratch270;
|
||||||
|
u32 scratch271;
|
||||||
|
u32 scratch272;
|
||||||
|
u32 scratch273;
|
||||||
|
u32 scratch274;
|
||||||
|
u32 scratch275;
|
||||||
|
u32 scratch276;
|
||||||
|
u32 scratch277;
|
||||||
|
u32 scratch278;
|
||||||
|
u32 scratch279;
|
||||||
|
u32 scratch280;
|
||||||
|
u32 scratch281;
|
||||||
|
u32 scratch282;
|
||||||
|
u32 scratch283;
|
||||||
|
u32 scratch284;
|
||||||
|
u32 scratch285;
|
||||||
|
u32 scratch286;
|
||||||
|
u32 scratch287;
|
||||||
|
u32 scratch288;
|
||||||
|
u32 scratch289;
|
||||||
|
u32 scratch290;
|
||||||
|
u32 scratch291;
|
||||||
|
u32 scratch292;
|
||||||
|
u32 scratch293;
|
||||||
|
u32 scratch294;
|
||||||
|
u32 scratch295;
|
||||||
|
u32 scratch296;
|
||||||
|
u32 scratch297;
|
||||||
|
u32 scratch298;
|
||||||
|
u32 scratch299; /* 0x9CC */
|
||||||
|
u32 _rsv0x9D0[50];
|
||||||
|
u32 secure_scratch80; /* 0xa98 */
|
||||||
|
u32 secure_scratch81;
|
||||||
|
u32 secure_scratch82;
|
||||||
|
u32 secure_scratch83;
|
||||||
|
u32 secure_scratch84;
|
||||||
|
u32 secure_scratch85;
|
||||||
|
u32 secure_scratch86;
|
||||||
|
u32 secure_scratch87;
|
||||||
|
u32 secure_scratch88;
|
||||||
|
u32 secure_scratch89;
|
||||||
|
u32 secure_scratch90;
|
||||||
|
u32 secure_scratch91;
|
||||||
|
u32 secure_scratch92;
|
||||||
|
u32 secure_scratch93;
|
||||||
|
u32 secure_scratch94;
|
||||||
|
u32 secure_scratch95;
|
||||||
|
u32 secure_scratch96;
|
||||||
|
u32 secure_scratch97;
|
||||||
|
u32 secure_scratch98;
|
||||||
|
u32 secure_scratch99;
|
||||||
|
u32 secure_scratch100;
|
||||||
|
u32 secure_scratch101;
|
||||||
|
u32 secure_scratch102;
|
||||||
|
u32 secure_scratch103;
|
||||||
|
u32 secure_scratch104;
|
||||||
|
u32 secure_scratch105;
|
||||||
|
u32 secure_scratch106;
|
||||||
|
u32 secure_scratch107;
|
||||||
|
u32 secure_scratch108;
|
||||||
|
u32 secure_scratch109;
|
||||||
|
u32 secure_scratch110;
|
||||||
|
u32 secure_scratch111;
|
||||||
|
u32 secure_scratch112;
|
||||||
|
u32 secure_scratch113;
|
||||||
|
u32 secure_scratch114;
|
||||||
|
u32 secure_scratch115;
|
||||||
|
u32 secure_scratch116;
|
||||||
|
u32 secure_scratch117;
|
||||||
|
u32 secure_scratch118;
|
||||||
|
u32 secure_scratch119;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* _TEGRA210_PMC_H_ */
|
171
source/soc/smmu.c
Normal file
171
source/soc/smmu.c
Normal file
@ -0,0 +1,171 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (c) 2018 balika011
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include "smmu.h"
|
||||||
|
#include "../soc/cluster.h"
|
||||||
|
#include "../soc/t210.h"
|
||||||
|
#include "../mem/mc_t210.h"
|
||||||
|
#include "../utils/util.h"
|
||||||
|
#include "../utils/aarch64_util.h"
|
||||||
|
|
||||||
|
bool smmu_used = false;
|
||||||
|
u8 *_pageheap = (u8 *)SMMU_HEAP_ADDR;
|
||||||
|
|
||||||
|
//Enabling SMMU requires a TZ secure write: MC(MC_SMMU_CONFIG) = 1;
|
||||||
|
u8 smmu_payload[] __attribute__((aligned(16))) = {
|
||||||
|
0x41, 0x01, 0x00, 0x58, // 0x00: LDR X1, =0x70019010
|
||||||
|
0x20, 0x00, 0x80, 0xD2, // 0x04: MOV X0, #0x1
|
||||||
|
0x20, 0x00, 0x00, 0xB9, // 0x08: STR W0, [X1]
|
||||||
|
0x1F, 0x71, 0x08, 0xD5, // 0x0C: IC IALLUIS
|
||||||
|
0x9F, 0x3B, 0x03, 0xD5, // 0x10: DSB ISH
|
||||||
|
0xFE, 0xFF, 0xFF, 0x17, // 0x14: B loop
|
||||||
|
0x00, 0x00, 0x80, 0xD2, // 0x18: MOV X0, #0x0
|
||||||
|
0x20, 0x00, 0x00, 0xB9, // 0x1C: STR W0, [X1]
|
||||||
|
0x80, 0x00, 0x00, 0x58, // 0x20: LDR X0, =0x4002B000
|
||||||
|
0x00, 0x00, 0x1F, 0xD6, // 0x28: BR X0
|
||||||
|
0x10, 0x90, 0x01, 0x70, // 0x28: MC_SMMU_CONFIG
|
||||||
|
0x00, 0x00, 0x00, 0x00, // 0x2C:
|
||||||
|
0x00, 0x00, 0x00, 0x00, // 0x30: secmon address
|
||||||
|
0x00, 0x00, 0x00, 0x00 // 0x34:
|
||||||
|
};
|
||||||
|
|
||||||
|
void *page_alloc(u32 num)
|
||||||
|
{
|
||||||
|
u8 *res = _pageheap;
|
||||||
|
_pageheap += 0x1000 * num;
|
||||||
|
memset(res, 0, 0x1000 * num);
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 *smmu_alloc_pdir()
|
||||||
|
{
|
||||||
|
u32 *pdir = (u32 *)page_alloc(1);
|
||||||
|
for (int pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
|
||||||
|
pdir[pdn] = _PDE_VACANT(pdn);
|
||||||
|
return pdir;
|
||||||
|
}
|
||||||
|
|
||||||
|
void smmu_flush_regs()
|
||||||
|
{
|
||||||
|
(void)MC(MC_SMMU_PTB_DATA);
|
||||||
|
}
|
||||||
|
|
||||||
|
void smmu_flush_all()
|
||||||
|
{
|
||||||
|
MC(MC_SMMU_PTC_FLUSH) = 0;
|
||||||
|
smmu_flush_regs();
|
||||||
|
MC(MC_SMMU_TLB_FLUSH) = 0;
|
||||||
|
smmu_flush_regs();
|
||||||
|
}
|
||||||
|
|
||||||
|
void smmu_init(u32 secmon_base)
|
||||||
|
{
|
||||||
|
MC(MC_SMMU_PTB_ASID) = 0;
|
||||||
|
MC(MC_SMMU_PTB_DATA) = 0;
|
||||||
|
MC(MC_SMMU_TLB_CONFIG) = 0x30000030;
|
||||||
|
MC(MC_SMMU_PTC_CONFIG) = 0x28000F3F;
|
||||||
|
MC(MC_SMMU_PTC_FLUSH) = 0;
|
||||||
|
MC(MC_SMMU_TLB_FLUSH) = 0;
|
||||||
|
|
||||||
|
// Set the secmon address
|
||||||
|
*(u32 *)(smmu_payload + 0x30) = secmon_base;
|
||||||
|
}
|
||||||
|
|
||||||
|
void smmu_enable()
|
||||||
|
{
|
||||||
|
if (smmu_used)
|
||||||
|
return;
|
||||||
|
|
||||||
|
cluster_boot_cpu0((u32)smmu_payload);
|
||||||
|
smmu_used = true;
|
||||||
|
msleep(150);
|
||||||
|
|
||||||
|
smmu_flush_all();
|
||||||
|
}
|
||||||
|
|
||||||
|
bool smmu_is_used()
|
||||||
|
{
|
||||||
|
return smmu_used;
|
||||||
|
}
|
||||||
|
|
||||||
|
void smmu_exit()
|
||||||
|
{
|
||||||
|
*(uint32_t *)(smmu_payload + 0x14) = _NOP();
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 *smmu_init_domain4(u32 dev_base, u32 asid)
|
||||||
|
{
|
||||||
|
u32 *pdir = smmu_alloc_pdir();
|
||||||
|
|
||||||
|
MC(MC_SMMU_PTB_ASID) = asid;
|
||||||
|
MC(MC_SMMU_PTB_DATA) = SMMU_MK_PDIR((u32)pdir, _PDIR_ATTR);
|
||||||
|
smmu_flush_regs();
|
||||||
|
|
||||||
|
MC(dev_base) = 0x80000000 | (asid << 24) | (asid << 16) | (asid << 8) | (asid);
|
||||||
|
smmu_flush_regs();
|
||||||
|
|
||||||
|
return pdir;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 *smmu_get_pte(u32 *pdir, u32 iova)
|
||||||
|
{
|
||||||
|
u32 ptn = SMMU_ADDR_TO_PFN(iova);
|
||||||
|
u32 pdn = SMMU_ADDR_TO_PDN(iova);
|
||||||
|
u32 *ptbl;
|
||||||
|
|
||||||
|
if (pdir[pdn] != _PDE_VACANT(pdn))
|
||||||
|
ptbl = (u32 *)((pdir[pdn] & SMMU_PFN_MASK) << SMMU_PDIR_SHIFT);
|
||||||
|
else
|
||||||
|
{
|
||||||
|
ptbl = (u32 *)page_alloc(1);
|
||||||
|
u32 addr = SMMU_PDN_TO_ADDR(pdn);
|
||||||
|
for (int pn = 0; pn < SMMU_PTBL_COUNT; pn++, addr += SMMU_PAGE_SIZE)
|
||||||
|
ptbl[pn] = _PTE_VACANT(addr);
|
||||||
|
pdir[pdn] = SMMU_MK_PDE((u32)ptbl, _PDE_ATTR | _PDE_NEXT);
|
||||||
|
smmu_flush_all();
|
||||||
|
}
|
||||||
|
|
||||||
|
return &ptbl[ptn % SMMU_PTBL_COUNT];
|
||||||
|
}
|
||||||
|
|
||||||
|
void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr)
|
||||||
|
{
|
||||||
|
for (int i = 0; i < cnt; i++)
|
||||||
|
{
|
||||||
|
u32 *pte = smmu_get_pte(pdir, addr);
|
||||||
|
*pte = SMMU_ADDR_TO_PFN(page) | attr;
|
||||||
|
addr += 0x1000;
|
||||||
|
page += 0x1000;
|
||||||
|
}
|
||||||
|
smmu_flush_all();
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 *smmu_init_for_tsec()
|
||||||
|
{
|
||||||
|
return smmu_init_domain4(MC_SMMU_TSEC_ASID, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
void smmu_deinit_for_tsec()
|
||||||
|
{
|
||||||
|
MC(MC_SMMU_PTB_ASID) = 1;
|
||||||
|
MC(MC_SMMU_PTB_DATA) = 0;
|
||||||
|
MC(MC_SMMU_TSEC_ASID) = 0;
|
||||||
|
smmu_flush_regs();
|
||||||
|
}
|
||||||
|
|
82
source/soc/smmu.h
Normal file
82
source/soc/smmu.h
Normal file
@ -0,0 +1,82 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
#define SMMU_HEAP_ADDR 0xA0000000
|
||||||
|
|
||||||
|
#define MC_INTSTATUS 0x0
|
||||||
|
#define MC_INTMASK 0x4
|
||||||
|
#define MC_ERR_STATUS 0x8
|
||||||
|
#define MC_ERR_ADR 0xc
|
||||||
|
#define MC_SMMU_CONFIG 0x10
|
||||||
|
#define MC_SMMU_TLB_CONFIG 0x14
|
||||||
|
#define MC_SMMU_PTC_CONFIG 0x18
|
||||||
|
#define MC_SMMU_PTB_ASID 0x1c
|
||||||
|
#define MC_SMMU_PTB_DATA 0x20
|
||||||
|
#define MC_SMMU_TLB_FLUSH 0x30
|
||||||
|
#define MC_SMMU_PTC_FLUSH 0x34
|
||||||
|
#define MC_SMMU_ASID_SECURITY 0x38
|
||||||
|
#define MC_SMMU_TSEC_ASID 0x294
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_0 0x228
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_2 0x230
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_3 0x234
|
||||||
|
#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98
|
||||||
|
|
||||||
|
#define SMMU_PDE_NEXT_SHIFT 28
|
||||||
|
#define MC_SMMU_PTB_DATA_0_ASID_NONSECURE_SHIFT 29
|
||||||
|
#define MC_SMMU_PTB_DATA_0_ASID_WRITABLE_SHIFT 30
|
||||||
|
#define MC_SMMU_PTB_DATA_0_ASID_READABLE_SHIFT 31
|
||||||
|
#define SMMU_PAGE_SHIFT 12
|
||||||
|
#define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT)
|
||||||
|
#define SMMU_PDIR_COUNT 1024
|
||||||
|
#define SMMU_PDIR_SIZE (sizeof(u32) * SMMU_PDIR_COUNT)
|
||||||
|
#define SMMU_PTBL_COUNT 1024
|
||||||
|
#define SMMU_PTBL_SIZE (sizeof(u32) * SMMU_PTBL_COUNT)
|
||||||
|
#define SMMU_PDIR_SHIFT 12
|
||||||
|
#define SMMU_PDE_SHIFT 12
|
||||||
|
#define SMMU_PTE_SHIFT 12
|
||||||
|
#define SMMU_PFN_MASK 0x000FFFFF
|
||||||
|
#define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
|
||||||
|
#define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
|
||||||
|
#define SMMU_PDN_TO_ADDR(addr) ((pdn) << 22)
|
||||||
|
#define _READABLE (1 << MC_SMMU_PTB_DATA_0_ASID_READABLE_SHIFT)
|
||||||
|
#define _WRITABLE (1 << MC_SMMU_PTB_DATA_0_ASID_WRITABLE_SHIFT)
|
||||||
|
#define _NONSECURE (1 << MC_SMMU_PTB_DATA_0_ASID_NONSECURE_SHIFT)
|
||||||
|
#define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT)
|
||||||
|
#define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE)
|
||||||
|
#define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE)
|
||||||
|
#define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
|
||||||
|
#define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR)
|
||||||
|
#define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
|
||||||
|
#define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
|
||||||
|
#define SMMU_MK_PDIR(page, attr) (((page) >> SMMU_PDIR_SHIFT) | (attr))
|
||||||
|
#define SMMU_MK_PDE(page, attr) (((page) >> SMMU_PDE_SHIFT) | (attr))
|
||||||
|
|
||||||
|
void *page_alloc(u32 num);
|
||||||
|
u32 *smmu_alloc_pdir();
|
||||||
|
void smmu_flush_regs();
|
||||||
|
void smmu_flush_all();
|
||||||
|
void smmu_init(u32 secmon_base);
|
||||||
|
void smmu_enable();
|
||||||
|
bool smmu_is_used();
|
||||||
|
void smmu_exit();
|
||||||
|
u32 *smmu_init_domain4(u32 dev_base, u32 asid);
|
||||||
|
u32 *smmu_get_pte(u32 *pdir, u32 iova);
|
||||||
|
void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr);
|
||||||
|
u32 *smmu_init_for_tsec();
|
||||||
|
void smmu_deinit_for_tsec();
|
186
source/soc/t210.h
Normal file
186
source/soc/t210.h
Normal file
@ -0,0 +1,186 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _T210_H_
|
||||||
|
#define _T210_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
#define BOOTROM_BASE 0x100000
|
||||||
|
#define HOST1X_BASE 0x50000000
|
||||||
|
#define BPMP_CACHE_BASE 0x50040000
|
||||||
|
#define DISPLAY_A_BASE 0x54200000
|
||||||
|
#define DSI_BASE 0x54300000
|
||||||
|
#define VIC_BASE 0x54340000
|
||||||
|
#define TSEC_BASE 0x54500000
|
||||||
|
#define SOR1_BASE 0x54580000
|
||||||
|
#define TMR_BASE 0x60005000
|
||||||
|
#define CLOCK_BASE 0x60006000
|
||||||
|
#define FLOW_CTLR_BASE 0x60007000
|
||||||
|
#define SYSREG_BASE 0x6000C000
|
||||||
|
#define SB_BASE (SYSREG_BASE + 0x200)
|
||||||
|
#define GPIO_BASE 0x6000D000
|
||||||
|
#define GPIO_1_BASE (GPIO_BASE)
|
||||||
|
#define GPIO_2_BASE (GPIO_BASE + 0x100)
|
||||||
|
#define GPIO_3_BASE (GPIO_BASE + 0x200)
|
||||||
|
#define GPIO_4_BASE (GPIO_BASE + 0x300)
|
||||||
|
#define GPIO_5_BASE (GPIO_BASE + 0x400)
|
||||||
|
#define GPIO_6_BASE (GPIO_BASE + 0x500)
|
||||||
|
#define GPIO_7_BASE (GPIO_BASE + 0x600)
|
||||||
|
#define GPIO_8_BASE (GPIO_BASE + 0x700)
|
||||||
|
#define EXCP_VEC_BASE 0x6000F000
|
||||||
|
#define IPATCH_BASE 0x6001DC00
|
||||||
|
#define APB_MISC_BASE 0x70000000
|
||||||
|
#define PINMUX_AUX_BASE 0x70003000
|
||||||
|
#define UART_BASE 0x70006000
|
||||||
|
#define PWM_BASE 0x7000A000
|
||||||
|
#define RTC_BASE 0x7000E000
|
||||||
|
#define PMC_BASE 0x7000E400
|
||||||
|
#define SYSCTR0_BASE 0x700F0000
|
||||||
|
#define FUSE_BASE 0x7000F800
|
||||||
|
#define KFUSE_BASE 0x7000FC00
|
||||||
|
#define SE_BASE 0x70012000
|
||||||
|
#define MC_BASE 0x70019000
|
||||||
|
#define EMC_BASE 0x7001B000
|
||||||
|
#define MIPI_CAL_BASE 0x700E3000
|
||||||
|
#define CL_DVFS_BASE 0x70110000
|
||||||
|
#define I2S_BASE 0x702D1000
|
||||||
|
#define TZRAM_BASE 0x7C010000
|
||||||
|
|
||||||
|
#define _REG(base, off) *(vu32 *)((base) + (off))
|
||||||
|
|
||||||
|
#define HOST1X(off) _REG(HOST1X_BASE, off)
|
||||||
|
#define BPMP_CACHE_CTRL(off) _REG(BPMP_CACHE_BASE, off)
|
||||||
|
#define DISPLAY_A(off) _REG(DISPLAY_A_BASE, off)
|
||||||
|
#define DSI(off) _REG(DSI_BASE, off)
|
||||||
|
#define VIC(off) _REG(VIC_BASE, off)
|
||||||
|
#define TSEC(off) _REG(TSEC_BASE, off)
|
||||||
|
#define SOR1(off) _REG(SOR1_BASE, off)
|
||||||
|
#define TMR(off) _REG(TMR_BASE, off)
|
||||||
|
#define CLOCK(off) _REG(CLOCK_BASE, off)
|
||||||
|
#define FLOW_CTLR(off) _REG(FLOW_CTLR_BASE, off)
|
||||||
|
#define SYSREG(off) _REG(SYSREG_BASE, off)
|
||||||
|
#define SB(off) _REG(SB_BASE, off)
|
||||||
|
#define GPIO(off) _REG(GPIO_BASE, off)
|
||||||
|
#define GPIO_1(off) _REG(GPIO_1_BASE, off)
|
||||||
|
#define GPIO_2(off) _REG(GPIO_2_BASE, off)
|
||||||
|
#define GPIO_3(off) _REG(GPIO_3_BASE, off)
|
||||||
|
#define GPIO_4(off) _REG(GPIO_4_BASE, off)
|
||||||
|
#define GPIO_5(off) _REG(GPIO_5_BASE, off)
|
||||||
|
#define GPIO_6(off) _REG(GPIO_6_BASE, off)
|
||||||
|
#define GPIO_7(off) _REG(GPIO_7_BASE, off)
|
||||||
|
#define GPIO_8(off) _REG(GPIO_8_BASE, off)
|
||||||
|
#define EXCP_VEC(off) _REG(EXCP_VEC_BASE, off)
|
||||||
|
#define APB_MISC(off) _REG(APB_MISC_BASE, off)
|
||||||
|
#define PINMUX_AUX(off) _REG(PINMUX_AUX_BASE, off)
|
||||||
|
#define PWM(off) _REG(PWM_BASE, off)
|
||||||
|
#define RTC(off) _REG(RTC_BASE, off)
|
||||||
|
#define PMC(off) _REG(PMC_BASE, off)
|
||||||
|
#define SYSCTR0(off) _REG(SYSCTR0_BASE, off)
|
||||||
|
#define FUSE(off) _REG(FUSE_BASE, off)
|
||||||
|
#define KFUSE(off) _REG(KFUSE_BASE, off)
|
||||||
|
#define SE(off) _REG(SE_BASE, off)
|
||||||
|
#define MC(off) _REG(MC_BASE, off)
|
||||||
|
#define EMC(off) _REG(EMC_BASE, off)
|
||||||
|
#define MIPI_CAL(off) _REG(MIPI_CAL_BASE, off)
|
||||||
|
#define I2S(off) _REG(I2S_BASE, off)
|
||||||
|
#define CL_DVFS(off) _REG(CL_DVFS_BASE, off)
|
||||||
|
#define TEST_REG(off) _REG(0x0, off)
|
||||||
|
|
||||||
|
/*! EVP registers. */
|
||||||
|
#define EVP_CPU_RESET_VECTOR 0x100
|
||||||
|
|
||||||
|
/*! Misc registers. */
|
||||||
|
#define APB_MISC_PP_STRAPPING_OPT_A 0x08
|
||||||
|
#define APB_MISC_PP_PINMUX_GLOBAL 0x40
|
||||||
|
#define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34
|
||||||
|
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98
|
||||||
|
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4
|
||||||
|
#define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64
|
||||||
|
#define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68
|
||||||
|
|
||||||
|
/*! System registers. */
|
||||||
|
#define AHB_ARBITRATION_XBAR_CTRL 0xE0
|
||||||
|
#define AHB_AHB_SPARE_REG 0x110
|
||||||
|
|
||||||
|
/*! Secure boot registers. */
|
||||||
|
#define SB_CSR 0x0
|
||||||
|
#define SB_AA64_RESET_LOW 0x30
|
||||||
|
#define SB_AA64_RESET_HIGH 0x34
|
||||||
|
|
||||||
|
/*! SOR registers. */
|
||||||
|
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB 0x1E8
|
||||||
|
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB 0x21C
|
||||||
|
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB 0x208
|
||||||
|
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB 0x20C
|
||||||
|
|
||||||
|
/*! RTC registers. */
|
||||||
|
#define APBDEV_RTC_SECONDS 0x8
|
||||||
|
#define APBDEV_RTC_SHADOW_SECONDS 0xC
|
||||||
|
#define APBDEV_RTC_MILLI_SECONDS 0x10
|
||||||
|
|
||||||
|
/*! SYSCTR0 registers. */
|
||||||
|
#define SYSCTR0_CNTFID0 0x20
|
||||||
|
#define SYSCTR0_CNTCR 0x00
|
||||||
|
#define SYSCTR0_COUNTERID0 0xFE0
|
||||||
|
#define SYSCTR0_COUNTERID1 0xFE4
|
||||||
|
#define SYSCTR0_COUNTERID2 0xFE8
|
||||||
|
#define SYSCTR0_COUNTERID3 0xFEC
|
||||||
|
#define SYSCTR0_COUNTERID4 0xFD0
|
||||||
|
#define SYSCTR0_COUNTERID5 0xFD4
|
||||||
|
#define SYSCTR0_COUNTERID6 0xFD8
|
||||||
|
#define SYSCTR0_COUNTERID7 0xFDC
|
||||||
|
#define SYSCTR0_COUNTERID8 0xFF0
|
||||||
|
#define SYSCTR0_COUNTERID9 0xFF4
|
||||||
|
#define SYSCTR0_COUNTERID10 0xFF8
|
||||||
|
#define SYSCTR0_COUNTERID11 0xFFC
|
||||||
|
|
||||||
|
/*! TMR registers. */
|
||||||
|
#define TIMERUS_CNTR_1US (0x10 + 0x0)
|
||||||
|
#define TIMERUS_USEC_CFG (0x10 + 0x4)
|
||||||
|
#define TIMER_TMR9_TMR_PTV 0x80
|
||||||
|
#define TIMER_EN (1 << 31)
|
||||||
|
#define TIMER_PER_EN (1 << 30)
|
||||||
|
#define TIMER_WDT4_CONFIG (0x100 + 0x80)
|
||||||
|
#define TIMER_SRC(TMR) (TMR & 0xF)
|
||||||
|
#define TIMER_PER(PER) ((PER & 0xFF) << 4)
|
||||||
|
#define TIMER_SYSRESET_EN (1 << 14)
|
||||||
|
#define TIMER_PMCRESET_EN (1 << 15)
|
||||||
|
#define TIMER_WDT4_COMMAND (0x108 + 0x80)
|
||||||
|
#define TIMER_START_CNT (1 << 0)
|
||||||
|
#define TIMER_CNT_DISABLE (1 << 1)
|
||||||
|
#define TIMER_WDT4_UNLOCK_PATTERN (0x10C + 0x80)
|
||||||
|
#define TIMER_MAGIC_PTRN 0xC45A
|
||||||
|
|
||||||
|
/*! I2S registers. */
|
||||||
|
#define I2S1_CG 0x88
|
||||||
|
#define I2S1_CTRL 0xA0
|
||||||
|
#define I2S2_CG 0x188
|
||||||
|
#define I2S2_CTRL 0x1A0
|
||||||
|
#define I2S3_CG 0x288
|
||||||
|
#define I2S3_CTRL 0x2A0
|
||||||
|
#define I2S4_CG 0x388
|
||||||
|
#define I2S4_CTRL 0x3A0
|
||||||
|
#define I2S5_CG 0x488
|
||||||
|
#define I2S5_CTRL 0x4A0
|
||||||
|
#define I2S_CG_SLCG_ENABLE (1 << 0)
|
||||||
|
#define I2S_CTRL_MASTER_EN (1 << 10)
|
||||||
|
|
||||||
|
/*! Special registers. */
|
||||||
|
#define EMC_SCRATCH0 0x324
|
||||||
|
#define EMC_SEPT_RUN (1 << 31)
|
||||||
|
|
||||||
|
#endif
|
77
source/start.S
Normal file
77
source/start.S
Normal file
@ -0,0 +1,77 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text._start
|
||||||
|
.arm
|
||||||
|
|
||||||
|
.extern _reloc_ipl
|
||||||
|
.type _reloc_ipl, %function
|
||||||
|
|
||||||
|
.extern memset
|
||||||
|
.type memset, %function
|
||||||
|
|
||||||
|
.extern ipl_main
|
||||||
|
.type ipl_main, %function
|
||||||
|
|
||||||
|
.globl _start
|
||||||
|
.type _start, %function
|
||||||
|
_start:
|
||||||
|
ADR R0, _start
|
||||||
|
LDR R1, =__ipl_start
|
||||||
|
CMP R0, R1
|
||||||
|
BEQ _real_start
|
||||||
|
|
||||||
|
/* If we are not in the right location already, copy a relocator to upper IRAM. */
|
||||||
|
ADR R2, _reloc_ipl
|
||||||
|
LDR R3, =0x4003FF00
|
||||||
|
MOV R4, #(_real_start - _reloc_ipl)
|
||||||
|
_copy_loop:
|
||||||
|
LDMIA R2!, {R5}
|
||||||
|
STMIA R3!, {R5}
|
||||||
|
SUBS R4, #4
|
||||||
|
BNE _copy_loop
|
||||||
|
|
||||||
|
/* Use the relocator to copy ourselves into the right place. */
|
||||||
|
LDR R2, =__ipl_end
|
||||||
|
SUB R2, R2, R1
|
||||||
|
LDR R3, =_real_start
|
||||||
|
LDR R4, =0x4003FF00
|
||||||
|
BX R4
|
||||||
|
|
||||||
|
_reloc_ipl:
|
||||||
|
LDMIA R0!, {R4-R7}
|
||||||
|
STMIA R1!, {R4-R7}
|
||||||
|
SUBS R2, #0x10
|
||||||
|
BNE _reloc_ipl
|
||||||
|
/* Jump to the relocated entry. */
|
||||||
|
BX R3
|
||||||
|
|
||||||
|
_real_start:
|
||||||
|
/* Initially, we place our stack in IRAM but will move it to SDRAM later. */
|
||||||
|
LDR SP, =0x4003FF00
|
||||||
|
LDR R0, =__bss_start
|
||||||
|
EOR R1, R1, R1
|
||||||
|
LDR R2, =__bss_end
|
||||||
|
SUB R2, R2, R0
|
||||||
|
BL memset
|
||||||
|
BL ipl_main
|
||||||
|
B .
|
||||||
|
|
||||||
|
.globl pivot_stack
|
||||||
|
.type pivot_stack, %function
|
||||||
|
pivot_stack:
|
||||||
|
MOV SP, R0
|
||||||
|
BX LR
|
432
source/storage/mmc.h
Normal file
432
source/storage/mmc.h
Normal file
@ -0,0 +1,432 @@
|
|||||||
|
/*
|
||||||
|
* Header for MultiMediaCard (MMC)
|
||||||
|
*
|
||||||
|
* Copyright 2002 Hewlett-Packard Company
|
||||||
|
*
|
||||||
|
* Use consistent with the GNU GPL is permitted,
|
||||||
|
* provided that this copyright notice is
|
||||||
|
* preserved in its entirety in all copies and derived works.
|
||||||
|
*
|
||||||
|
* HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
|
||||||
|
* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
|
||||||
|
* FITNESS FOR ANY PARTICULAR PURPOSE.
|
||||||
|
*
|
||||||
|
* Many thanks to Alessandro Rubini and Jonathan Corbet!
|
||||||
|
*
|
||||||
|
* Based strongly on code by:
|
||||||
|
*
|
||||||
|
* Author: Yong-iL Joh <tolkien@mizi.com>
|
||||||
|
*
|
||||||
|
* Author: Andrew Christian
|
||||||
|
* 15 May 2002
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef LINUX_MMC_MMC_H
|
||||||
|
#define LINUX_MMC_MMC_H
|
||||||
|
|
||||||
|
/* Standard MMC commands (4.1) type argument response */
|
||||||
|
/* class 1 */
|
||||||
|
#define MMC_GO_IDLE_STATE 0 /* bc */
|
||||||
|
#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
|
||||||
|
#define MMC_ALL_SEND_CID 2 /* bcr R2 */
|
||||||
|
#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
|
||||||
|
#define MMC_SET_DSR 4 /* bc [31:16] RCA */
|
||||||
|
#define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */
|
||||||
|
#define MMC_SWITCH 6 /* ac [31:0] See below R1b */
|
||||||
|
#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
|
||||||
|
#define MMC_SEND_EXT_CSD 8 /* adtc R1 */
|
||||||
|
#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
|
||||||
|
#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
|
||||||
|
#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
|
||||||
|
#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
|
||||||
|
#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
|
||||||
|
#define MMC_BUS_TEST_R 14 /* adtc R1 */
|
||||||
|
#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
|
||||||
|
#define MMC_BUS_TEST_W 19 /* adtc R1 */
|
||||||
|
#define MMC_SPI_READ_OCR 58 /* spi spi_R3 */
|
||||||
|
#define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
|
||||||
|
|
||||||
|
/* class 2 */
|
||||||
|
#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
|
||||||
|
#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
|
||||||
|
#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
|
||||||
|
#define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */
|
||||||
|
#define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */
|
||||||
|
|
||||||
|
/* class 3 */
|
||||||
|
#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
|
||||||
|
|
||||||
|
/* class 4 */
|
||||||
|
#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
|
||||||
|
#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
|
||||||
|
#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
|
||||||
|
#define MMC_PROGRAM_CID 26 /* adtc R1 */
|
||||||
|
#define MMC_PROGRAM_CSD 27 /* adtc R1 */
|
||||||
|
|
||||||
|
/* class 6 */
|
||||||
|
#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
|
||||||
|
#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
|
||||||
|
#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
|
||||||
|
|
||||||
|
/* class 5 */
|
||||||
|
#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
|
||||||
|
#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
|
||||||
|
#define MMC_ERASE 38 /* ac R1b */
|
||||||
|
|
||||||
|
/* class 9 */
|
||||||
|
#define MMC_FAST_IO 39 /* ac <Complex> R4 */
|
||||||
|
#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
|
||||||
|
|
||||||
|
/* class 7 */
|
||||||
|
#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
|
||||||
|
|
||||||
|
/* class 8 */
|
||||||
|
#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
|
||||||
|
#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
|
||||||
|
|
||||||
|
/* class 11 */
|
||||||
|
#define MMC_QUE_TASK_PARAMS 44 /* ac [20:16] task id R1 */
|
||||||
|
#define MMC_QUE_TASK_ADDR 45 /* ac [31:0] data addr R1 */
|
||||||
|
#define MMC_EXECUTE_READ_TASK 46 /* adtc [20:16] task id R1 */
|
||||||
|
#define MMC_EXECUTE_WRITE_TASK 47 /* adtc [20:16] task id R1 */
|
||||||
|
#define MMC_CMDQ_TASK_MGMT 48 /* ac [20:16] task id R1b */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MMC_SWITCH argument format:
|
||||||
|
*
|
||||||
|
* [31:26] Always 0
|
||||||
|
* [25:24] Access Mode
|
||||||
|
* [23:16] Location of target Byte in EXT_CSD
|
||||||
|
* [15:08] Value Byte
|
||||||
|
* [07:03] Always 0
|
||||||
|
* [02:00] Command Set
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
MMC status in R1, for native mode (SPI bits are different)
|
||||||
|
Type
|
||||||
|
e : error bit
|
||||||
|
s : status bit
|
||||||
|
r : detected and set for the actual command response
|
||||||
|
x : detected and set during command execution. the host must poll
|
||||||
|
the card by sending status command in order to read these bits.
|
||||||
|
Clear condition
|
||||||
|
a : according to the card state
|
||||||
|
b : always related to the previous command. Reception of
|
||||||
|
a valid command will clear it (with a delay of one command)
|
||||||
|
c : clear by read
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
|
||||||
|
#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
|
||||||
|
#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
|
||||||
|
#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
|
||||||
|
#define R1_ERASE_PARAM (1 << 27) /* ex, c */
|
||||||
|
#define R1_WP_VIOLATION (1 << 26) /* erx, c */
|
||||||
|
#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
|
||||||
|
#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
|
||||||
|
#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
|
||||||
|
#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
|
||||||
|
#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
|
||||||
|
#define R1_CC_ERROR (1 << 20) /* erx, c */
|
||||||
|
#define R1_ERROR (1 << 19) /* erx, c */
|
||||||
|
#define R1_UNDERRUN (1 << 18) /* ex, c */
|
||||||
|
#define R1_OVERRUN (1 << 17) /* ex, c */
|
||||||
|
#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
|
||||||
|
#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
|
||||||
|
#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
|
||||||
|
#define R1_ERASE_RESET (1 << 13) /* sr, c */
|
||||||
|
#define R1_STATUS(x) (x & 0xFFFFE000)
|
||||||
|
#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
|
||||||
|
#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
|
||||||
|
#define R1_SWITCH_ERROR (1 << 7) /* sx, c */
|
||||||
|
#define R1_EXCEPTION_EVENT (1 << 6) /* sr, a */
|
||||||
|
#define R1_APP_CMD (1 << 5) /* sr, c */
|
||||||
|
|
||||||
|
#define R1_STATE_IDLE 0
|
||||||
|
#define R1_STATE_READY 1
|
||||||
|
#define R1_STATE_IDENT 2
|
||||||
|
#define R1_STATE_STBY 3
|
||||||
|
#define R1_STATE_TRAN 4
|
||||||
|
#define R1_STATE_DATA 5
|
||||||
|
#define R1_STATE_RCV 6
|
||||||
|
#define R1_STATE_PRG 7
|
||||||
|
#define R1_STATE_DIS 8
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
|
||||||
|
* R1 is the low order byte; R2 is the next highest byte, when present.
|
||||||
|
*/
|
||||||
|
#define R1_SPI_IDLE (1 << 0)
|
||||||
|
#define R1_SPI_ERASE_RESET (1 << 1)
|
||||||
|
#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
|
||||||
|
#define R1_SPI_COM_CRC (1 << 3)
|
||||||
|
#define R1_SPI_ERASE_SEQ (1 << 4)
|
||||||
|
#define R1_SPI_ADDRESS (1 << 5)
|
||||||
|
#define R1_SPI_PARAMETER (1 << 6)
|
||||||
|
/* R1 bit 7 is always zero */
|
||||||
|
#define R2_SPI_CARD_LOCKED (1 << 8)
|
||||||
|
#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
|
||||||
|
#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
|
||||||
|
#define R2_SPI_ERROR (1 << 10)
|
||||||
|
#define R2_SPI_CC_ERROR (1 << 11)
|
||||||
|
#define R2_SPI_CARD_ECC_ERROR (1 << 12)
|
||||||
|
#define R2_SPI_WP_VIOLATION (1 << 13)
|
||||||
|
#define R2_SPI_ERASE_PARAM (1 << 14)
|
||||||
|
#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
|
||||||
|
#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
|
||||||
|
|
||||||
|
/*
|
||||||
|
* OCR bits are mostly in host.h
|
||||||
|
*/
|
||||||
|
#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Card Command Classes (CCC)
|
||||||
|
*/
|
||||||
|
#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */
|
||||||
|
/* (CMD0,1,2,3,4,7,9,10,12,13,15) */
|
||||||
|
/* (and for SPI, CMD58,59) */
|
||||||
|
#define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */
|
||||||
|
/* (CMD11) */
|
||||||
|
#define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */
|
||||||
|
/* (CMD16,17,18) */
|
||||||
|
#define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */
|
||||||
|
/* (CMD20) */
|
||||||
|
#define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */
|
||||||
|
/* (CMD16,24,25,26,27) */
|
||||||
|
#define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */
|
||||||
|
/* (CMD32,33,34,35,36,37,38,39) */
|
||||||
|
#define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */
|
||||||
|
/* (CMD28,29,30) */
|
||||||
|
#define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */
|
||||||
|
/* (CMD16,CMD42) */
|
||||||
|
#define CCC_APP_SPEC (1<<8) /* (8) Application specific */
|
||||||
|
/* (CMD55,56,57,ACMD*) */
|
||||||
|
#define CCC_IO_MODE (1<<9) /* (9) I/O mode */
|
||||||
|
/* (CMD5,39,40,52,53) */
|
||||||
|
#define CCC_SWITCH (1<<10) /* (10) High speed switch */
|
||||||
|
/* (CMD6,34,35,36,37,50) */
|
||||||
|
/* (11) Reserved */
|
||||||
|
/* (CMD?) */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* CSD field definitions
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
|
||||||
|
#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
|
||||||
|
#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */
|
||||||
|
#define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
|
||||||
|
|
||||||
|
#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
|
||||||
|
#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
|
||||||
|
#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
|
||||||
|
#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */
|
||||||
|
#define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* EXT_CSD fields
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */
|
||||||
|
#define EXT_CSD_FLUSH_CACHE 32 /* W */
|
||||||
|
#define EXT_CSD_CACHE_CTRL 33 /* R/W */
|
||||||
|
#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
|
||||||
|
#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */
|
||||||
|
#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */
|
||||||
|
#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */
|
||||||
|
#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */
|
||||||
|
#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
|
||||||
|
#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
|
||||||
|
#define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */
|
||||||
|
#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
|
||||||
|
#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
|
||||||
|
#define EXT_CSD_HPI_MGMT 161 /* R/W */
|
||||||
|
#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
|
||||||
|
#define EXT_CSD_BKOPS_EN 163 /* R/W */
|
||||||
|
#define EXT_CSD_BKOPS_START 164 /* W */
|
||||||
|
#define EXT_CSD_SANITIZE_START 165 /* W */
|
||||||
|
#define EXT_CSD_WR_REL_PARAM 166 /* RO */
|
||||||
|
#define EXT_CSD_RPMB_MULT 168 /* RO */
|
||||||
|
#define EXT_CSD_FW_CONFIG 169 /* R/W */
|
||||||
|
#define EXT_CSD_BOOT_WP 173 /* R/W */
|
||||||
|
#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
|
||||||
|
#define EXT_CSD_PART_CONFIG 179 /* R/W */
|
||||||
|
#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
|
||||||
|
#define EXT_CSD_BUS_WIDTH 183 /* R/W */
|
||||||
|
#define EXT_CSD_STROBE_SUPPORT 184 /* RO */
|
||||||
|
#define EXT_CSD_HS_TIMING 185 /* R/W */
|
||||||
|
#define EXT_CSD_POWER_CLASS 187 /* R/W */
|
||||||
|
#define EXT_CSD_REV 192 /* RO */
|
||||||
|
#define EXT_CSD_STRUCTURE 194 /* RO */
|
||||||
|
#define EXT_CSD_CARD_TYPE 196 /* RO */
|
||||||
|
#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */
|
||||||
|
#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */
|
||||||
|
#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
|
||||||
|
#define EXT_CSD_PWR_CL_52_195 200 /* RO */
|
||||||
|
#define EXT_CSD_PWR_CL_26_195 201 /* RO */
|
||||||
|
#define EXT_CSD_PWR_CL_52_360 202 /* RO */
|
||||||
|
#define EXT_CSD_PWR_CL_26_360 203 /* RO */
|
||||||
|
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
|
||||||
|
#define EXT_CSD_S_A_TIMEOUT 217 /* RO */
|
||||||
|
#define EXT_CSD_REL_WR_SEC_C 222 /* RO */
|
||||||
|
#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
|
||||||
|
#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
|
||||||
|
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
|
||||||
|
#define EXT_CSD_BOOT_MULT 226 /* RO */
|
||||||
|
#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
|
||||||
|
#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
|
||||||
|
#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
|
||||||
|
#define EXT_CSD_TRIM_MULT 232 /* RO */
|
||||||
|
#define EXT_CSD_PWR_CL_200_195 236 /* RO */
|
||||||
|
#define EXT_CSD_PWR_CL_200_360 237 /* RO */
|
||||||
|
#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */
|
||||||
|
#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */
|
||||||
|
#define EXT_CSD_BKOPS_STATUS 246 /* RO */
|
||||||
|
#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
|
||||||
|
#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
|
||||||
|
#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
|
||||||
|
#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */
|
||||||
|
#define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */
|
||||||
|
#define EXT_CSD_DEVICE_VERSION 262 /* RO, 2 bytes */
|
||||||
|
#define EXT_CSD_PRE_EOL_INFO 267 /* RO */
|
||||||
|
#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268 /* RO */
|
||||||
|
#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269 /* RO */
|
||||||
|
#define EXT_CSD_CMDQ_DEPTH 307 /* RO */
|
||||||
|
#define EXT_CSD_CMDQ_SUPPORT 308 /* RO */
|
||||||
|
#define EXT_CSD_SUPPORTED_MODE 493 /* RO */
|
||||||
|
#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
|
||||||
|
#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
|
||||||
|
#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */
|
||||||
|
#define EXT_CSD_MAX_PACKED_READS 501 /* RO */
|
||||||
|
#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
|
||||||
|
#define EXT_CSD_HPI_FEATURES 503 /* RO */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* EXT_CSD field definitions
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define EXT_CSD_WR_REL_PARAM_EN (1<<2)
|
||||||
|
|
||||||
|
#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40)
|
||||||
|
#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10)
|
||||||
|
#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04)
|
||||||
|
#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
|
||||||
|
|
||||||
|
#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
|
||||||
|
#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
|
||||||
|
#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3)
|
||||||
|
#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
|
||||||
|
|
||||||
|
#define EXT_CSD_PART_SETTING_COMPLETED (0x1)
|
||||||
|
#define EXT_CSD_PART_SUPPORT_PART_EN (0x1)
|
||||||
|
|
||||||
|
#define EXT_CSD_CMD_SET_NORMAL (1<<0)
|
||||||
|
#define EXT_CSD_CMD_SET_SECURE (1<<1)
|
||||||
|
#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
|
||||||
|
|
||||||
|
#define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */
|
||||||
|
#define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */
|
||||||
|
#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \
|
||||||
|
EXT_CSD_CARD_TYPE_HS_52)
|
||||||
|
#define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
|
||||||
|
/* DDR mode @1.8V or 3V I/O */
|
||||||
|
#define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
|
||||||
|
/* DDR mode @1.2V I/O */
|
||||||
|
#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
|
||||||
|
| EXT_CSD_CARD_TYPE_DDR_1_2V)
|
||||||
|
#define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */
|
||||||
|
#define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */
|
||||||
|
/* SDR mode @1.2V I/O */
|
||||||
|
#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
|
||||||
|
EXT_CSD_CARD_TYPE_HS200_1_2V)
|
||||||
|
#define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */
|
||||||
|
#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */
|
||||||
|
#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
|
||||||
|
EXT_CSD_CARD_TYPE_HS400_1_2V)
|
||||||
|
#define EXT_CSD_CARD_TYPE_HS400ES (1<<8) /* Card can run at HS400ES */
|
||||||
|
|
||||||
|
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
|
||||||
|
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
|
||||||
|
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
|
||||||
|
#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
|
||||||
|
#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
|
||||||
|
#define EXT_CSD_BUS_WIDTH_STROBE (1<<7) /* Enhanced strobe mode */
|
||||||
|
|
||||||
|
#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
|
||||||
|
#define EXT_CSD_TIMING_HS 1 /* High speed */
|
||||||
|
#define EXT_CSD_TIMING_HS200 2 /* HS200 */
|
||||||
|
#define EXT_CSD_TIMING_HS400 3 /* HS400 */
|
||||||
|
#define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
|
||||||
|
|
||||||
|
#define EXT_CSD_SEC_ER_EN (1<<0)
|
||||||
|
#define EXT_CSD_SEC_BD_BLK_EN (1<<2)
|
||||||
|
#define EXT_CSD_SEC_GB_CL_EN (1<<4)
|
||||||
|
#define EXT_CSD_SEC_SANITIZE (1<<6) /* v4.5 only */
|
||||||
|
|
||||||
|
#define EXT_CSD_RST_N_EN_MASK 0x3
|
||||||
|
#define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */
|
||||||
|
|
||||||
|
#define EXT_CSD_NO_POWER_NOTIFICATION 0
|
||||||
|
#define EXT_CSD_POWER_ON 1
|
||||||
|
#define EXT_CSD_POWER_OFF_SHORT 2
|
||||||
|
#define EXT_CSD_POWER_OFF_LONG 3
|
||||||
|
|
||||||
|
#define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */
|
||||||
|
#define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */
|
||||||
|
#define EXT_CSD_PWR_CL_8BIT_SHIFT 4
|
||||||
|
#define EXT_CSD_PWR_CL_4BIT_SHIFT 0
|
||||||
|
|
||||||
|
#define EXT_CSD_PACKED_EVENT_EN (1<<3)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* EXCEPTION_EVENT_STATUS field
|
||||||
|
*/
|
||||||
|
#define EXT_CSD_URGENT_BKOPS (1<<0)
|
||||||
|
#define EXT_CSD_DYNCAP_NEEDED (1<<1)
|
||||||
|
#define EXT_CSD_SYSPOOL_EXHAUSTED (1<<2)
|
||||||
|
#define EXT_CSD_PACKED_FAILURE (1<<3)
|
||||||
|
|
||||||
|
#define EXT_CSD_PACKED_GENERIC_ERROR (1<<0)
|
||||||
|
#define EXT_CSD_PACKED_INDEXED_ERROR (1<<1)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* BKOPS status level
|
||||||
|
*/
|
||||||
|
#define EXT_CSD_BKOPS_LEVEL_2 0x2
|
||||||
|
|
||||||
|
/*
|
||||||
|
* BKOPS modes
|
||||||
|
*/
|
||||||
|
#define EXT_CSD_MANUAL_BKOPS_MASK 0x01
|
||||||
|
#define EXT_CSD_AUTO_BKOPS_MASK 0x02
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Command Queue
|
||||||
|
*/
|
||||||
|
#define EXT_CSD_CMDQ_MODE_ENABLED (1<<0)
|
||||||
|
#define EXT_CSD_CMDQ_DEPTH_MASK 0x1F
|
||||||
|
#define EXT_CSD_CMDQ_SUPPORTED (1<<0)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MMC_SWITCH access modes
|
||||||
|
*/
|
||||||
|
#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
|
||||||
|
#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
|
||||||
|
#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
|
||||||
|
#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Erase/trim/discard
|
||||||
|
*/
|
||||||
|
#define MMC_ERASE_ARG 0x00000000
|
||||||
|
#define MMC_SECURE_ERASE_ARG 0x80000000
|
||||||
|
#define MMC_TRIM_ARG 0x00000001
|
||||||
|
#define MMC_DISCARD_ARG 0x00000003
|
||||||
|
#define MMC_SECURE_TRIM1_ARG 0x80000001
|
||||||
|
#define MMC_SECURE_TRIM2_ARG 0x80008000
|
||||||
|
#define MMC_SECURE_ARGS 0x80000000
|
||||||
|
#define MMC_TRIM_ARGS 0x00008001
|
||||||
|
|
||||||
|
#endif /* LINUX_MMC_MMC_H */
|
77
source/storage/nx_emmc.c
Normal file
77
source/storage/nx_emmc.c
Normal file
@ -0,0 +1,77 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include "nx_emmc.h"
|
||||||
|
#include "../mem/heap.h"
|
||||||
|
#include "../utils/list.h"
|
||||||
|
|
||||||
|
void nx_emmc_gpt_parse(link_t *gpt, sdmmc_storage_t *storage)
|
||||||
|
{
|
||||||
|
u8 *buf = (u8 *)malloc(NX_GPT_NUM_BLOCKS * NX_EMMC_BLOCKSIZE);
|
||||||
|
|
||||||
|
sdmmc_storage_read(storage, NX_GPT_FIRST_LBA, NX_GPT_NUM_BLOCKS, buf);
|
||||||
|
|
||||||
|
gpt_header_t *hdr = (gpt_header_t *)buf;
|
||||||
|
for (u32 i = 0; i < hdr->num_part_ents; i++)
|
||||||
|
{
|
||||||
|
gpt_entry_t *ent = (gpt_entry_t *)(buf + (hdr->part_ent_lba - 1) * NX_EMMC_BLOCKSIZE + i * sizeof(gpt_entry_t));
|
||||||
|
emmc_part_t *part = (emmc_part_t *)malloc(sizeof(emmc_part_t));
|
||||||
|
part->lba_start = ent->lba_start;
|
||||||
|
part->lba_end = ent->lba_end;
|
||||||
|
part->attrs = ent->attrs;
|
||||||
|
|
||||||
|
//HACK
|
||||||
|
for (u32 i = 0; i < 36; i++)
|
||||||
|
part->name[i] = ent->name[i];
|
||||||
|
part->name[36] = 0;
|
||||||
|
|
||||||
|
list_append(gpt, &part->link);
|
||||||
|
}
|
||||||
|
|
||||||
|
free(buf);
|
||||||
|
}
|
||||||
|
|
||||||
|
void nx_emmc_gpt_free(link_t *gpt)
|
||||||
|
{
|
||||||
|
LIST_FOREACH_SAFE(iter, gpt)
|
||||||
|
free(CONTAINER_OF(iter, emmc_part_t, link));
|
||||||
|
}
|
||||||
|
|
||||||
|
emmc_part_t *nx_emmc_part_find(link_t *gpt, const char *name)
|
||||||
|
{
|
||||||
|
LIST_FOREACH_ENTRY(emmc_part_t, part, gpt, link)
|
||||||
|
if (!strcmp(part->name, name))
|
||||||
|
return part;
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
int nx_emmc_part_read(sdmmc_storage_t *storage, emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf)
|
||||||
|
{
|
||||||
|
// The last LBA is inclusive.
|
||||||
|
if (part->lba_start + sector_off > part->lba_end)
|
||||||
|
return 0;
|
||||||
|
return sdmmc_storage_read(storage, part->lba_start + sector_off, num_sectors, buf);
|
||||||
|
}
|
||||||
|
|
||||||
|
int nx_emmc_part_write(sdmmc_storage_t *storage, emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf)
|
||||||
|
{
|
||||||
|
// The last LBA is inclusive.
|
||||||
|
if (part->lba_start + sector_off > part->lba_end)
|
||||||
|
return 0;
|
||||||
|
return sdmmc_storage_write(storage, part->lba_start + sector_off, num_sectors, buf);
|
||||||
|
}
|
72
source/storage/nx_emmc.h
Normal file
72
source/storage/nx_emmc.h
Normal file
@ -0,0 +1,72 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _NX_EMMC_H_
|
||||||
|
#define _NX_EMMC_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
#include "../utils/list.h"
|
||||||
|
#include "sdmmc.h"
|
||||||
|
|
||||||
|
typedef struct _gpt_entry_t
|
||||||
|
{
|
||||||
|
u8 type_guid[0x10];
|
||||||
|
u8 part_guid[0x10];
|
||||||
|
u64 lba_start;
|
||||||
|
u64 lba_end;
|
||||||
|
u64 attrs;
|
||||||
|
u16 name[36];
|
||||||
|
} gpt_entry_t;
|
||||||
|
|
||||||
|
typedef struct _gpt_header_t
|
||||||
|
{
|
||||||
|
u64 signature;
|
||||||
|
u32 revision;
|
||||||
|
u32 size;
|
||||||
|
u32 crc32;
|
||||||
|
u32 res1;
|
||||||
|
u64 my_lba;
|
||||||
|
u64 alt_lba;
|
||||||
|
u64 first_use_lba;
|
||||||
|
u64 last_use_lba;
|
||||||
|
u8 disk_guid[0x10];
|
||||||
|
u64 part_ent_lba;
|
||||||
|
u32 num_part_ents;
|
||||||
|
u32 part_ent_size;
|
||||||
|
u32 part_ents_crc32;
|
||||||
|
u8 res2[420];
|
||||||
|
} gpt_header_t;
|
||||||
|
|
||||||
|
#define NX_GPT_FIRST_LBA 1
|
||||||
|
#define NX_GPT_NUM_BLOCKS 33
|
||||||
|
#define NX_EMMC_BLOCKSIZE 512
|
||||||
|
|
||||||
|
typedef struct _emmc_part_t
|
||||||
|
{
|
||||||
|
u32 lba_start;
|
||||||
|
u32 lba_end;
|
||||||
|
u64 attrs;
|
||||||
|
s8 name[37];
|
||||||
|
link_t link;
|
||||||
|
} emmc_part_t;
|
||||||
|
|
||||||
|
void nx_emmc_gpt_parse(link_t *gpt, sdmmc_storage_t *storage);
|
||||||
|
void nx_emmc_gpt_free(link_t *gpt);
|
||||||
|
emmc_part_t *nx_emmc_part_find(link_t *gpt, const char *name);
|
||||||
|
int nx_emmc_part_read(sdmmc_storage_t *storage, emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf);
|
||||||
|
int nx_emmc_part_write(sdmmc_storage_t *storage, emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf);
|
||||||
|
|
||||||
|
#endif
|
124
source/storage/sd.h
Normal file
124
source/storage/sd.h
Normal file
@ -0,0 +1,124 @@
|
|||||||
|
/*
|
||||||
|
* include/linux/mmc/sd.h
|
||||||
|
*
|
||||||
|
* Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
|
||||||
|
* Copyright (C) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or (at
|
||||||
|
* your option) any later version.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef LINUX_MMC_SD_H
|
||||||
|
#define LINUX_MMC_SD_H
|
||||||
|
|
||||||
|
/* SD commands type argument response */
|
||||||
|
/* class 0 */
|
||||||
|
/* This is basically the same command as for MMC with some quirks. */
|
||||||
|
#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */
|
||||||
|
#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */
|
||||||
|
#define SD_SWITCH_VOLTAGE 11 /* ac R1 */
|
||||||
|
|
||||||
|
/* class 10 */
|
||||||
|
#define SD_SWITCH 6 /* adtc [31:0] See below R1 */
|
||||||
|
|
||||||
|
/* class 5 */
|
||||||
|
#define SD_ERASE_WR_BLK_START 32 /* ac [31:0] data addr R1 */
|
||||||
|
#define SD_ERASE_WR_BLK_END 33 /* ac [31:0] data addr R1 */
|
||||||
|
|
||||||
|
/* Application commands */
|
||||||
|
#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
|
||||||
|
#define SD_APP_SD_STATUS 13 /* adtc R1 */
|
||||||
|
#define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */
|
||||||
|
#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */
|
||||||
|
#define SD_APP_SET_CLR_CARD_DETECT 42
|
||||||
|
#define SD_APP_SEND_SCR 51 /* adtc R1 */
|
||||||
|
|
||||||
|
/* OCR bit definitions */
|
||||||
|
#define SD_OCR_S18R (1 << 24) /* 1.8V switching request */
|
||||||
|
#define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */
|
||||||
|
#define SD_OCR_XPC (1 << 28) /* SDXC power control */
|
||||||
|
#define SD_OCR_CCS (1 << 30) /* Card Capacity Status */
|
||||||
|
#define SD_OCR_VDD_32_33 (1 << 20) /* VDD voltage 3.2 ~ 3.3 */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SD_SWITCH argument format:
|
||||||
|
*
|
||||||
|
* [31] Check (0) or switch (1)
|
||||||
|
* [30:24] Reserved (0)
|
||||||
|
* [23:20] Function group 6
|
||||||
|
* [19:16] Function group 5
|
||||||
|
* [15:12] Function group 4
|
||||||
|
* [11:8] Function group 3
|
||||||
|
* [7:4] Function group 2
|
||||||
|
* [3:0] Function group 1
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SD_SEND_IF_COND argument format:
|
||||||
|
*
|
||||||
|
* [31:12] Reserved (0)
|
||||||
|
* [11:8] Host Voltage Supply Flags
|
||||||
|
* [7:0] Check Pattern (0xAA)
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SCR field definitions
|
||||||
|
*/
|
||||||
|
#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */
|
||||||
|
#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */
|
||||||
|
#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00-3.0X */
|
||||||
|
#define SD_SCR_BUS_WIDTH_1 (1<<0)
|
||||||
|
#define SD_SCR_BUS_WIDTH_4 (1<<2)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SD bus widths
|
||||||
|
*/
|
||||||
|
#define SD_BUS_WIDTH_1 0
|
||||||
|
#define SD_BUS_WIDTH_4 2
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SD bus speeds
|
||||||
|
*/
|
||||||
|
#define UHS_SDR12_BUS_SPEED 0
|
||||||
|
#define HIGH_SPEED_BUS_SPEED 1
|
||||||
|
#define UHS_SDR25_BUS_SPEED 1
|
||||||
|
#define UHS_SDR50_BUS_SPEED 2
|
||||||
|
#define UHS_SDR104_BUS_SPEED 3
|
||||||
|
#define UHS_DDR50_BUS_SPEED 4
|
||||||
|
#define HS400_BUS_SPEED 5
|
||||||
|
|
||||||
|
#define SD_MODE_HIGH_SPEED (1 << HIGH_SPEED_BUS_SPEED)
|
||||||
|
#define SD_MODE_UHS_SDR12 (1 << UHS_SDR12_BUS_SPEED)
|
||||||
|
#define SD_MODE_UHS_SDR25 (1 << UHS_SDR25_BUS_SPEED)
|
||||||
|
#define SD_MODE_UHS_SDR50 (1 << UHS_SDR50_BUS_SPEED)
|
||||||
|
#define SD_MODE_UHS_SDR104 (1 << UHS_SDR104_BUS_SPEED)
|
||||||
|
#define SD_MODE_UHS_DDR50 (1 << UHS_DDR50_BUS_SPEED)
|
||||||
|
|
||||||
|
#define SD_DRIVER_TYPE_B 0x01
|
||||||
|
#define SD_DRIVER_TYPE_A 0x02
|
||||||
|
|
||||||
|
#define SD_SET_CURRENT_LIMIT_200 0
|
||||||
|
#define SD_SET_CURRENT_LIMIT_400 1
|
||||||
|
#define SD_SET_CURRENT_LIMIT_600 2
|
||||||
|
#define SD_SET_CURRENT_LIMIT_800 3
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SD_SWITCH mode
|
||||||
|
*/
|
||||||
|
#define SD_SWITCH_CHECK 0
|
||||||
|
#define SD_SWITCH_SET 1
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SD_SWITCH function groups
|
||||||
|
*/
|
||||||
|
#define SD_SWITCH_GRP_ACCESS 0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SD_SWITCH access modes
|
||||||
|
*/
|
||||||
|
#define SD_SWITCH_ACCESS_DEF 0
|
||||||
|
#define SD_SWITCH_ACCESS_HS 1
|
||||||
|
|
||||||
|
#endif /* LINUX_MMC_SD_H */
|
1189
source/storage/sdmmc.c
Normal file
1189
source/storage/sdmmc.c
Normal file
File diff suppressed because it is too large
Load Diff
113
source/storage/sdmmc.h
Normal file
113
source/storage/sdmmc.h
Normal file
@ -0,0 +1,113 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (C) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _SDMMC_H_
|
||||||
|
#define _SDMMC_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
#include "sdmmc_driver.h"
|
||||||
|
|
||||||
|
typedef struct _mmc_cid
|
||||||
|
{
|
||||||
|
u32 manfid;
|
||||||
|
u8 prod_name[8];
|
||||||
|
u8 card_bga;
|
||||||
|
u8 prv;
|
||||||
|
u32 serial;
|
||||||
|
u16 oemid;
|
||||||
|
u16 year;
|
||||||
|
u8 hwrev;
|
||||||
|
u8 fwrev;
|
||||||
|
u8 month;
|
||||||
|
} mmc_cid_t;
|
||||||
|
|
||||||
|
typedef struct _mmc_csd
|
||||||
|
{
|
||||||
|
u8 structure;
|
||||||
|
u8 mmca_vsn;
|
||||||
|
u16 cmdclass;
|
||||||
|
u32 c_size;
|
||||||
|
u32 r2w_factor;
|
||||||
|
u32 max_dtr;
|
||||||
|
u32 erase_size; /* In sectors */
|
||||||
|
u32 read_blkbits;
|
||||||
|
u32 write_blkbits;
|
||||||
|
u32 capacity;
|
||||||
|
u8 write_protect;
|
||||||
|
u16 busspeed;
|
||||||
|
} mmc_csd_t;
|
||||||
|
|
||||||
|
typedef struct _mmc_ext_csd
|
||||||
|
{
|
||||||
|
u8 rev;
|
||||||
|
u32 sectors;
|
||||||
|
int bkops; /* background support bit */
|
||||||
|
int bkops_en; /* manual bkops enable bit */
|
||||||
|
u8 ext_struct; /* 194 */
|
||||||
|
u8 card_type; /* 196 */
|
||||||
|
u8 bkops_status; /* 246 */
|
||||||
|
u16 dev_version;
|
||||||
|
u8 boot_mult;
|
||||||
|
u8 rpmb_mult;
|
||||||
|
} mmc_ext_csd_t;
|
||||||
|
|
||||||
|
typedef struct _sd_scr
|
||||||
|
{
|
||||||
|
u8 sda_vsn;
|
||||||
|
u8 sda_spec3;
|
||||||
|
u8 bus_widths;
|
||||||
|
u8 cmds;
|
||||||
|
} sd_scr_t;
|
||||||
|
|
||||||
|
typedef struct _sd_ssr
|
||||||
|
{
|
||||||
|
u8 bus_width;
|
||||||
|
u8 speed_class;
|
||||||
|
u8 uhs_grade;
|
||||||
|
u8 video_class;
|
||||||
|
u8 app_class;
|
||||||
|
} sd_ssr_t;
|
||||||
|
|
||||||
|
/*! SDMMC storage context. */
|
||||||
|
typedef struct _sdmmc_storage_t
|
||||||
|
{
|
||||||
|
sdmmc_t *sdmmc;
|
||||||
|
u32 rca;
|
||||||
|
int has_sector_access;
|
||||||
|
u32 sec_cnt;
|
||||||
|
int is_low_voltage;
|
||||||
|
u32 partition;
|
||||||
|
u8 raw_cid[0x10];
|
||||||
|
u8 raw_csd[0x10];
|
||||||
|
u8 raw_scr[8];
|
||||||
|
u8 raw_ssr[0x40];
|
||||||
|
mmc_cid_t cid;
|
||||||
|
mmc_csd_t csd;
|
||||||
|
mmc_ext_csd_t ext_csd;
|
||||||
|
sd_scr_t scr;
|
||||||
|
sd_ssr_t ssr;
|
||||||
|
} sdmmc_storage_t;
|
||||||
|
|
||||||
|
int sdmmc_storage_end(sdmmc_storage_t *storage);
|
||||||
|
int sdmmc_storage_read(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, void *buf);
|
||||||
|
int sdmmc_storage_write(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, void *buf);
|
||||||
|
int sdmmc_storage_init_mmc(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 id, u32 bus_width, u32 type);
|
||||||
|
int sdmmc_storage_set_mmc_partition(sdmmc_storage_t *storage, u32 partition);
|
||||||
|
int sdmmc_storage_init_sd(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 id, u32 bus_width, u32 type);
|
||||||
|
int sdmmc_storage_init_gc(sdmmc_storage_t *storage, sdmmc_t *sdmmc);
|
||||||
|
|
||||||
|
#endif
|
1113
source/storage/sdmmc_driver.c
Normal file
1113
source/storage/sdmmc_driver.c
Normal file
File diff suppressed because it is too large
Load Diff
126
source/storage/sdmmc_driver.h
Normal file
126
source/storage/sdmmc_driver.h
Normal file
@ -0,0 +1,126 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _SDMMC_DRIVER_H_
|
||||||
|
#define _SDMMC_DRIVER_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
#include "sdmmc_t210.h"
|
||||||
|
|
||||||
|
/*! SDMMC controller IDs. */
|
||||||
|
#define SDMMC_1 0
|
||||||
|
#define SDMMC_2 1
|
||||||
|
#define SDMMC_3 2
|
||||||
|
#define SDMMC_4 3
|
||||||
|
|
||||||
|
/*! SDMMC power types. */
|
||||||
|
#define SDMMC_POWER_OFF 0
|
||||||
|
#define SDMMC_POWER_1_8 1
|
||||||
|
#define SDMMC_POWER_3_3 2
|
||||||
|
|
||||||
|
/*! SDMMC bus widths. */
|
||||||
|
#define SDMMC_BUS_WIDTH_1 0
|
||||||
|
#define SDMMC_BUS_WIDTH_4 1
|
||||||
|
#define SDMMC_BUS_WIDTH_8 2
|
||||||
|
|
||||||
|
/*! SDMMC response types. */
|
||||||
|
#define SDMMC_RSP_TYPE_0 0
|
||||||
|
#define SDMMC_RSP_TYPE_1 1
|
||||||
|
#define SDMMC_RSP_TYPE_2 2
|
||||||
|
#define SDMMC_RSP_TYPE_3 3
|
||||||
|
#define SDMMC_RSP_TYPE_4 4
|
||||||
|
#define SDMMC_RSP_TYPE_5 5
|
||||||
|
|
||||||
|
/*! SDMMC mask interrupt status. */
|
||||||
|
#define SDMMC_MASKINT_MASKED 0
|
||||||
|
#define SDMMC_MASKINT_NOERROR -1
|
||||||
|
#define SDMMC_MASKINT_ERROR -2
|
||||||
|
|
||||||
|
/*! SDMMC host control 2 */
|
||||||
|
#define SDHCI_CTRL_UHS_MASK 0xFFF8
|
||||||
|
#define SDHCI_CTRL_VDD_330 0xFFF7
|
||||||
|
#define SDHCI_CTRL_VDD_180 8
|
||||||
|
#define SDHCI_CTRL_EXEC_TUNING 0x40
|
||||||
|
#define SDHCI_CTRL_TUNED_CLK 0x80
|
||||||
|
#define SDHCI_HOST_VERSION_4_EN 0x1000
|
||||||
|
#define SDHCI_ADDRESSING_64BIT_EN 0x2000
|
||||||
|
#define SDHCI_CTRL_PRESET_VAL_EN 0x8000
|
||||||
|
|
||||||
|
/*! SD bus speeds. */
|
||||||
|
#define UHS_SDR12_BUS_SPEED 0
|
||||||
|
#define HIGH_SPEED_BUS_SPEED 1
|
||||||
|
#define UHS_SDR25_BUS_SPEED 1
|
||||||
|
#define UHS_SDR50_BUS_SPEED 2
|
||||||
|
#define UHS_SDR104_BUS_SPEED 3
|
||||||
|
#define UHS_DDR50_BUS_SPEED 4
|
||||||
|
#define HS400_BUS_SPEED 5
|
||||||
|
|
||||||
|
/*! Helper for SWITCH command argument. */
|
||||||
|
#define SDMMC_SWITCH(mode, index, value) (((mode) << 24) | ((index) << 16) | ((value) << 8))
|
||||||
|
|
||||||
|
/*! SDMMC controller context. */
|
||||||
|
typedef struct _sdmmc_t
|
||||||
|
{
|
||||||
|
t210_sdmmc_t *regs;
|
||||||
|
u32 id;
|
||||||
|
u32 divisor;
|
||||||
|
u32 clock_stopped;
|
||||||
|
int no_sd;
|
||||||
|
int sd_clock_enabled;
|
||||||
|
int venclkctl_set;
|
||||||
|
u32 venclkctl_tap;
|
||||||
|
u32 expected_rsp_type;
|
||||||
|
u32 dma_addr_next;
|
||||||
|
u32 rsp[4];
|
||||||
|
u32 rsp3;
|
||||||
|
} sdmmc_t;
|
||||||
|
|
||||||
|
/*! SDMMC command. */
|
||||||
|
typedef struct _sdmmc_cmd_t
|
||||||
|
{
|
||||||
|
u16 cmd;
|
||||||
|
u32 arg;
|
||||||
|
u32 rsp_type;
|
||||||
|
u32 check_busy;
|
||||||
|
} sdmmc_cmd_t;
|
||||||
|
|
||||||
|
/*! SDMMC request. */
|
||||||
|
typedef struct _sdmmc_req_t
|
||||||
|
{
|
||||||
|
void *buf;
|
||||||
|
u32 blksize;
|
||||||
|
u32 num_sectors;
|
||||||
|
int is_write;
|
||||||
|
int is_multi_block;
|
||||||
|
int is_auto_cmd12;
|
||||||
|
} sdmmc_req_t;
|
||||||
|
|
||||||
|
int sdmmc_get_voltage(sdmmc_t *sdmmc);
|
||||||
|
u32 sdmmc_get_bus_width(sdmmc_t *sdmmc);
|
||||||
|
void sdmmc_set_bus_width(sdmmc_t *sdmmc, u32 bus_width);
|
||||||
|
void sdmmc_get_venclkctl(sdmmc_t *sdmmc);
|
||||||
|
int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type);
|
||||||
|
void sdmmc_sd_clock_ctrl(sdmmc_t *sdmmc, int no_sd);
|
||||||
|
int sdmmc_get_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 size, u32 type);
|
||||||
|
int sdmmc_config_tuning(sdmmc_t *sdmmc, u32 type, u32 cmd);
|
||||||
|
int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp);
|
||||||
|
int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int no_sd);
|
||||||
|
void sdmmc_end(sdmmc_t *sdmmc);
|
||||||
|
void sdmmc_init_cmd(sdmmc_cmd_t *cmdbuf, u16 cmd, u32 arg, u32 rsp_type, u32 check_busy);
|
||||||
|
int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *blkcnt_out);
|
||||||
|
int sdmmc_enable_low_voltage(sdmmc_t *sdmmc);
|
||||||
|
|
||||||
|
#endif
|
132
source/storage/sdmmc_t210.h
Normal file
132
source/storage/sdmmc_t210.h
Normal file
@ -0,0 +1,132 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _SDMMC_T210_H_
|
||||||
|
#define _SDMMC_T210_H_
|
||||||
|
|
||||||
|
#include "../utils/types.h"
|
||||||
|
|
||||||
|
#define TEGRA_MMC_PWRCTL_SD_BUS_POWER 0x1
|
||||||
|
#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 0xA
|
||||||
|
#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 0xC
|
||||||
|
#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 0xE
|
||||||
|
#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_MASK 0xF1
|
||||||
|
|
||||||
|
#define TEGRA_MMC_HOSTCTL_1BIT 0x00
|
||||||
|
#define TEGRA_MMC_HOSTCTL_4BIT 0x02
|
||||||
|
#define TEGRA_MMC_HOSTCTL_8BIT 0x20
|
||||||
|
|
||||||
|
#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE 0x1
|
||||||
|
#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE 0x2
|
||||||
|
#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE 0x4
|
||||||
|
#define TEGRA_MMC_CLKCON_CLKGEN_SELECT 0x20
|
||||||
|
|
||||||
|
#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL 0x1
|
||||||
|
#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE 0x2
|
||||||
|
#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE 0x4
|
||||||
|
|
||||||
|
#define TEGRA_MMC_TRNMOD_DMA_ENABLE 0x1
|
||||||
|
#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE 0x2
|
||||||
|
#define TEGRA_MMC_TRNMOD_AUTO_CMD12 0x4
|
||||||
|
#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE 0x0
|
||||||
|
#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ 0x10
|
||||||
|
#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT 0x20
|
||||||
|
|
||||||
|
#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK 0x8
|
||||||
|
#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK 0x10
|
||||||
|
#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER 0x20
|
||||||
|
|
||||||
|
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK 0x3
|
||||||
|
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE 0x0
|
||||||
|
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 0x1
|
||||||
|
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 0x2
|
||||||
|
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY 0x3
|
||||||
|
|
||||||
|
#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE 0x1
|
||||||
|
#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE 0x2
|
||||||
|
#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT 0x8
|
||||||
|
#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT 0x8000
|
||||||
|
#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT 0x10000
|
||||||
|
|
||||||
|
#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY 0x20
|
||||||
|
|
||||||
|
typedef struct _t210_sdmmc_t
|
||||||
|
{
|
||||||
|
vu32 sysad;
|
||||||
|
vu16 blksize;
|
||||||
|
vu16 blkcnt;
|
||||||
|
vu32 argument;
|
||||||
|
vu16 trnmod;
|
||||||
|
vu16 cmdreg;
|
||||||
|
vu32 rspreg0;
|
||||||
|
vu32 rspreg1;
|
||||||
|
vu32 rspreg2;
|
||||||
|
vu32 rspreg3;
|
||||||
|
vu32 bdata;
|
||||||
|
vu32 prnsts;
|
||||||
|
vu8 hostctl;
|
||||||
|
vu8 pwrcon;
|
||||||
|
vu8 blkgap;
|
||||||
|
vu8 wakcon;
|
||||||
|
vu16 clkcon;
|
||||||
|
vu8 timeoutcon;
|
||||||
|
vu8 swrst;
|
||||||
|
vu16 norintsts;
|
||||||
|
vu16 errintsts;
|
||||||
|
vu16 norintstsen;
|
||||||
|
vu16 errintstsen;
|
||||||
|
vu16 norintsigen;
|
||||||
|
vu16 errintsigen;
|
||||||
|
vu16 acmd12errsts;
|
||||||
|
vu16 hostctl2;
|
||||||
|
vu32 capareg;
|
||||||
|
vu32 capareg_1;
|
||||||
|
vu32 maxcurr;
|
||||||
|
vu8 res3[4];
|
||||||
|
vu16 setacmd12err;
|
||||||
|
vu16 setinterr;
|
||||||
|
vu8 admaerr;
|
||||||
|
vu8 res4[3];
|
||||||
|
vu32 admaaddr;
|
||||||
|
vu32 admaaddr_hi;
|
||||||
|
vu8 res5[156];
|
||||||
|
vu16 slotintstatus;
|
||||||
|
vu16 hcver;
|
||||||
|
vu32 venclkctl;
|
||||||
|
vu32 venspictl;
|
||||||
|
vu32 venspiintsts;
|
||||||
|
vu32 venceatactl;
|
||||||
|
vu32 venbootctl;
|
||||||
|
vu32 venbootacktout;
|
||||||
|
vu32 venbootdattout;
|
||||||
|
vu32 vendebouncecnt;
|
||||||
|
vu32 venmiscctl;
|
||||||
|
vu32 res6[34];
|
||||||
|
vu32 field_1AC;
|
||||||
|
vu32 field_1B0;
|
||||||
|
vu8 res7[8];
|
||||||
|
vu32 field_1BC;
|
||||||
|
vu32 field_1C0;
|
||||||
|
vu32 field_1C4;
|
||||||
|
vu8 field_1C8[24];
|
||||||
|
vu32 sdmemcmppadctl;
|
||||||
|
vu32 autocalcfg;
|
||||||
|
vu32 autocalintval;
|
||||||
|
vu32 autocalsts;
|
||||||
|
vu32 field_1F0;
|
||||||
|
} t210_sdmmc_t;
|
||||||
|
|
||||||
|
#endif
|
35
source/utils/aarch64_util.h
Normal file
35
source/utils/aarch64_util.h
Normal file
@ -0,0 +1,35 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _ARM64_H_
|
||||||
|
#define _ARM64_H_
|
||||||
|
|
||||||
|
#include "types.h"
|
||||||
|
|
||||||
|
#define LSL0 0
|
||||||
|
#define LSL16 16
|
||||||
|
#define LSL32 32
|
||||||
|
|
||||||
|
#define _PAGEOFF(x) ((x) & 0xFFFFF000)
|
||||||
|
|
||||||
|
#define _ADRP(r, o) 0x90000000 | ((((o) >> 12) & 0x3) << 29) | ((((o) >> 12) & 0x1FFFFC) << 3) | ((r) & 0x1F)
|
||||||
|
#define _BL(a, o) 0x94000000 | ((((o) - (a)) >> 2) & 0x3FFFFFF)
|
||||||
|
#define _B(a, o) 0x14000000 | ((((o) - (a)) >> 2) & 0x3FFFFFF)
|
||||||
|
#define _MOVKX(r, i, s) 0xF2800000 | (((s) & 0x30) << 17) | (((i) & 0xFFFF) << 5) | ((r) & 0x1F)
|
||||||
|
#define _MOVZX(r, i, s) 0xD2800000 | (((s) & 0x30) << 17) | (((i) & 0xFFFF) << 5) | ((r) & 0x1F)
|
||||||
|
#define _NOP() 0xD503201F
|
||||||
|
|
||||||
|
#endif
|
74
source/utils/btn.c
Normal file
74
source/utils/btn.c
Normal file
@ -0,0 +1,74 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (C) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "btn.h"
|
||||||
|
#include "../soc/i2c.h"
|
||||||
|
#include "../soc/gpio.h"
|
||||||
|
#include "../soc/t210.h"
|
||||||
|
#include "util.h"
|
||||||
|
#include "../power/max77620.h"
|
||||||
|
|
||||||
|
u32 btn_read()
|
||||||
|
{
|
||||||
|
u32 res = 0;
|
||||||
|
if (!gpio_read(GPIO_PORT_X, GPIO_PIN_7))
|
||||||
|
res |= BTN_VOL_DOWN;
|
||||||
|
if (!gpio_read(GPIO_PORT_X, GPIO_PIN_6))
|
||||||
|
res |= BTN_VOL_UP;
|
||||||
|
if (i2c_recv_byte(4, MAX77620_I2C_ADDR, 0x15) & 0x4)
|
||||||
|
res |= BTN_POWER;
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 btn_wait()
|
||||||
|
{
|
||||||
|
u32 res = 0, btn = btn_read();
|
||||||
|
bool pwr = false;
|
||||||
|
|
||||||
|
//Power button down, raise a filter.
|
||||||
|
if (btn & BTN_POWER)
|
||||||
|
{
|
||||||
|
pwr = true;
|
||||||
|
btn &= ~BTN_POWER;
|
||||||
|
}
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
res = btn_read();
|
||||||
|
//Power button up, remove filter.
|
||||||
|
if (!(res & BTN_POWER) && pwr)
|
||||||
|
pwr = false;
|
||||||
|
else if (pwr) //Power button still down.
|
||||||
|
res &= ~BTN_POWER;
|
||||||
|
} while (btn == res);
|
||||||
|
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 btn_wait_timeout(u32 time_ms, u32 mask)
|
||||||
|
{
|
||||||
|
u32 timeout = get_tmr_ms() + time_ms;
|
||||||
|
u32 res = btn_read() & mask;
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
if (!(res & mask))
|
||||||
|
res = btn_read() & mask;
|
||||||
|
} while (get_tmr_ms() < timeout);
|
||||||
|
|
||||||
|
return res;
|
||||||
|
}
|
31
source/utils/btn.h
Normal file
31
source/utils/btn.h
Normal file
@ -0,0 +1,31 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (C) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _BTN_H_
|
||||||
|
#define _BTN_H_
|
||||||
|
|
||||||
|
#include "types.h"
|
||||||
|
|
||||||
|
#define BTN_POWER 0x1
|
||||||
|
#define BTN_VOL_DOWN 0x2
|
||||||
|
#define BTN_VOL_UP 0x4
|
||||||
|
|
||||||
|
u32 btn_read();
|
||||||
|
u32 btn_wait();
|
||||||
|
u32 btn_wait_timeout(u32 time_ms, u32 mask);
|
||||||
|
|
||||||
|
#endif
|
95
source/utils/list.h
Normal file
95
source/utils/list.h
Normal file
@ -0,0 +1,95 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _LIST_H_
|
||||||
|
#define _LIST_H_
|
||||||
|
|
||||||
|
#include "types.h"
|
||||||
|
|
||||||
|
/*! Initialize list. */
|
||||||
|
#define LIST_INIT(name) link_t name = {&name, &name}
|
||||||
|
|
||||||
|
/*! Initialize static list. */
|
||||||
|
#define LIST_INIT_STATIC(name) static link_t name = {&name, &name}
|
||||||
|
|
||||||
|
/*! Iterate over all list links. */
|
||||||
|
#define LIST_FOREACH(iter, list) \
|
||||||
|
for(link_t *iter = (list)->next; iter != (list); iter = iter->next)
|
||||||
|
|
||||||
|
/*! Safely iterate over all list links. */
|
||||||
|
#define LIST_FOREACH_SAFE(iter, list) \
|
||||||
|
for(link_t *iter = (list)->next, *safe = iter->next; iter != (list); iter = safe, safe = iter->next)
|
||||||
|
|
||||||
|
/*! Iterate over all list members. */
|
||||||
|
#define LIST_FOREACH_ENTRY(etype, iter, list, mn) \
|
||||||
|
for(etype *iter = CONTAINER_OF((list)->next, etype, mn); &iter->mn != (list); iter = CONTAINER_OF(iter->mn.next, etype, mn))
|
||||||
|
|
||||||
|
typedef struct _link_t
|
||||||
|
{
|
||||||
|
struct _link_t *prev;
|
||||||
|
struct _link_t *next;
|
||||||
|
} link_t;
|
||||||
|
|
||||||
|
static inline void link_init(link_t *l)
|
||||||
|
{
|
||||||
|
l->prev = NULL;
|
||||||
|
l->next = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int link_used(link_t *l)
|
||||||
|
{
|
||||||
|
if(l->next == NULL)
|
||||||
|
return 1;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void list_init(link_t *lh)
|
||||||
|
{
|
||||||
|
lh->prev = lh;
|
||||||
|
lh->next = lh;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void list_prepend(link_t *lh, link_t *l)
|
||||||
|
{
|
||||||
|
l->next = lh->next;
|
||||||
|
l->prev = lh;
|
||||||
|
lh->next->prev = l;
|
||||||
|
lh->next = l;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void list_append(link_t *lh, link_t *l)
|
||||||
|
{
|
||||||
|
l->prev = lh->prev;
|
||||||
|
l->next = lh;
|
||||||
|
lh->prev->next = l;
|
||||||
|
lh->prev = l;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void list_remove(link_t *l)
|
||||||
|
{
|
||||||
|
l->next->prev = l->prev;
|
||||||
|
l->prev->next = l->next;
|
||||||
|
link_init(l);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int list_empty(link_t *lh)
|
||||||
|
{
|
||||||
|
if(lh->next == lh)
|
||||||
|
return 1;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
86
source/utils/types.h
Normal file
86
source/utils/types.h
Normal file
@ -0,0 +1,86 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _TYPES_H_
|
||||||
|
#define _TYPES_H_
|
||||||
|
|
||||||
|
#define NULL ((void *)0)
|
||||||
|
|
||||||
|
#define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))
|
||||||
|
#define MAX(a, b) ((a) > (b) ? (a) : (b))
|
||||||
|
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||||
|
|
||||||
|
#define OFFSET_OF(t, m) ((u32)&((t *)NULL)->m)
|
||||||
|
#define CONTAINER_OF(mp, t, mn) ((t *)((u32)mp - OFFSET_OF(t, mn)))
|
||||||
|
|
||||||
|
#define KB_FIRMWARE_VERSION_100_200 0
|
||||||
|
#define KB_FIRMWARE_VERSION_300 1
|
||||||
|
#define KB_FIRMWARE_VERSION_301 2
|
||||||
|
#define KB_FIRMWARE_VERSION_400 3
|
||||||
|
#define KB_FIRMWARE_VERSION_500 4
|
||||||
|
#define KB_FIRMWARE_VERSION_600 5
|
||||||
|
#define KB_FIRMWARE_VERSION_620 6
|
||||||
|
#define KB_FIRMWARE_VERSION_700 7
|
||||||
|
#define KB_FIRMWARE_VERSION_MAX KB_FIRMWARE_VERSION_700
|
||||||
|
|
||||||
|
#define HOS_PKG11_MAGIC 0x31314B50
|
||||||
|
|
||||||
|
#define COLOR_RED 0xFFE70000
|
||||||
|
#define COLOR_ORANGE 0xFFFF8C00
|
||||||
|
#define COLOR_YELLOW 0xFFFFFF40
|
||||||
|
#define COLOR_GREEN 0xFF40FF00
|
||||||
|
#define COLOR_BLUE 0xFF00DDFF
|
||||||
|
#define COLOR_VIOLET 0xFF8040FF
|
||||||
|
|
||||||
|
typedef char s8;
|
||||||
|
typedef short s16;
|
||||||
|
typedef short SHORT;
|
||||||
|
typedef int s32;
|
||||||
|
typedef int INT;
|
||||||
|
typedef long LONG;
|
||||||
|
typedef long long int s64;
|
||||||
|
typedef unsigned char u8;
|
||||||
|
typedef unsigned char BYTE;
|
||||||
|
typedef unsigned short u16;
|
||||||
|
typedef unsigned short WORD;
|
||||||
|
typedef unsigned short WCHAR;
|
||||||
|
typedef unsigned int u32;
|
||||||
|
typedef unsigned int UINT;
|
||||||
|
typedef unsigned long DWORD;
|
||||||
|
typedef unsigned long long QWORD;
|
||||||
|
typedef unsigned long long int u64;
|
||||||
|
typedef volatile unsigned char vu8;
|
||||||
|
typedef volatile unsigned short vu16;
|
||||||
|
typedef volatile unsigned int vu32;
|
||||||
|
|
||||||
|
typedef int bool;
|
||||||
|
#define true 1
|
||||||
|
#define false 0
|
||||||
|
|
||||||
|
#define BOOT_CFG_AUTOBOOT_EN (1 << 0)
|
||||||
|
#define BOOT_CFG_FROM_LAUNCH (1 << 1)
|
||||||
|
#define BOOT_CFG_SEPT_RUN (1 << 7)
|
||||||
|
|
||||||
|
typedef struct __attribute__((__packed__)) _boot_cfg_t
|
||||||
|
{
|
||||||
|
u8 boot_cfg;
|
||||||
|
u8 autoboot;
|
||||||
|
u8 autoboot_list;
|
||||||
|
u8 rsvd_cfg;
|
||||||
|
u8 rsvd[32];
|
||||||
|
} boot_cfg_t;
|
||||||
|
|
||||||
|
#endif
|
99
source/utils/util.c
Normal file
99
source/utils/util.c
Normal file
@ -0,0 +1,99 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (C) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "util.h"
|
||||||
|
#include "../soc/t210.h"
|
||||||
|
|
||||||
|
u32 get_tmr_s()
|
||||||
|
{
|
||||||
|
return RTC(APBDEV_RTC_SECONDS);
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 get_tmr_ms()
|
||||||
|
{
|
||||||
|
// The registers must be read with the following order:
|
||||||
|
// -> RTC_MILLI_SECONDS (0x10) -> RTC_SHADOW_SECONDS (0xC)
|
||||||
|
return (RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS) << 10));
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 get_tmr_us()
|
||||||
|
{
|
||||||
|
return TMR(TIMERUS_CNTR_1US); //TIMERUS_CNTR_1US
|
||||||
|
}
|
||||||
|
|
||||||
|
void msleep(u32 milliseconds)
|
||||||
|
{
|
||||||
|
u32 start = RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS) << 10);
|
||||||
|
while (((RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS) << 10)) - start) <= milliseconds)
|
||||||
|
;
|
||||||
|
}
|
||||||
|
|
||||||
|
void usleep(u32 microseconds)
|
||||||
|
{
|
||||||
|
u32 start = TMR(TIMERUS_CNTR_1US);
|
||||||
|
// Casting to u32 is important!
|
||||||
|
while ((u32)(TMR(TIMERUS_CNTR_1US) - start) <= microseconds)
|
||||||
|
;
|
||||||
|
}
|
||||||
|
|
||||||
|
void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops)
|
||||||
|
{
|
||||||
|
for(u32 i = 0; i < num_ops; i++)
|
||||||
|
base[ops[i].off] = ops[i].val;
|
||||||
|
}
|
||||||
|
|
||||||
|
#define CRC32C_POLY 0x82F63B78
|
||||||
|
u32 crc32c(const void *buf, u32 len)
|
||||||
|
{
|
||||||
|
const u8 *cbuf = (const u8 *)buf;
|
||||||
|
u32 crc = 0xFFFFFFFF;
|
||||||
|
while (len--)
|
||||||
|
{
|
||||||
|
crc ^= *cbuf++;
|
||||||
|
for (int i = 0; i < 8; i++)
|
||||||
|
crc = crc & 1 ? (crc >> 1) ^ CRC32C_POLY : crc >> 1;
|
||||||
|
}
|
||||||
|
return ~crc;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 memcmp32sparse(const u32 *buf1, const u32 *buf2, u32 len)
|
||||||
|
{
|
||||||
|
u32 len32 = len / 4;
|
||||||
|
|
||||||
|
if (!(len32 % 32))
|
||||||
|
{
|
||||||
|
while (len32)
|
||||||
|
{
|
||||||
|
len32 -= 32;
|
||||||
|
if(buf1[len32] != buf2[len32])
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
while (len32)
|
||||||
|
{
|
||||||
|
len32 -= 32;
|
||||||
|
if(buf1[len32] != buf2[len32])
|
||||||
|
return 1;
|
||||||
|
if (len32 < 32)
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
44
source/utils/util.h
Normal file
44
source/utils/util.h
Normal file
@ -0,0 +1,44 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 naehrwert
|
||||||
|
* Copyright (C) 2018 CTCaer
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _UTIL_H_
|
||||||
|
#define _UTIL_H_
|
||||||
|
|
||||||
|
#include "types.h"
|
||||||
|
|
||||||
|
#define byte_swap_32(num) ((num >> 24) & 0xff) | ((num << 8) & 0xff0000) | \
|
||||||
|
((num >> 8 )& 0xff00) | ((num << 24) & 0xff000000)
|
||||||
|
|
||||||
|
typedef struct _cfg_op_t
|
||||||
|
{
|
||||||
|
u32 off;
|
||||||
|
u32 val;
|
||||||
|
} cfg_op_t;
|
||||||
|
|
||||||
|
u32 get_tmr_us();
|
||||||
|
u32 get_tmr_ms();
|
||||||
|
u32 get_tmr_s();
|
||||||
|
void usleep(u32 ticks);
|
||||||
|
void msleep(u32 milliseconds);
|
||||||
|
void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops);
|
||||||
|
u32 crc32c(const void *buf, u32 len);
|
||||||
|
|
||||||
|
/* This is a faster implementation of memcmp that checks two u32 values */
|
||||||
|
/* every 128 Bytes block. Intented only for Backup and Restore */
|
||||||
|
u32 memcmp32sparse(const u32 *buf1, const u32 *buf2, u32 len);
|
||||||
|
|
||||||
|
#endif
|
Loading…
Reference in New Issue
Block a user