mirror of
https://github.com/shchmue/Lockpick_RCM.git
synced 2024-06-29 13:06:01 +02:00
346 lines
13 KiB
C
346 lines
13 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include "hw_init.h"
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#include "bpmp.h"
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#include "clock.h"
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#include "fuse.h"
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#include "gpio.h"
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#include "i2c.h"
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#include "pinmux.h"
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#include "pmc.h"
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#include "t210.h"
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#include "../gfx/di.h"
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#include "../mem/mc.h"
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#include "../mem/minerva.h"
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#include "../mem/sdram.h"
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#include "../power/max77620.h"
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#include "../power/max7762x.h"
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#include "../sec/se.h"
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#include "../sec/se_t210.h"
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#include "../storage/sdmmc.h"
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#include "../utils/util.h"
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extern sdmmc_t sd_sdmmc;
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extern boot_cfg_t b_cfg;
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/*
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* CLK_OSC - 38.4 MHz crystal.
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* CLK_M - 19.2 MHz (osc/2).
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* CLK_S - 32.768 KHz (from PMIC).
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* SCLK - 204MHz init (-> 408MHz -> OC).
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* HCLK - 204MHz init (-> 408MHz -> OC).
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* PCLK - 68MHz init (-> 136MHz -> OC/4).
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*/
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void _config_oscillators()
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{
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CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; // Set CLK_M_DIVISOR to 2.
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SYSCTR0(SYSCTR0_CNTFID0) = 19200000; // Set counter frequency.
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TMR(TIMERUS_USEC_CFG) = 0x45F; // For 19.2MHz clk_m.
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CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x50000071; // Set OSC to 38.4MHz and drive strength.
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PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81) | 0xE; // Set LP0 OSC drive strength.
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PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF) | PMC_OSC_EDPD_OVER_OSC_CTRL_OVER;
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PMC(APBDEV_PMC_CNTRL2) = (PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF) | PMC_CNTRL2_HOLD_CKE_LOW_EN;
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PMC(APBDEV_PMC_SCRATCH188) = (PMC(APBDEV_PMC_SCRATCH188) & 0xFCFFFFFF) | (4 << 23); // LP0 EMC2TMC_CFG_XM2COMP_PU_VREF_SEL_RANGE.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10; // Set HCLK div to 2 and PCLK div to 1.
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CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) &= 0xBFFFFFFF; // PLLMB disable.
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PMC(APBDEV_PMC_TSC_MULT) = (PMC(APBDEV_PMC_TSC_MULT) & 0xFFFF0000) | 0x249F; //0x249F = 19200000 * (16 / 32.768 kHz)
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0; // Set SCLK div to 1.
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; // Set clk source to Run and PLLP_OUT2 (204MHz).
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CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; // Enable SUPER_SDIV to 1.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3.
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}
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void _config_gpios()
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{
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PINMUX_AUX(PINMUX_AUX_UART2_TX) = 0;
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PINMUX_AUX(PINMUX_AUX_UART3_TX) = 0;
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// Set Joy-Con IsAttached direction.
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PINMUX_AUX(PINMUX_AUX_GPIO_PE6) = PINMUX_INPUT_ENABLE;
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PINMUX_AUX(PINMUX_AUX_GPIO_PH6) = PINMUX_INPUT_ENABLE;
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// Set pin mode for Joy-Con IsAttached and UARTB/C TX pins.
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#if !defined (DEBUG_UART_PORT) || DEBUG_UART_PORT != UART_B
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gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO);
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#endif
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#if !defined (DEBUG_UART_PORT) || DEBUG_UART_PORT != UART_C
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gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO);
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#endif
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// Set Joy-Con IsAttached mode.
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gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_GPIO);
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gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_GPIO);
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// Enable input logic for Joy-Con IsAttached and UARTB/C TX pins.
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gpio_output_enable(GPIO_PORT_G, GPIO_PIN_0, GPIO_OUTPUT_DISABLE);
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gpio_output_enable(GPIO_PORT_D, GPIO_PIN_1, GPIO_OUTPUT_DISABLE);
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gpio_output_enable(GPIO_PORT_E, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
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gpio_output_enable(GPIO_PORT_H, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
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pinmux_config_i2c(I2C_1);
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pinmux_config_i2c(I2C_5);
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pinmux_config_uart(0);
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// Configure volume up/down as inputs.
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gpio_config(GPIO_PORT_X, GPIO_PIN_6, GPIO_MODE_GPIO);
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gpio_config(GPIO_PORT_X, GPIO_PIN_7, GPIO_MODE_GPIO);
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gpio_output_enable(GPIO_PORT_X, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
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gpio_output_enable(GPIO_PORT_X, GPIO_PIN_7, GPIO_OUTPUT_DISABLE);
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// Configure HOME as inputs.
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// PINMUX_AUX(PINMUX_AUX_BUTTON_HOME) = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE;
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// gpio_config(GPIO_PORT_Y, GPIO_PIN_1, GPIO_MODE_GPIO);
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}
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void _config_pmc_scratch()
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{
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PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF; // Unset Debug console from Customer Option.
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PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; // Unset DATA_DQ_E_IVREF EMC_PMACRO_DATA_PAD_TX_CTRL
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PMC(APBDEV_PMC_SECURE_SCRATCH21) |= PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT;
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}
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void _mbist_workaround()
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{
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= (1 << 6); // Enable APE clock.
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// Set mux output to SOR1 clock switch.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) | 0x8000) & 0xFFFFBFFF;
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// Enabled PLLD and set csi to PLLD for test pattern generation.
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CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) |= 0x40800000;
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// Clear per-clock resets.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_CLR) = 0x40; // Clear reset APE.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_CLR) = 0x40000; // Clear reset VIC.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000; // Clear reset DISP1, HOST1X.
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usleep(2);
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// I2S channels to master and disable SLCG.
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I2S(I2S1_CTRL) |= I2S_CTRL_MASTER_EN;
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I2S(I2S1_CG) &= ~I2S_CG_SLCG_ENABLE;
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I2S(I2S2_CTRL) |= I2S_CTRL_MASTER_EN;
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I2S(I2S2_CG) &= ~I2S_CG_SLCG_ENABLE;
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I2S(I2S3_CTRL) |= I2S_CTRL_MASTER_EN;
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I2S(I2S3_CG) &= ~I2S_CG_SLCG_ENABLE;
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I2S(I2S4_CTRL) |= I2S_CTRL_MASTER_EN;
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I2S(I2S4_CG) &= ~I2S_CG_SLCG_ENABLE;
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I2S(I2S5_CTRL) |= I2S_CTRL_MASTER_EN;
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I2S(I2S5_CG) &= ~I2S_CG_SLCG_ENABLE;
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DISPLAY_A(_DIREG(DC_COM_DSC_TOP_CTL)) |= 4; // DSC_SLCG_OVERRIDE.
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VIC(0x8C) = 0xFFFFFFFF;
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usleep(2);
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// Set per-clock reset.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_SET) = 0x40; // Set reset APE.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000; // Set reset DISP1, HOST1x.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_SET) = 0x40000; // Set reset VIC.
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// Enable specific clocks and disable all others.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = 0xC0; // Enable clock PMC, FUSE.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) = 0x80000130; // Enable clock RTC, TMR, GPIO, BPMP_CACHE.
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//CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) = 0x80400130; // Keep USB data ON.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) = 0x1F00200; // Enable clock CSITE, IRAMA, IRAMB, IRAMC, IRAMD, BPMP_CACHE_RAM.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = 0x80400808; // Enable clock MSELECT, APB2APE, SPDIF_DOUBLER, SE.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_W) = 0x402000FC; // Enable clock PCIERX0, PCIERX1, PCIERX2, PCIERX3, PCIERX4, PCIERX5, ENTROPY, MC1.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X) = 0x23000780; // Enable clock MC_CAPA, MC_CAPB, MC_CPU, MC_BBC, DBGAPB, HPLL_ADSP, PLLG_REF.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) = 0x300; // Enable clock MC_CDPA, MC_CCPA.
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// Disable clock gate overrides.
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA) = 0;
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB) = 0;
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC) = 0;
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) = 0;
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE) = 0;
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// Set child clock sources.
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CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) &= 0x1F7FFFFF; // Disable PLLD and set reference clock and csi clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) &= 0xFFFF3FFF; // Set SOR1 to automatic muxing of safe clock (24MHz) or SOR1 clk switch.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT.
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}
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void _config_se_brom()
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{
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// Skip SBK/SSK if sept was run.
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if (!(b_cfg.boot_cfg & BOOT_CFG_SEPT_RUN))
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{
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// Bootrom part we skipped.
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u32 sbk[4] = {
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FUSE(FUSE_PRIVATE_KEY0),
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FUSE(FUSE_PRIVATE_KEY1),
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FUSE(FUSE_PRIVATE_KEY2),
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FUSE(FUSE_PRIVATE_KEY3)
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};
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// Set SBK to slot 14.
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se_aes_key_set(14, sbk, 0x10);
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// Lock SBK from being read.
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SE(SE_KEY_TABLE_ACCESS_REG_OFFSET + 14 * 4) = 0x7E;
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// Lock SSK (although it's not set and unused anyways).
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SE(SE_KEY_TABLE_ACCESS_REG_OFFSET + 15 * 4) = 0x7E;
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}
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// This memset needs to happen here, else TZRAM will behave weirdly later on.
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memset((void *)TZRAM_BASE, 0, 0x10000);
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PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_ENABLE;
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SE(SE_INT_STATUS_REG_OFFSET) = 0x1F;
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// Clear the boot reason to avoid problems later
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PMC(APBDEV_PMC_SCRATCH200) = 0x0;
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PMC(APBDEV_PMC_RST_STATUS) = 0x0;
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APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = (APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) & 0xF0) | (7 << 10);
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}
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void _config_regulators()
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{
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CNFGBBC, MAX77620_CNFGBBC_RESISTOR_1K);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1,
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(1 << 6) | (1 << MAX77620_ONOFFCNFG1_MRT_SHIFT)); // PWR delay for forced shutdown off.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG0,
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(7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG1,
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(7 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (1 << MAX77620_FPS_EN_SRC_SHIFT));
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG2,
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(7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
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max77620_regulator_config_fps(REGULATOR_LDO4);
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max77620_regulator_config_fps(REGULATOR_LDO8);
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max77620_regulator_config_fps(REGULATOR_SD0);
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max77620_regulator_config_fps(REGULATOR_SD1);
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max77620_regulator_config_fps(REGULATOR_SD3);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_GPIO3,
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(4 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (2 << MAX77620_FPS_PD_PERIOD_SHIFT)); // 3.x+
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// Set vdd_core voltage to 1.125V
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max77620_regulator_set_voltage(REGULATOR_SD0, 1125000);
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// Fix CPU/GPU after a Linux warmboot.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, 2);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO6, 2);
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_0_95V); // Disable power.
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVC_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_1_09V); // Enable DVS power.
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG, MAX77621_RAMP_50mV_PER_US);
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i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG,
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MAX77621_T_JUNCTION_120 | MAX77621_FT_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS |
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MAX77621_CKKADV_TRIP_150mV_PER_US | MAX77621_INDUCTOR_NOMINAL);
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_0_95V); // Disable power.
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_VOUT_DVC_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_1_09V); // Enable DVS power.
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_CONTROL1_REG, MAX77621_RAMP_50mV_PER_US);
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i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_CONTROL2_REG,
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MAX77621_T_JUNCTION_120 | MAX77621_FT_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS |
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MAX77621_CKKADV_TRIP_150mV_PER_US | MAX77621_INDUCTOR_NOMINAL);
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// Disable low battery shutdown monitor.
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max77620_low_battery_monitor_config();
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}
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void config_hw()
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{
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// Bootrom stuff we skipped by going through rcm.
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_config_se_brom();
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//FUSE(FUSE_PRIVATEKEYDISABLE) = 0x11;
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SYSREG(AHB_AHB_SPARE_REG) &= 0xFFFFFF9F; // Unset APB2JTAG_OVERRIDE_EN and OBS_OVERRIDE_EN.
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PMC(APBDEV_PMC_SCRATCH49) = PMC(APBDEV_PMC_SCRATCH49) & 0xFFFFFFFC;
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_mbist_workaround();
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clock_enable_se();
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// Enable fuse clock.
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clock_enable_fuse(true);
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// Disable fuse programming.
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fuse_disable_program();
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mc_enable();
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_config_oscillators();
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APB_MISC(APB_MISC_PP_PINMUX_GLOBAL) = 0;
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_config_gpios();
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clock_enable_cl_dvfs();
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clock_enable_i2c(I2C_1);
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clock_enable_i2c(I2C_5);
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clock_enable_tzram();
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i2c_init(I2C_1);
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i2c_init(I2C_5);
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_config_regulators();
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_config_pmc_scratch(); // Missing from 4.x+
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // Set SCLK to PLLP_OUT (408MHz).
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sdram_init();
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bpmp_mmu_enable();
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mc_enable_ahb_redirect();
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}
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void reconfig_hw_workaround(bool extra_reconfig, u32 magic)
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{
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// Flush and disable MMU.
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bpmp_mmu_disable();
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bpmp_clk_rate_set(BPMP_CLK_NORMAL);
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minerva_change_freq(FREQ_204);
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// Re-enable clocks to Audio Processing Engine as a workaround to hanging.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= (1 << 6); // Enable APE clock.
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if (extra_reconfig)
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{
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msleep(10);
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PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_SDMMC1_IO_EN;
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clock_disable_cl_dvfs();
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// Disable Joy-con GPIOs.
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gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO);
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gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO);
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gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_SPIO);
|
|
gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_SPIO);
|
|
}
|
|
|
|
// Power off display.
|
|
display_end();
|
|
|
|
// Enable clock to USBD and init SDMMC1 to avoid hangs with bad hw inits.
|
|
if (magic == 0xBAADF00D)
|
|
{
|
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) |= (1 << 22);
|
|
sdmmc_init(&sd_sdmmc, SDMMC_1, SDMMC_POWER_3_3, SDMMC_BUS_WIDTH_1, 5, 0);
|
|
clock_disable_cl_dvfs();
|
|
|
|
msleep(200);
|
|
}
|
|
}
|