mirror of
https://github.com/shchmue/Lockpick_RCM.git
synced 2024-06-01 11:28:46 +02:00
96 lines
3.1 KiB
C
96 lines
3.1 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _SDRAM_H_
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#define _SDRAM_H_
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#include <mem/emc.h>
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/*
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* Tegra X1/X1+ EMC/DRAM Bandwidth Chart:
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*
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* 40.8 MHz: 0.61 GiB/s
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* 68.0 MHz: 1.01 GiB/s
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* 102.0 MHz: 1.52 GiB/s
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* 204.0 MHz: 3.04 GiB/s <-- Tegra X1/X1+ Init/SC7 Frequency
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* 408.0 MHz: 6.08 GiB/s
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* 665.6 MHz: 9.92 GiB/s
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* 800.0 MHz: 11.92 GiB/s <-- Tegra X1/X1+ Nvidia OS Boot Frequency
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* 1065.6 MHz: 15.89 GiB/s
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* 1331.2 MHz: 19.84 GiB/s
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* 1600.0 MHz: 23.84 GiB/s <-- Tegra X1 Official Max Frequency
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* 1862.4 MHz: 27.75 GiB/s <-- Tegra X1+ Official Max Frequency
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* 2131.2 MHz: 31.76 GiB/s
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*
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* Note: BWbits = Hz x bus width x channels = Hz x 64 x 2.
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*/
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enum sdram_ids_erista
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{
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// LPDDR4 3200Mbps.
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LPDDR4_ICOSA_4GB_SAMSUNG_K4F6E304HB_MGCH = 0,
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LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE = 1,
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LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WT = 2,
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LPDDR4_COPPER_4GB_SAMSUNG_K4F6E304HB_MGCH = 3, // Changed to AULA Hynix 4GB 1Y-A.
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LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH = 4,
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LPDDR4_COPPER_4GB_HYNIX_H9HCNNNBPUMLHR_NLE = 5,
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LPDDR4_COPPER_4GB_MICRON_MT53B512M32D2NP_062_WT = 6,
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};
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enum sdram_ids_mariko
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{
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// LPDDR4X 3733Mbps.
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LPDDR4X_IOWA_4GB_SAMSUNG_X1X2 = 7,
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LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AM_MGCJ = 8,
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LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 9,
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LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLHR_NME = 10,
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LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WT = 11, // 4266Mbps.
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LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AM_MGCJ = 12,
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LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 13,
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LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLHR_NME = 14,
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LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WT = 15, // 4266Mbps.
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// LPDDR4X 4266Mbps?
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LPDDR4X_IOWA_4GB_SAMSUNG_Y = 16,
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LPDDR4X_IOWA_4GB_SAMSUNG_1Y_X = 17,
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LPDDR4X_IOWA_8GB_SAMSUNG_1Y_X = 18,
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LPDDR4X_HOAG_4GB_SAMSUNG_1Y_X = 19,
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LPDDR4X_IOWA_4GB_SAMSUNG_1Y_Y = 20,
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LPDDR4X_IOWA_8GB_SAMSUNG_1Y_Y = 21,
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LPDDR4X_AULA_4GB_SAMSUNG_1Y_A = 22,
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LPDDR4X_AULA_8GB_SAMSUNG_1Y_X = 23,
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LPDDR4X_AULA_4GB_SAMSUNG_1Y_X = 24,
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LPDDR4X_IOWA_4GB_MICRON_1Y_A = 25,
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LPDDR4X_HOAG_4GB_MICRON_1Y_A = 26,
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LPDDR4X_AULA_4GB_MICRON_1Y_A = 27
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};
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void sdram_init();
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void *sdram_get_params_patched();
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void *sdram_get_params_t210b01();
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void sdram_lp0_save_params(const void *params);
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emc_mr_data_t sdram_read_mrx(emc_mr_t mrx);
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#endif
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