From e4661f035b7e8bac3ae126767d510a3900858586 Mon Sep 17 00:00:00 2001 From: shchmue Date: Tue, 30 Nov 2021 11:39:35 -0700 Subject: [PATCH] Update to hekate bdk 5.6.5 --- bdk/display/di.c | 20 +++-- bdk/display/di.h | 7 +- bdk/input/touch.c | 2 +- bdk/libs/fatfs/ff.c | 11 +-- bdk/mem/minerva.h | 4 +- bdk/mem/sdram.c | 10 +-- bdk/mem/sdram.h | 34 ++++---- bdk/mem/sdram_config_t210b01.inl | 41 ++++----- bdk/mem/smmu.c | 8 +- bdk/memory_map.h | 18 ++-- bdk/power/regulator_5v.c | 68 +++++++++++---- bdk/sec/tsec.c | 10 +-- bdk/soc/hw_init.c | 27 +++--- bdk/soc/hw_init.h | 5 +- bdk/soc/pmc.h | 7 ++ bdk/thermal/fan.c | 19 ++-- bdk/usb/usb_gadget_ums.c | 3 +- bdk/utils/types.h | 145 +++++++++++++++++++++---------- bdk/utils/util.c | 2 +- bdk/utils/util.h | 20 ++--- source/storage/emummc.c | 13 ++- source/storage/emummc.h | 2 +- 22 files changed, 299 insertions(+), 177 deletions(-) diff --git a/bdk/display/di.c b/bdk/display/di.c index ee4b45d..9396e99 100644 --- a/bdk/display/di.c +++ b/bdk/display/di.c @@ -436,12 +436,12 @@ void display_init() // For Aula ensure that we have a compatible panel id. if (nx_aula && _display_id == 0xCCCC) - _display_id = PANEL_SAM_70_UNK; + _display_id = PANEL_SAM_AMS699VC01; // Initialize display panel. switch (_display_id) { - case PANEL_SAM_70_UNK: + case PANEL_SAM_AMS699VC01: _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000); _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xA0, 0); // Write 0 to 0xA0. _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, MIPI_DCS_SET_CONTROL_DISPLAY | (DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL << 8), 0); // Enable brightness control. @@ -539,7 +539,7 @@ void display_init() void display_backlight_pwm_init() { - if (_display_id == PANEL_SAM_70_UNK) + if (_display_id == PANEL_SAM_AMS699VC01) return; clock_enable_pwm(); @@ -557,6 +557,10 @@ void display_backlight(bool enable) void display_dsi_backlight_brightness(u32 brightness) { + // Normalize brightness value by 82% and a base of 45 duty. + if (brightness) + brightness = (brightness * PANEL_OLED_BL_COEFF / 100) + PANEL_OLED_BL_OFFSET; + u16 bl_ctrl = byte_swap_16((u16)(brightness * 8)); display_dsi_vblank_write(MIPI_DCS_SET_BRIGHTNESS, 2, &bl_ctrl); } @@ -592,7 +596,7 @@ void display_backlight_brightness(u32 brightness, u32 step_delay) if (brightness > 255) brightness = 255; - if (_display_id != PANEL_SAM_70_UNK) + if (_display_id != PANEL_SAM_AMS699VC01) display_pwm_backlight_brightness(brightness, step_delay); else display_dsi_backlight_brightness(brightness); @@ -624,7 +628,7 @@ static void _display_panel_and_hw_end(bool no_panel_deinit) exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_disable_config, 17); exec_cfg((u32 *)DSI_BASE, _display_dsi_timing_deinit_config, 16); - if (_display_id != PANEL_SAM_70_UNK) + if (_display_id != PANEL_SAM_AMS699VC01) usleep(10000); // De-initialize display panel. @@ -678,7 +682,7 @@ static void _display_panel_and_hw_end(bool no_panel_deinit) // Blank - powerdown. _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_ENTER_SLEEP_MODE, - (_display_id == PANEL_SAM_70_UNK) ? 120000 : 50000); + (_display_id == PANEL_SAM_AMS699VC01) ? 120000 : 50000); skip_panel_deinit: // Disable LCD power pins. @@ -734,7 +738,7 @@ void display_set_decoded_panel_id(u32 id) // For Aula ensure that we have a compatible panel id. if (nx_aula && _display_id == 0xCCCC) - _display_id = PANEL_SAM_70_UNK; + _display_id = PANEL_SAM_AMS699VC01; } void display_color_screen(u32 color) @@ -749,7 +753,7 @@ void display_color_screen(u32 color) DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = (DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE) | GENERAL_ACT_REQ; usleep(35000); // No need to wait on Aula. - if (_display_id != PANEL_SAM_70_UNK) + if (_display_id != PANEL_SAM_AMS699VC01) display_backlight(true); else display_backlight_brightness(255, 0); diff --git a/bdk/display/di.h b/bdk/display/di.h index 9229a22..1e0f991 100644 --- a/bdk/display/di.h +++ b/bdk/display/di.h @@ -652,6 +652,9 @@ #define DCS_CONTROL_DISPLAY_DIMMING_CTRL BIT(3) #define DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL BIT(5) +#define PANEL_OLED_BL_COEFF 82 // 82%. +#define PANEL_OLED_BL_OFFSET 45 // Least legible backlight duty. + /* Switch Panels: * * 6.2" panels for Icosa and Iowa skus: @@ -671,7 +674,7 @@ * [40] XX [10]: Vendor 40 [UNCONFIRMED ID] * * 7.0" OLED panels for Aula skus: - * [50] XX [20]: Samsung AMS700XXXX [UNCONFIRMED ID and MODEL] + * [50] 9B [20]: Samsung AMS699VC01-0 (Rev 2.5) */ /* Display ID Decoding: @@ -703,7 +706,7 @@ enum PANEL_INL_2J055IA_27A = 0x1020, PANEL_AUO_A055TAN01 = 0x1030, PANEL_V40_55_UNK = 0x1040, - PANEL_SAM_70_UNK = 0x2050 + PANEL_SAM_AMS699VC01 = 0x2050 }; void display_init(); diff --git a/bdk/input/touch.c b/bdk/input/touch.c index 2aba0e4..4c49837 100644 --- a/bdk/input/touch.c +++ b/bdk/input/touch.c @@ -39,7 +39,7 @@ static touch_panel_info_t _panels[] = { 1, 0, 1, 1, "GiS GGM6 B2X" }, { 2, 0, 0, 0, "NISSHA NBF-K9A" }, { 3, 1, 0, 0, "GiS 5.5\"" }, - { 4, 0, 0, 1, "Unknown_001" }, + { 4, 0, 0, 1, "Samsung BH2109" }, { -1, 1, 0, 1, "GiS VA 6.2\"" } }; diff --git a/bdk/libs/fatfs/ff.c b/bdk/libs/fatfs/ff.c index 75e0271..08e800f 100644 --- a/bdk/libs/fatfs/ff.c +++ b/bdk/libs/fatfs/ff.c @@ -3274,7 +3274,6 @@ static FRESULT find_volume ( /* FR_OK(0): successful, !=0: an error occurred */ stat = disk_status(fs->pdrv); if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */ if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check write protection if needed */ - EFSPRINTF("WPEN1"); return FR_WRITE_PROTECTED; } return FR_OK; /* The filesystem object is valid */ @@ -3289,11 +3288,9 @@ static FRESULT find_volume ( /* FR_OK(0): successful, !=0: an error occurred */ fs->pdrv = LD2PD(vol); /* Bind the logical drive and a physical drive */ stat = disk_initialize(fs->pdrv); /* Initialize the physical drive */ if (stat & STA_NOINIT) { /* Check if the initialization succeeded */ - EFSPRINTF("MDNR"); return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */ } if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */ - EFSPRINTF("WPEN2"); return FR_WRITE_PROTECTED; } #if FF_MAX_SS != FF_MIN_SS /* Get sector size (multiple sector size cfg only) */ @@ -4712,9 +4709,9 @@ DWORD *f_expand_cltbl ( } if (f_lseek(fp, CREATE_LINKMAP)) { /* Create cluster link table */ ff_memfree(fp->cltbl); - fp->cltbl = NULL; + fp->cltbl = (void *)0; EFSPRINTF("CLTBLSZ"); - return NULL; + return (void *)0; } f_lseek(fp, 0); @@ -6737,6 +6734,8 @@ int f_puts ( putbuff pb; + if (str == (void *)0) return EOF; /* String is NULL */ + putc_init(&pb, fp); while (*str) putc_bfd(&pb, *str++); /* Put the string */ return putc_flush(&pb); @@ -6763,6 +6762,8 @@ int f_printf ( TCHAR c, d, str[32], *p; + if (fmt == (void *)0) return EOF; /* String is NULL */ + putc_init(&pb, fp); va_start(arp, fmt); diff --git a/bdk/mem/minerva.h b/bdk/mem/minerva.h index 51cb215..a81cdc8 100644 --- a/bdk/mem/minerva.h +++ b/bdk/mem/minerva.h @@ -27,8 +27,8 @@ typedef struct { - s32 rate_to; - s32 rate_from; + u32 rate_to; + u32 rate_from; emc_table_t *mtc_table; u32 table_entries; emc_table_t *current_emc_table; diff --git a/bdk/mem/sdram.c b/bdk/mem/sdram.c index 0f2ce3e..00ec355 100644 --- a/bdk/mem/sdram.c +++ b/bdk/mem/sdram.c @@ -55,11 +55,11 @@ static const u8 dram_encoding_t210b01[] = { LPDDR4X_NO_PATCH, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ, LPDDR4X_NO_PATCH, - LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046, + LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE, LPDDR4X_NO_PATCH, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ, LPDDR4X_NO_PATCH, - LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046, + LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE, LPDDR4X_4GB_SAMSUNG_Y, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL, @@ -69,9 +69,9 @@ static const u8 dram_encoding_t210b01[] = { LPDDR4X_UNUSED, // Removed. LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL, - LPDDR4X_4GB_MICRON_1Y_A, - LPDDR4X_4GB_MICRON_1Y_A, - LPDDR4X_4GB_MICRON_1Y_A, + LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF, + LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF, + LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL, }; diff --git a/bdk/mem/sdram.h b/bdk/mem/sdram.h index 3caac47..42907f9 100644 --- a/bdk/mem/sdram.h +++ b/bdk/mem/sdram.h @@ -50,7 +50,7 @@ enum sdram_ids_erista // LPDDR4 3200Mbps. LPDDR4_ICOSA_4GB_SAMSUNG_K4F6E304HB_MGCH = 0, LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE = 1, - LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WT = 2, + LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WT = 2, // WT:C. LPDDR4_COPPER_4GB_SAMSUNG_K4F6E304HB_MGCH = 3, // Changed to Iowa Hynix 4GB 1Y-A. LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH = 4, LPDDR4_COPPER_4GB_HYNIX_H9HCNNNBPUMLHR_NLE = 5, // Changed to Hoag Hynix 4GB 1Y-A. @@ -70,12 +70,12 @@ enum sdram_ids_mariko LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AM_MGCJ = 8, // Die-M. LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 9, // Die-M. LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLHR_NME = 10, // Die-M. - LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WT = 11, // 4266Mbps. WT:E. Die-E. + LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTE = 11, // 4266Mbps. Die-E. LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AM_MGCJ = 12, // Die-M. LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 13, // Die-M. LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLHR_NME = 14, // Die-M. - LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WT = 15, // 4266Mbps. WT:E. Die-E. + LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTE = 15, // 4266Mbps. Die-E. // LPDDR4X 4266Mbps. LPDDR4X_IOWA_4GB_SAMSUNG_Y = 16, @@ -92,9 +92,9 @@ enum sdram_ids_mariko LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 23, // Die-A. LPDDR4X_AULA_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 24, // Die-A. - LPDDR4X_IOWA_4GB_MICRON_1Y_A = 25, - LPDDR4X_HOAG_4GB_MICRON_1Y_A = 26, - LPDDR4X_AULA_4GB_MICRON_1Y_A = 27, + LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 25, // 4266Mbps. Die-F. + LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTF = 26, // 4266Mbps. Die-F. + LPDDR4X_AULA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 27, // 4266Mbps. Die-F. LPDDR4X_AULA_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 28, // Die-A. }; @@ -107,17 +107,17 @@ enum sdram_codes_mariko // LPDDR4X_4GB_SAMSUNG_K4U6E3S4AM_MGCJ DRAM IDs: 08, 12. // LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLHR_NME DRAM IDs: 10, 14. - LPDDR4X_4GB_SAMSUNG_X1X2 = 1, // DRAM IDs: 07. - LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 2, // DRAM IDs: 09, 13. - LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046 = 3, // DRAM IDs: 11, 15. - LPDDR4X_4GB_SAMSUNG_Y = 4, // DRAM IDs: 16. - LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 5, // DRAM IDs: 17, 19, 24. - LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 6, // DRAM IDs: 18, 23, 28. - LPDDR4X_4GB_SAMSUNG_1Y_Y = 7, // DRAM IDs: 20. - LPDDR4X_8GB_SAMSUNG_1Y_Y = 8, // DRAM IDs: 21. - //LPDDR4X_8GB_SAMSUNG_1Y_A = 9, // DRAM IDs: 22. Unused. - LPDDR4X_4GB_MICRON_1Y_A = 10, // DRAM IDs: 25, 26, 27. - LPDDR4X_4GB_HYNIX_1Y_A = 11, // DRAM IDs: 03, 05, 06. + LPDDR4X_4GB_SAMSUNG_X1X2 = 1, // DRAM IDs: 07. + LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 2, // DRAM IDs: 09, 13. + LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE = 3, // DRAM IDs: 11, 15. + LPDDR4X_4GB_SAMSUNG_Y = 4, // DRAM IDs: 16. + LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 5, // DRAM IDs: 17, 19, 24. + LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 6, // DRAM IDs: 18, 23, 28. + LPDDR4X_4GB_SAMSUNG_1Y_Y = 7, // DRAM IDs: 20. + LPDDR4X_8GB_SAMSUNG_1Y_Y = 8, // DRAM IDs: 21. + //LPDDR4X_8GB_SAMSUNG_1Y_A = 9, // DRAM IDs: 22. Unused. + LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF = 10, // DRAM IDs: 25, 26, 27. + LPDDR4X_4GB_HYNIX_1Y_A = 11, // DRAM IDs: 03, 05, 06. }; void sdram_init(); diff --git a/bdk/mem/sdram_config_t210b01.inl b/bdk/mem/sdram_config_t210b01.inl index 0d1d617..28cc063 100644 --- a/bdk/mem/sdram_config_t210b01.inl +++ b/bdk/mem/sdram_config_t210b01.inl @@ -769,13 +769,13 @@ static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210b01[] = { { 0x2A800000, 0x6DC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // mc_video_protect_gpu_override0. { 0x00000002, 0x6E0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // mc_video_protect_gpu_override1. - // Micron LPDDR4X 4GB MT53D1024M32D1NP-053-WT Die-E for retail Iowa and Hoag. - { 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046 }, // emc_auto_cal_config2. - { 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046 }, // emc_auto_cal_vref_sel0. - { 0x88161414, 0x2E0 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046 }, // emc_mrw14. - { 0x80000713, 0x32C / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046 }, // emc_dyn_self_ref_control. - { 0x2A800000, 0x6DC / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046 }, // mc_video_protect_gpu_override0. - { 0x00000002, 0x6E0 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046 }, // mc_video_protect_gpu_override1. + // Micron LPDDR4X 4GB MT53D1024M32D1NP-053-WT:E Die-E for retail Iowa and Hoag. + { 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE }, // emc_auto_cal_config2. + { 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE }, // emc_auto_cal_vref_sel0. + { 0x88161414, 0x2E0 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE }, // emc_mrw14. + { 0x80000713, 0x32C / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE }, // emc_dyn_self_ref_control. + { 0x2A800000, 0x6DC / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE }, // mc_video_protect_gpu_override0. + { 0x00000002, 0x6E0 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE }, // mc_video_protect_gpu_override1. // Samsung LPDDR4X 4GB (Y01) Die-? for Iowa. { 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_auto_cal_config2. @@ -957,19 +957,20 @@ static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210b01[] = { { 0x00000002, 0x680 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // mc_emem_arb_timing_r2r. { 0x02020001, 0x694 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // mc_emem_arb_da_turns. */ - // Micron LPDDR4X 4GB 10nm-class (1y-01) Die-A for Unknown Iowa/Hoag/Aula. - { 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_auto_cal_config2. - { 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_auto_cal_vref_sel0. - { 0x00000006, 0x1CC / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_quse. - { 0x00000005, 0x1D0 / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_quse_width. - { 0x00000003, 0x1DC / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_einput. - { 0x0000000C, 0x1E0 / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_einput_duration. - { 0x00000008, 0x24C / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_tfaw. - { 0x88161414, 0x2E0 / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_mrw14. - { 0x80000713, 0x32C / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_dyn_self_ref_control. - { 0x00000001, 0x670 / 4, LPDDR4X_4GB_MICRON_1Y_A }, // mc_emem_arb_timing_faw. - { 0x2A800000, 0x6DC / 4, LPDDR4X_4GB_MICRON_1Y_A }, // mc_video_protect_gpu_override0. - { 0x00000002, 0x6E0 / 4, LPDDR4X_4GB_MICRON_1Y_A }, // mc_video_protect_gpu_override1. + + // Micron LPDDR4X 4GB MT53D1024M32D1NP-053-WT:F 10nm-class (1y-01) Die-F for Newer Iowa/Hoag/Aula. + { 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_auto_cal_config2. + { 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_auto_cal_vref_sel0. + { 0x00000006, 0x1CC / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_quse. + { 0x00000005, 0x1D0 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_quse_width. + { 0x00000003, 0x1DC / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_einput. + { 0x0000000C, 0x1E0 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_einput_duration. + { 0x00000008, 0x24C / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_tfaw. + { 0x88161414, 0x2E0 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_mrw14. + { 0x80000713, 0x32C / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // emc_dyn_self_ref_control. + { 0x00000001, 0x670 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // mc_emem_arb_timing_faw. + { 0x2A800000, 0x6DC / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // mc_video_protect_gpu_override0. + { 0x00000002, 0x6E0 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF }, // mc_video_protect_gpu_override1. // Hynix LPDDR4X 4GB 10nm-class (1y-01) Die-A for Unknown Iowa/Hoag/Aula. { 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_auto_cal_config2. diff --git a/bdk/mem/smmu.c b/bdk/mem/smmu.c index 6ee99b9..f2f20fb 100644 --- a/bdk/mem/smmu.c +++ b/bdk/mem/smmu.c @@ -48,8 +48,8 @@ u8 smmu_payload[] __attribute__((aligned(16))) = { void *page_alloc(u32 num) { u8 *res = _pageheap; - _pageheap += 0x1000 * num; - memset(res, 0, 0x1000 * num); + _pageheap += SZ_PAGE * num; + memset(res, 0, SZ_PAGE * num); return res; } @@ -150,8 +150,8 @@ void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr) { u32 *pte = smmu_get_pte(pdir, addr); *pte = SMMU_ADDR_TO_PFN(page) | attr; - addr += 0x1000; - page += 0x1000; + addr += SZ_PAGE; + page += SZ_PAGE; } smmu_flush_all(); } diff --git a/bdk/memory_map.h b/bdk/memory_map.h index 70f1354..4303ddd 100644 --- a/bdk/memory_map.h +++ b/bdk/memory_map.h @@ -23,7 +23,7 @@ #define LDR_LOAD_ADDR 0x40007000 #define IPL_LOAD_ADDR 0x40008000 -#define IPL_SZ_MAX 0x20000 // 128KB. +#define IPL_SZ_MAX SZ_128K /* --- XUSB EP context and TRB ring buffers --- */ #define XUSB_RING_ADDR 0x40020000 @@ -35,16 +35,16 @@ /* --- DRAM START --- */ #define DRAM_START 0x80000000 -#define HOS_RSVD 0x1000000 // Do not write anything in this area. +#define HOS_RSVD SZ_16M // Do not write anything in this area. #define NYX_LOAD_ADDR 0x81000000 -#define NYX_SZ_MAX 0x1000000 // 16MB +#define NYX_SZ_MAX SZ_16M /* --- Gap: 0x82000000 - 0x82FFFFFF --- */ /* Stack theoretical max: 33MB */ #define IPL_STACK_TOP 0x83100000 #define IPL_HEAP_START 0x84000000 -#define IPL_HEAP_SZ 0x20000000 // 512MB. +#define IPL_HEAP_SZ SZ_512M /* --- Gap: 1040MB 0xA4000000 - 0xE4FFFFFF --- */ // Virtual disk / Chainloader buffers. @@ -60,26 +60,26 @@ // L4T Kernel Panic Storage (PSTORE). #define PSTORE_ADDR 0xB0000000 -#define PSTORE_SZ 0x200000 // 2MB. +#define PSTORE_SZ SZ_2M //#define DRAM_LIB_ADDR 0xE0000000 /* --- Chnldr: 252MB 0xC03C0000 - 0xCFFFFFFF --- */ //! Only used when chainloading. // SDMMC DMA buffers 1 #define SDMMC_UPPER_BUFFER 0xE5000000 -#define SDMMC_UP_BUF_SZ 0x8000000 // 128MB. +#define SDMMC_UP_BUF_SZ SZ_128M // Nyx buffers. #define NYX_STORAGE_ADDR 0xED000000 #define NYX_RES_ADDR 0xEE000000 -#define NYX_RES_SZ 0x1000000 // 16MB. +#define NYX_RES_SZ SZ_16M // SDMMC DMA buffers 2 #define SDXC_BUF_ALIGNED 0xEF000000 #define MIXD_BUF_ALIGNED 0xF0000000 #define TITLEKEY_BUF_ADR MIXD_BUF_ALIGNED #define EMMC_BUF_ALIGNED MIXD_BUF_ALIGNED -#define SDMMC_DMA_BUF_SZ 0x1000000 // 16MB (4MB currently used). +#define SDMMC_DMA_BUF_SZ SZ_16M // 4MB currently used. // Nyx LvGL buffers. #define NYX_LV_VDB_ADR 0xF1000000 @@ -107,7 +107,7 @@ #define USB_EP_CONTROL_BUF_ADDR 0xFEF80000 #define USB_EP_BULK_IN_BUF_ADDR 0xFF000000 #define USB_EP_BULK_OUT_BUF_ADDR 0xFF800000 -#define USB_EP_BULK_OUT_MAX_XFER 0x800000 +#define USB_EP_BULK_OUT_MAX_XFER SZ_8M // #define EXT_PAYLOAD_ADDR 0xC0000000 // #define RCM_PAYLOAD_ADDR (EXT_PAYLOAD_ADDR + ALIGN(PATCHED_RELOC_SZ, 0x10)) diff --git a/bdk/power/regulator_5v.c b/bdk/power/regulator_5v.c index 7b8924b..379f7a6 100644 --- a/bdk/power/regulator_5v.c +++ b/bdk/power/regulator_5v.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 CTCaer + * Copyright (c) 2019-2021 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,7 +14,9 @@ * along with this program. If not, see . */ +#include #include +#include #include #include #include @@ -34,17 +36,30 @@ void regulator_5v_enable(u8 dev) gpio_output_enable(GPIO_PORT_A, GPIO_PIN_5, GPIO_OUTPUT_ENABLE); gpio_write(GPIO_PORT_A, GPIO_PIN_5, GPIO_HIGH); - // Fan and Rail power from USB 5V VBUS. - PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN0) = PINMUX_LPDR | 1; - gpio_config(GPIO_PORT_CC, GPIO_PIN_4, GPIO_MODE_GPIO); - gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_4, GPIO_OUTPUT_ENABLE); - gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW); - usb_src = false; + // Only Icosa and Iowa have USB 5V VBUS rails. Skip on Hoag/Aula. + u32 hw_type = fuse_read_hw_type(); + if (hw_type == FUSE_NX_HW_TYPE_ICOSA || + hw_type == FUSE_NX_HW_TYPE_IOWA) + { + // Fan and Rail power from USB 5V VBUS. + PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN0) = PINMUX_LPDR | 1; + gpio_config(GPIO_PORT_CC, GPIO_PIN_4, GPIO_MODE_GPIO); + gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_4, GPIO_OUTPUT_ENABLE); + gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW); + } - // Make sure GPIO power is enabled. - PMC(APBDEV_PMC_NO_IOPOWER) &= ~PMC_NO_IOPOWER_GPIO_IO_EN; - // Override power detect for GPIO AO IO rails. - PMC(APBDEV_PMC_PWR_DET_VAL) &= ~PMC_PWR_DET_GPIO_IO_EN; + // Enable GPIO AO IO rail for T210. + if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210) + { + // Make sure GPIO power is enabled. + PMC(APBDEV_PMC_NO_IOPOWER) &= ~PMC_NO_IOPOWER_GPIO_IO_EN; + (void)PMC(APBDEV_PMC_NO_IOPOWER); // Commit write. + + // Override power detect for GPIO AO IO rails. + PMC(APBDEV_PMC_PWR_DET_VAL) &= ~PMC_PWR_DET_GPIO_IO_EN; + (void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write. + } + usb_src = false; } reg_5v_dev |= dev; } @@ -61,15 +76,26 @@ void regulator_5v_disable(u8 dev) gpio_config(GPIO_PORT_A, GPIO_PIN_5, GPIO_MODE_SPIO); PINMUX_AUX(PINMUX_AUX_SATA_LED_ACTIVE) = PINMUX_PARKED | PINMUX_INPUT_ENABLE; - // Rail power from USB 5V VBUS. - gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW); - gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_4, GPIO_OUTPUT_DISABLE); - gpio_config(GPIO_PORT_CC, GPIO_PIN_4, GPIO_MODE_SPIO); - PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN0) = PINMUX_IO_HV | PINMUX_LPDR | PINMUX_PARKED | PINMUX_INPUT_ENABLE; - usb_src = false; + // Only Icosa and Iowa have USB 5V VBUS rails. Skip on Hoag/Aula. + u32 hw_type = fuse_read_hw_type(); + if (hw_type == FUSE_NX_HW_TYPE_ICOSA || + hw_type == FUSE_NX_HW_TYPE_IOWA) + { + // Rail power from USB 5V VBUS. + gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW); + gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_4, GPIO_OUTPUT_DISABLE); + gpio_config(GPIO_PORT_CC, GPIO_PIN_4, GPIO_MODE_SPIO); + PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN0) = PINMUX_IO_HV | PINMUX_LPDR | PINMUX_PARKED | PINMUX_INPUT_ENABLE; + usb_src = false; + + } // GPIO AO IO rails. - PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_GPIO_IO_EN; + if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210) + { + PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_GPIO_IO_EN; + (void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write. + } } } @@ -80,6 +106,12 @@ bool regulator_5v_get_dev_enabled(u8 dev) void regulator_5v_usb_src_enable(bool enable) { + // Only for Icosa/Iowa. Skip on Hoag/Aula. + u32 hw_type = fuse_read_hw_type(); + if (hw_type != FUSE_NX_HW_TYPE_ICOSA && + hw_type != FUSE_NX_HW_TYPE_IOWA) + return; + if (enable && !usb_src) { gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_HIGH); diff --git a/bdk/sec/tsec.c b/bdk/sec/tsec.c index 1e9d01f..50a90ae 100644 --- a/bdk/sec/tsec.c +++ b/bdk/sec/tsec.c @@ -125,7 +125,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) TSEC(TSEC_DMATRFBASE) = (u32)tsec_ctxt->fw >> 8; else { - fwbuf = (u8 *)malloc(0x4000); + fwbuf = (u8 *)malloc(SZ_16K); u8 *fwbuf_aligned = (u8 *)ALIGN((u32)fwbuf, 0x100); memcpy(fwbuf_aligned, tsec_ctxt->fw, tsec_ctxt->size); TSEC(TSEC_DMATRFBASE) = (u32)fwbuf_aligned >> 8; @@ -151,13 +151,13 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) // Clock reset controller. car = page_alloc(1); - memcpy(car, (void *)CLOCK_BASE, 0x1000); + memcpy(car, (void *)CLOCK_BASE, SZ_PAGE); car[CLK_RST_CONTROLLER_CLK_SOURCE_TSEC / 4] = 2; smmu_map(pdir, CLOCK_BASE, (u32)car, 1, _WRITABLE | _READABLE | _NONSECURE); // Fuse driver. fuse = page_alloc(1); - memcpy((void *)&fuse[0x800/4], (void *)FUSE_BASE, 0x400); + memcpy((void *)&fuse[0x800/4], (void *)FUSE_BASE, SZ_1K); fuse[0x82C / 4] = 0; fuse[0x9E0 / 4] = (1 << (TSEC_HOS_KB_620 + 2)) - 1; fuse[0x9E4 / 4] = (1 << (TSEC_HOS_KB_620 + 2)) - 1; @@ -173,12 +173,12 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) // Security engine. se = page_alloc(1); - memcpy(se, (void *)SE_BASE, 0x1000); + memcpy(se, (void *)SE_BASE, SZ_PAGE); smmu_map(pdir, SE_BASE, (u32)se, 1, _READABLE | _WRITABLE | _NONSECURE); // Memory controller. mc = page_alloc(1); - memcpy(mc, (void *)MC_BASE, 0x1000); + memcpy(mc, (void *)MC_BASE, SZ_PAGE); mc[MC_IRAM_BOM / 4] = 0; mc[MC_IRAM_TOM / 4] = 0x80000000; smmu_map(pdir, MC_BASE, (u32)mc, 1, _READABLE | _NONSECURE); diff --git a/bdk/soc/hw_init.c b/bdk/soc/hw_init.c index 5efe5df..c86dc3a 100644 --- a/bdk/soc/hw_init.c +++ b/bdk/soc/hw_init.c @@ -48,14 +48,8 @@ extern boot_cfg_t b_cfg; extern volatile nyx_storage_t *nyx_str; -/* - * CLK_OSC - 38.4 MHz crystal. - * CLK_M - 19.2 MHz (osc/2). - * CLK_S - 32.768 KHz (from PMIC). - * SCLK - 204MHz init (-> 408MHz -> OC). - * HCLK - 204MHz init (-> 408MHz -> OC). - * PCLK - 68MHz init (-> 136MHz -> OC/4). - */ +u32 hw_rst_status; +u32 hw_rst_reason; u32 hw_get_chip_id() { @@ -65,6 +59,15 @@ u32 hw_get_chip_id() return GP_HIDREV_MAJOR_T210; } +/* + * CLK_OSC - 38.4 MHz crystal. + * CLK_M - 19.2 MHz (osc/2). + * CLK_S - 32.768 KHz (from PMIC). + * SCLK - 204MHz init (-> 408MHz -> OC). + * HCLK - 204MHz init (-> 408MHz -> OC). + * PCLK - 68MHz init (-> 136MHz -> OC/4). + */ + static void _config_oscillators() { CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; // Set CLK_M_DIVISOR to 2. @@ -260,11 +263,15 @@ static void _config_se_brom() // se_key_acc_ctrl(15, SE_KEY_TBL_DIS_KEYREAD_FLAG); // This memset needs to happen here, else TZRAM will behave weirdly later on. - memset((void *)TZRAM_BASE, 0, 0x10000); + memset((void *)TZRAM_BASE, 0, SZ_64K); PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_ENABLE; SE(SE_INT_STATUS_REG) = 0x1F; // Clear all SE interrupts. - // Clear the boot reason to avoid problems later + // Save reset reason. + hw_rst_status = PMC(APBDEV_PMC_SCRATCH200); + hw_rst_reason = PMC(APBDEV_PMC_RST_STATUS) & PMC_RST_STATUS_MASK; + + // Clear the boot reason to avoid problems later. PMC(APBDEV_PMC_SCRATCH200) = 0x0; PMC(APBDEV_PMC_RST_STATUS) = 0x0; APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = (APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) & 0xF0) | (7 << 10); diff --git a/bdk/soc/hw_init.h b/bdk/soc/hw_init.h index a1b2dfc..4a24c33 100644 --- a/bdk/soc/hw_init.h +++ b/bdk/soc/hw_init.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2021 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -23,6 +23,9 @@ #define BL_MAGIC_CRBOOT_SLD 0x30444C53 // SLD0, seamless display type 0. #define BL_MAGIC_BROKEN_HWI 0xBAADF00D // Broken hwinit. +extern u32 hw_rst_status; +extern u32 hw_rst_reason; + void hw_init(); void hw_reinit_workaround(bool coreboot, u32 magic); u32 hw_get_chip_id(); diff --git a/bdk/soc/pmc.h b/bdk/soc/pmc.h index 42bd869..937786a 100644 --- a/bdk/soc/pmc.h +++ b/bdk/soc/pmc.h @@ -60,6 +60,13 @@ #define APBDEV_PMC_CLK_OUT_CNTRL 0x1A8 #define PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN BIT(2) #define APBDEV_PMC_RST_STATUS 0x1B4 +#define PMC_RST_STATUS_MASK 0x7 +#define PMC_RST_STATUS_POR 0 +#define PMC_RST_STATUS_WATCHDOG 1 +#define PMC_RST_STATUS_SENSOR 2 +#define PMC_RST_STATUS_SW_MAIN 3 +#define PMC_RST_STATUS_LP0 4 +#define PMC_RST_STATUS_AOTAG 5 #define APBDEV_PMC_IO_DPD_REQ 0x1B8 #define PMC_IO_DPD_REQ_DPD_OFF BIT(30) #define APBDEV_PMC_IO_DPD2_REQ 0x1C0 diff --git a/bdk/thermal/fan.c b/bdk/thermal/fan.c index 14379e3..9e7a65e 100644 --- a/bdk/thermal/fan.c +++ b/bdk/thermal/fan.c @@ -1,7 +1,7 @@ /* * Fan driver for Nintendo Switch * - * Copyright (c) 2018-2020 CTCaer + * Copyright (c) 2018-2021 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,6 +18,7 @@ #include #include +#include #include #include #include @@ -28,9 +29,20 @@ void set_fan_duty(u32 duty) static bool fan_init = false; static u16 curr_duty = -1; + if (duty > 236) + duty = 236; + if (curr_duty == duty) return; + curr_duty = duty; + + //! TODO: Add HOAG/AULA support. + u32 hw_type = fuse_read_hw_type(); + if (hw_type != FUSE_NX_HW_TYPE_ICOSA && + hw_type != FUSE_NX_HW_TYPE_IOWA) + return; + if (!fan_init) { // Fan tachometer. @@ -46,9 +58,6 @@ void set_fan_duty(u32 duty) fan_init = true; } - if (duty > 236) - duty = 236; - // Inverted polarity. u32 inv_duty = 236 - duty; @@ -71,8 +80,6 @@ void set_fan_duty(u32 duty) // Enable fan. PINMUX_AUX(PINMUX_AUX_LCD_GPIO2) = 1; // Set source to PWM1. } - - curr_duty = duty; } void get_fan_speed(u32 *duty, u32 *rpm) diff --git a/bdk/usb/usb_gadget_ums.c b/bdk/usb/usb_gadget_ums.c index 4be2436..2b90439 100644 --- a/bdk/usb/usb_gadget_ums.c +++ b/bdk/usb/usb_gadget_ums.c @@ -1092,8 +1092,7 @@ static int _scsi_prevent_allow_removal(usbd_gadget_ums_t *ums) // Notify for possible unmounting? // Normally we sync here but we do synced writes to SDMMC. - if (ums->lun.prevent_medium_removal && !prevent) - ; + if (ums->lun.prevent_medium_removal && !prevent) { /* Do nothing */ } ums->lun.prevent_medium_removal = prevent; diff --git a/bdk/utils/types.h b/bdk/utils/types.h index b9c269e..4fc0101 100644 --- a/bdk/utils/types.h +++ b/bdk/utils/types.h @@ -20,10 +20,84 @@ #include +/* Types */ +typedef signed char s8; +typedef short s16; +typedef short SHORT; +typedef int s32; +typedef int INT; +typedef int bool; +typedef long LONG; +typedef long long int s64; + +typedef unsigned char u8; +typedef unsigned char BYTE; +typedef unsigned short u16; +typedef unsigned short WORD; +typedef unsigned short WCHAR; +typedef unsigned int u32; +typedef unsigned int UINT; +typedef unsigned long DWORD; +typedef unsigned long long QWORD; +typedef unsigned long long int u64; + +typedef volatile unsigned char vu8; +typedef volatile unsigned short vu16; +typedef volatile unsigned int vu32; + +#ifdef __aarch64__ +typedef u64 uptr; +#else /* __arm__ or __thumb__ */ +typedef u32 uptr; +#endif + +/* Colors */ +#define COLOR_RED 0xFFE70000 +#define COLOR_ORANGE 0xFFFF8C00 +#define COLOR_YELLOW 0xFFFFFF40 +#define COLOR_GREEN 0xFF40FF00 +#define COLOR_BLUE 0xFF00DDFF +#define COLOR_VIOLET 0xFF8040FF + +static const u32 colors[6] = {COLOR_RED, COLOR_ORANGE, COLOR_YELLOW, COLOR_GREEN, COLOR_BLUE, COLOR_VIOLET}; + +/* Important */ +#define false 0 +#define true 1 + #define NULL ((void *)0) -#define ALWAYS_INLINE inline __attribute__((always_inline)) +/* Misc */ +#define DISABLE 0 +#define ENABLE 1 +/* Sizes */ +#define SZ_1K 0x400 +#define SZ_2K 0x800 +#define SZ_4K 0x1000 +#define SZ_8K 0x2000 +#define SZ_16K 0x4000 +#define SZ_32K 0x8000 +#define SZ_64K 0x10000 +#define SZ_128K 0x20000 +#define SZ_256K 0x40000 +#define SZ_512K 0x80000 +#define SZ_1M 0x100000 +#define SZ_2M 0x200000 +#define SZ_4M 0x400000 +#define SZ_8M 0x800000 +#define SZ_16M 0x1000000 +#define SZ_32M 0x2000000 +#define SZ_64M 0x4000000 +#define SZ_128M 0x8000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 +#define SZ_PAGE SZ_4K + +/* Macros */ +#define ALWAYS_INLINE inline __attribute__((always_inline)) #define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) #define ALIGN_DOWN(x, a) ((x) & ~((a) - 1)) #define BIT(n) (1U << (n)) @@ -36,58 +110,37 @@ #define CLZ(n) __builtin_clz(n) #define CLO(n) __builtin_clz(~n) -#define OFFSET_OF(t, m) ((u32)&((t *)NULL)->m) -#define CONTAINER_OF(mp, t, mn) ((t *)((u32)mp - OFFSET_OF(t, mn))) +#define OFFSET_OF(t, m) ((uptr)&((t *)NULL)->m) +#define CONTAINER_OF(mp, t, mn) ((t *)((uptr)mp - OFFSET_OF(t, mn))) -#define COLOR_RED 0xFFE70000 -#define COLOR_ORANGE 0xFFFF8C00 -#define COLOR_YELLOW 0xFFFFFF40 -#define COLOR_GREEN 0xFF40FF00 -#define COLOR_BLUE 0xFF00DDFF -#define COLOR_VIOLET 0xFF8040FF +#define byte_swap_16(num) ((((num) >> 8) & 0xff) | (((num) << 8) & 0xff00)) +#define byte_swap_32(num) ((((num) >> 24) & 0xff) | (((num) << 8) & 0xff0000) | \ + (((num) >> 8 )& 0xff00) | (((num) << 24) & 0xff000000)) -typedef signed char s8; -typedef short s16; -typedef short SHORT; -typedef int s32; -typedef int INT; -typedef long LONG; -typedef long long int s64; -typedef unsigned char u8; -typedef unsigned char BYTE; -typedef unsigned short u16; -typedef unsigned short WORD; -typedef unsigned short WCHAR; -typedef unsigned int u32; -typedef unsigned int UINT; -typedef unsigned long DWORD; -typedef unsigned long long QWORD; -typedef unsigned long long int u64; -typedef volatile unsigned char vu8; -typedef volatile unsigned short vu16; -typedef volatile unsigned int vu32; - -#ifdef __aarch64__ -typedef u64 uptr; -#else /* __arm__ or __thumb__ */ -typedef u32 uptr; -#endif - -static const u32 colors[6] = {COLOR_RED, COLOR_ORANGE, COLOR_YELLOW, COLOR_GREEN, COLOR_BLUE, COLOR_VIOLET}; - -typedef int bool; -#define true 1 -#define false 0 - -#define DISABLE 0 -#define ENABLE 1 +/* Bootloader/Nyx */ #define BOOT_CFG_AUTOBOOT_EN BIT(0) #define BOOT_CFG_FROM_LAUNCH BIT(1) #define BOOT_CFG_FROM_ID BIT(2) #define BOOT_CFG_TO_EMUMMC BIT(3) -#define EXTRA_CFG_DUMP_EMUMMC BIT(0) +#define EXTRA_CFG_KEYS BIT(0) +#define EXTRA_CFG_PAYLOAD BIT(1) +#define EXTRA_CFG_MODULE BIT(2) + +#define EXTRA_CFG_NYX_UMS BIT(5) +#define EXTRA_CFG_NYX_RELOAD BIT(6) + +typedef enum _nyx_ums_type +{ + NYX_UMS_SD_CARD = 0, + NYX_UMS_EMMC_BOOT0, + NYX_UMS_EMMC_BOOT1, + NYX_UMS_EMMC_GPP, + NYX_UMS_EMUMMC_BOOT0, + NYX_UMS_EMUMMC_BOOT1, + NYX_UMS_EMUMMC_GPP +} nyx_ums_type; typedef struct __attribute__((__packed__)) _boot_cfg_t { @@ -107,7 +160,7 @@ typedef struct __attribute__((__packed__)) _boot_cfg_t }; } boot_cfg_t; -static_assert(sizeof(boot_cfg_t) == 0x84, "Boot CFG size is wrong!"); +static_assert(sizeof(boot_cfg_t) == 0x84, "Boot cfg storage size is wrong!"); typedef struct __attribute__((__packed__)) _ipl_ver_meta_t { diff --git a/bdk/utils/util.c b/bdk/utils/util.c index 2c21b28..146c404 100644 --- a/bdk/utils/util.c +++ b/bdk/utils/util.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert -* Copyright (c) 2018-2021 CTCaer +* Copyright (c) 2018-2020 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/bdk/utils/util.h b/bdk/utils/util.h index 213d9cf..d3d391f 100644 --- a/bdk/utils/util.h +++ b/bdk/utils/util.h @@ -21,6 +21,8 @@ #include #include +#define NYX_NEW_INFO 0x3058594E + typedef enum { REBOOT_RCM, // PMC reset. Enter RCM mode. @@ -33,9 +35,9 @@ typedef enum typedef enum { - NYX_CFG_BIS = BIT(5), NYX_CFG_UMS = BIT(6), - NYX_CFG_DUMP = BIT(7), + + NYX_CFG_EXTRA = 0xFF << 24 } nyx_cfg_t; typedef enum @@ -44,15 +46,11 @@ typedef enum ERR_SYSOLD_NYX = BIT(1), ERR_LIBSYS_MTC = BIT(2), ERR_SD_BOOT_EN = BIT(3), + ERR_PANIC_CODE = BIT(4), ERR_L4T_KERNEL = BIT(24), ERR_EXCEPTION = BIT(31), } hekate_errors_t; -#define byte_swap_32(num) ((((num) >> 24) & 0xff) | (((num) << 8) & 0xff0000) | \ - (((num) >> 8 )& 0xff00) | (((num) << 24) & 0xff000000)) - -#define byte_swap_16(num) ((((num) >> 8) & 0xff) | (((num) << 8) & 0xff00)) - typedef struct _cfg_op_t { u32 off; @@ -75,7 +73,7 @@ typedef struct _nyx_storage_t u32 cfg; u8 irama[0x8000]; u8 hekate[0x30000]; - u8 rsvd[0x800000 - sizeof(nyx_info_t)]; + u8 rsvd[SZ_8M - sizeof(nyx_info_t)]; nyx_info_t info; mtc_config_t mtc_cfg; emc_table_t mtc_table[10]; @@ -87,9 +85,9 @@ u32 bit_count_mask(u8 bits); void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops); u32 crc32_calc(u32 crc, const u8 *buf, u32 len); -u32 get_tmr_us(); -u32 get_tmr_ms(); -u32 get_tmr_s(); +u32 get_tmr_us(); +u32 get_tmr_ms(); +u32 get_tmr_s(); void usleep(u32 us); void msleep(u32 ms); diff --git a/source/storage/emummc.c b/source/storage/emummc.c index 52a748e..fc44be3 100644 --- a/source/storage/emummc.c +++ b/source/storage/emummc.c @@ -42,9 +42,9 @@ void emummc_load_cfg() emu_cfg.active_part = 0; emu_cfg.fs_ver = 0; if (!emu_cfg.nintendo_path) - emu_cfg.nintendo_path = (char *)malloc(0x80); + emu_cfg.nintendo_path = (char *)malloc(0x200); if (!emu_cfg.emummc_file_based_path) - emu_cfg.emummc_file_based_path = (char *)malloc(0x80); + emu_cfg.emummc_file_based_path = (char *)malloc(0x200); emu_cfg.nintendo_path[0] = 0; emu_cfg.emummc_file_based_path[0] = 0; @@ -109,7 +109,14 @@ bool emummc_set_path(char *path) if (found) { emu_cfg.enabled = 1; - emu_cfg.id = 0; + + // Get ID from path. + u32 id_from_path = 0; + u32 path_size = strlen(path); + if (path_size >= 4) + memcpy(&id_from_path, path + path_size - 4, 4); + emu_cfg.id = id_from_path; + strcpy(emu_cfg.nintendo_path, path); strcat(emu_cfg.nintendo_path, "/Nintendo"); } diff --git a/source/storage/emummc.h b/source/storage/emummc.h index e8b1d32..7e162fd 100644 --- a/source/storage/emummc.h +++ b/source/storage/emummc.h @@ -37,7 +37,7 @@ typedef struct _emummc_cfg_t { int enabled; u64 sector; - u16 id; + u32 id; char *path; char *nintendo_path; // Internal.