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<p>Flashcart Boot IO.
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SP_SR_SET_INTR_BREAK</b>&#160;&#160;&#160;(1 &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SP_SR_SET_SIG1</b>&#160;&#160;&#160;(1 &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SP_SR_CLR_SIG2</b>&#160;&#160;&#160;(1 &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SP_SR_SET_SIG3</b>&#160;&#160;&#160;(1 &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SP_SR_CLR_SIG4</b>&#160;&#160;&#160;(1 &lt;&lt; 17)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SP_SR_CLR_SIG5</b>&#160;&#160;&#160;(1 &lt;&lt; 19)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SP_SR_SET_SIG5</b>&#160;&#160;&#160;(1 &lt;&lt; 20)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SP_SR_CLR_SIG6</b>&#160;&#160;&#160;(1 &lt;&lt; 21)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SP_SR_SET_SIG6</b>&#160;&#160;&#160;(1 &lt;&lt; 22)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SP_SR_CLR_SIG7</b>&#160;&#160;&#160;(1 &lt;&lt; 23)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SP_SR_SET_SIG7</b>&#160;&#160;&#160;(1 &lt;&lt; 24)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_BASE</b>&#160;&#160;&#160;(0x04100000UL)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC</b>&#160;&#160;&#160;((<a class="el" href="boot__io_8h.html#structdpc__regs__t">dpc_regs_t</a> *) DPC_BASE)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_XBUS_DMEM_DMA</b>&#160;&#160;&#160;(1 &lt;&lt; 0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_FREEZE</b>&#160;&#160;&#160;(1 &lt;&lt; 1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_FLUSH</b>&#160;&#160;&#160;(1 &lt;&lt; 2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_START_GCLK</b>&#160;&#160;&#160;(1 &lt;&lt; 3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_TMEM_BUSY</b>&#160;&#160;&#160;(1 &lt;&lt; 4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_PIPE_BUSY</b>&#160;&#160;&#160;(1 &lt;&lt; 5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_CMD_BUSY</b>&#160;&#160;&#160;(1 &lt;&lt; 6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_CBUF_READY</b>&#160;&#160;&#160;(1 &lt;&lt; 7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_DMA_BUSY</b>&#160;&#160;&#160;(1 &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_END_VALID</b>&#160;&#160;&#160;(1 &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_START_VALID</b>&#160;&#160;&#160;(1 &lt;&lt; 10)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_CLR_XBUS_DMEM_DMA</b>&#160;&#160;&#160;(1 &lt;&lt; 0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_SET_XBUS_DMEM_DMA</b>&#160;&#160;&#160;(1 &lt;&lt; 1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_CLR_FREEZE</b>&#160;&#160;&#160;(1 &lt;&lt; 2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_SET_FREEZE</b>&#160;&#160;&#160;(1 &lt;&lt; 3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_CLR_FLUSH</b>&#160;&#160;&#160;(1 &lt;&lt; 4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_SET_FLUSH</b>&#160;&#160;&#160;(1 &lt;&lt; 5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_CLR_TMEM_CTR</b>&#160;&#160;&#160;(1 &lt;&lt; 6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_CLR_PIPE_CTR</b>&#160;&#160;&#160;(1 &lt;&lt; 7)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_CLR_CMD_CTR</b>&#160;&#160;&#160;(1 &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>DPC_SR_CLR_CLOCK_CTR</b>&#160;&#160;&#160;(1 &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>VI_BASE</b>&#160;&#160;&#160;(0x04400000UL)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>VI</b>&#160;&#160;&#160;((<a class="el" href="boot__io_8h.html#structvi__regs__t">vi_regs_t</a> *) VI_BASE)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>VI_CR_TYPE_16</b>&#160;&#160;&#160;(2 &lt;&lt; 0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>VI_CR_TYPE_32</b>&#160;&#160;&#160;(3 &lt;&lt; 0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>VI_CR_GAMMA_DITHER_ON</b>&#160;&#160;&#160;(1 &lt;&lt; 2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>VI_CR_GAMMA_ON</b>&#160;&#160;&#160;(1 &lt;&lt; 3)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>VI_CR_DIVOT_ON</b>&#160;&#160;&#160;(1 &lt;&lt; 4)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>VI_CR_SERRATE_ON</b>&#160;&#160;&#160;(1 &lt;&lt; 6)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>VI_CR_ANTIALIAS_0</b>&#160;&#160;&#160;(1 &lt;&lt; 8)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>VI_CR_ANTIALIAS_1</b>&#160;&#160;&#160;(1 &lt;&lt; 9)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>VI_CR_PIXEL_ADVANCE_0</b>&#160;&#160;&#160;(1 &lt;&lt; 12)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>VI_CR_PIXEL_ADVANCE_1</b>&#160;&#160;&#160;(1 &lt;&lt; 13)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>VI_CR_PIXEL_ADVANCE_2</b>&#160;&#160;&#160;(1 &lt;&lt; 14)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>VI_CR_PIXEL_ADVANCE_3</b>&#160;&#160;&#160;(1 &lt;&lt; 15)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>VI_CR_DITHER_FILTER_ON</b>&#160;&#160;&#160;(1 &lt;&lt; 16)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>AI_BASE</b>&#160;&#160;&#160;(0x04500000UL)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>AI</b>&#160;&#160;&#160;((<a class="el" href="boot__io_8h.html#structai__regs__t">ai_regs_t</a> *) AI_BASE)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>AI_SR_DMA_BUSY</b>&#160;&#160;&#160;(1 &lt;&lt; 30)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>AI_SR_FIFO_FULL</b>&#160;&#160;&#160;(1 &lt;&lt; 31)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>AI_CR_DMA_ON</b>&#160;&#160;&#160;(1 &lt;&lt; 0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PI_BASE</b>&#160;&#160;&#160;(0x04600000UL)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PI</b>&#160;&#160;&#160;((<a class="el" href="boot__io_8h.html#structpi__regs__t">pi_regs_t</a> *) PI_BASE)</td></tr>
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<tr class="memitem:a4ba798e6de5b9d90385ddceebea42ca5"><td class="memItemLeft" align="right" valign="top"><a id="a4ba798e6de5b9d90385ddceebea42ca5" name="a4ba798e6de5b9d90385ddceebea42ca5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>PI_SR_DMA_BUSY</b>&#160;&#160;&#160;(1 &lt;&lt; 0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PI_SR_IO_BUSY</b>&#160;&#160;&#160;(1 &lt;&lt; 1)</td></tr>
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<tr class="memitem:a1481f4b773b33da476c6b95de928a78f"><td class="memItemLeft" align="right" valign="top"><a id="a1481f4b773b33da476c6b95de928a78f" name="a1481f4b773b33da476c6b95de928a78f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>PI_SR_DMA_ERROR</b>&#160;&#160;&#160;(1 &lt;&lt; 2)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PI_SR_RESET</b>&#160;&#160;&#160;(1 &lt;&lt; 0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>PI_SR_CLR_INTR</b>&#160;&#160;&#160;(1 &lt;&lt; 1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>ROM_DDIPL_BASE</b>&#160;&#160;&#160;(0x06000000UL)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>ROM_DDIPL</b>&#160;&#160;&#160;((io32_t *) ROM_DDIPL_BASE)</td></tr>
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<tr class="memitem:a59f3bc734491f22037dfa60dd92879bf"><td class="memItemLeft" align="right" valign="top"><a id="a59f3bc734491f22037dfa60dd92879bf" name="a59f3bc734491f22037dfa60dd92879bf"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>ROM_CART_BASE</b>&#160;&#160;&#160;(0x10000000UL)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>ROM_CART</b>&#160;&#160;&#160;((io32_t *) ROM_CART_BASE)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>OS_INFO_BASE</b>&#160;&#160;&#160;(0x80000300UL)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>OS_INFO</b>&#160;&#160;&#160;((<a class="el" href="boot__io_8h.html#structos__info__t">os_info_t</a> *) OS_INFO_BASE)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>OS_INFO_RESET_TYPE_COLD</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>OS_INFO_RESET_TYPE_NMI</b>&#160;&#160;&#160;(1)</td></tr>
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</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="typedef-members" name="typedef-members"></a>
Typedefs</h2></td></tr>
<tr class="memitem:a17232a6f3649d110a69bd3a794dbb399"><td class="memItemLeft" align="right" valign="top"><a id="a17232a6f3649d110a69bd3a794dbb399" name="a17232a6f3649d110a69bd3a794dbb399"></a>
typedef volatile uint8_t&#160;</td><td class="memItemRight" valign="bottom"><b>io8_t</b></td></tr>
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<tr class="memitem:a5de58f60d2817fcfe4de199acc6cb6f3"><td class="memItemLeft" align="right" valign="top"><a id="a5de58f60d2817fcfe4de199acc6cb6f3" name="a5de58f60d2817fcfe4de199acc6cb6f3"></a>
typedef volatile uint32_t&#160;</td><td class="memItemRight" valign="bottom"><b>io32_t</b></td></tr>
<tr class="separator:a5de58f60d2817fcfe4de199acc6cb6f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p >Flashcart Boot IO. </p>
</div><hr/><h2 class="groupheader">Data Structure Documentation</h2>
<a name="structsp__mem__t" id="structsp__mem__t"></a>
<h2 class="memtitle"><span class="permalink"><a href="#structsp__mem__t">&#9670;&#160;</a></span>sp_mem_t</h2>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">struct sp_mem_t</td>
</tr>
</table>
</div><div class="memdoc">
<div class="textblock"></div><table class="fieldtable">
<tr><th colspan="3">Data Fields</th></tr>
<tr><td class="fieldtype">
<a id="a32512a78ee9a245ff70426ce12d1c1db" name="a32512a78ee9a245ff70426ce12d1c1db"></a>io32_t</td>
<td class="fieldname">
DMEM[1024]</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a902eb2ad7b99b7f94e5d09a81e516a48" name="a902eb2ad7b99b7f94e5d09a81e516a48"></a>io32_t</td>
<td class="fieldname">
IMEM[1024]</td>
<td class="fielddoc">
</td></tr>
</table>
</div>
</div>
<a name="structsp__regs__t" id="structsp__regs__t"></a>
<h2 class="memtitle"><span class="permalink"><a href="#structsp__regs__t">&#9670;&#160;</a></span>sp_regs_t</h2>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">struct sp_regs_t</td>
</tr>
</table>
</div><div class="memdoc">
<div class="textblock"></div><table class="fieldtable">
<tr><th colspan="3">Data Fields</th></tr>
<tr><td class="fieldtype">
<a id="ae7d837b8be7b32681c1004e945362163" name="ae7d837b8be7b32681c1004e945362163"></a>io32_t</td>
<td class="fieldname">
PADDR</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="aa42ea35ffb72f598580d2c2f2c539a5e" name="aa42ea35ffb72f598580d2c2f2c539a5e"></a>io32_t</td>
<td class="fieldname">
MADDR</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a7385f69dad65c3a23b0600923035f236" name="a7385f69dad65c3a23b0600923035f236"></a>io32_t</td>
<td class="fieldname">
RD_LEN</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a466044cbe77c530da1a893157d3f8d16" name="a466044cbe77c530da1a893157d3f8d16"></a>io32_t</td>
<td class="fieldname">
WR_LEN</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a04ee6c089b5bbab732bf3ac352dfff40" name="a04ee6c089b5bbab732bf3ac352dfff40"></a>io32_t</td>
<td class="fieldname">
SR</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a26b0fb4a2456b7f14a6c8eea80018823" name="a26b0fb4a2456b7f14a6c8eea80018823"></a>io32_t</td>
<td class="fieldname">
DMA_FULL</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a643213e3225fae5460f54c5dadc1a2d2" name="a643213e3225fae5460f54c5dadc1a2d2"></a>io32_t</td>
<td class="fieldname">
DMA_BUSY</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="adf0065c2e5ac765fc1b20fd733ba5d7b" name="adf0065c2e5ac765fc1b20fd733ba5d7b"></a>io32_t</td>
<td class="fieldname">
SEMAPHORE</td>
<td class="fielddoc">
</td></tr>
</table>
</div>
</div>
<a name="structdpc__regs__t" id="structdpc__regs__t"></a>
<h2 class="memtitle"><span class="permalink"><a href="#structdpc__regs__t">&#9670;&#160;</a></span>dpc_regs_t</h2>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">struct dpc_regs_t</td>
</tr>
</table>
</div><div class="memdoc">
<div class="textblock"><p >DPC Registers Structure. </p>
</div><table class="fieldtable">
<tr><th colspan="3">Data Fields</th></tr>
<tr><td class="fieldtype">
<a id="a23c61fcf584e98d4593c8b45dab8498a" name="a23c61fcf584e98d4593c8b45dab8498a"></a>io32_t</td>
<td class="fieldname">
START</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="ac211d738f5a6bce56ddfb3c215d5cc98" name="ac211d738f5a6bce56ddfb3c215d5cc98"></a>io32_t</td>
<td class="fieldname">
END</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a3d374c4bec049d42ab0e986f290511cc" name="a3d374c4bec049d42ab0e986f290511cc"></a>io32_t</td>
<td class="fieldname">
CURRENT</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="ab46bc9d0ff31e386a39e03bdfd199c4c" name="ab46bc9d0ff31e386a39e03bdfd199c4c"></a>io32_t</td>
<td class="fieldname">
SR</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="ad3b67aa0f79eb5da38748feff7f7cf34" name="ad3b67aa0f79eb5da38748feff7f7cf34"></a>io32_t</td>
<td class="fieldname">
CLOCK</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="add46d8fc540c7ae8d608d0a80ba2f0e4" name="add46d8fc540c7ae8d608d0a80ba2f0e4"></a>io32_t</td>
<td class="fieldname">
BUF_BUSY</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="aa1709fd6a872cee8824310647a6ee1f6" name="aa1709fd6a872cee8824310647a6ee1f6"></a>io32_t</td>
<td class="fieldname">
PIPE_BUSY</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a6c547306d8e6e87c2521481a26bebe77" name="a6c547306d8e6e87c2521481a26bebe77"></a>io32_t</td>
<td class="fieldname">
TMEM</td>
<td class="fielddoc">
</td></tr>
</table>
</div>
</div>
<a name="structvi__regs__t" id="structvi__regs__t"></a>
<h2 class="memtitle"><span class="permalink"><a href="#structvi__regs__t">&#9670;&#160;</a></span>vi_regs_t</h2>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">struct vi_regs_t</td>
</tr>
</table>
</div><div class="memdoc">
<div class="textblock"><p >Video Interface Registers Structure. </p>
</div><table class="fieldtable">
<tr><th colspan="3">Data Fields</th></tr>
<tr><td class="fieldtype">
<a id="acb0559579506d3949f0b35d39d98156a" name="acb0559579506d3949f0b35d39d98156a"></a>io32_t</td>
<td class="fieldname">
CR</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="afddfa288e765993552f0b0b9e5091abd" name="afddfa288e765993552f0b0b9e5091abd"></a>io32_t</td>
<td class="fieldname">
MADDR</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="af2521492273c60801fa69449d73487a9" name="af2521492273c60801fa69449d73487a9"></a>io32_t</td>
<td class="fieldname">
H_WIDTH</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="af3a2374353eaa0de3c38607693057cfa" name="af3a2374353eaa0de3c38607693057cfa"></a>io32_t</td>
<td class="fieldname">
V_INTR</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a16300cb685dffb0761649b885f36eeb3" name="a16300cb685dffb0761649b885f36eeb3"></a>io32_t</td>
<td class="fieldname">
CURR_LINE</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a62ad61417eb98ddc6ad522b566f4667d" name="a62ad61417eb98ddc6ad522b566f4667d"></a>io32_t</td>
<td class="fieldname">
TIMING</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="ac7797f5ba82e82db9cda5c459a8a7cea" name="ac7797f5ba82e82db9cda5c459a8a7cea"></a>io32_t</td>
<td class="fieldname">
V_SYNC</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a68c8e1537ebc5243d5b6bb773fe479ad" name="a68c8e1537ebc5243d5b6bb773fe479ad"></a>io32_t</td>
<td class="fieldname">
H_SYNC</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="ab76316a7a5c429c53d97eff274b99747" name="ab76316a7a5c429c53d97eff274b99747"></a>io32_t</td>
<td class="fieldname">
H_SYNC_LEAP</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="aa0297b871dc42976d5fefe87d136833b" name="aa0297b871dc42976d5fefe87d136833b"></a>io32_t</td>
<td class="fieldname">
H_LIMITS</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a8a17677bc1236677903d6312d64b73b8" name="a8a17677bc1236677903d6312d64b73b8"></a>io32_t</td>
<td class="fieldname">
V_LIMITS</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="ac2f4fd1da8557ce8056df383b8c1da22" name="ac2f4fd1da8557ce8056df383b8c1da22"></a>io32_t</td>
<td class="fieldname">
COLOR_BURST</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="abe25faca08f96d7d92585b9686fa647f" name="abe25faca08f96d7d92585b9686fa647f"></a>io32_t</td>
<td class="fieldname">
H_SCALE</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="ad640b8c4be56e5e183f09f78368e2328" name="ad640b8c4be56e5e183f09f78368e2328"></a>io32_t</td>
<td class="fieldname">
V_SCALE</td>
<td class="fielddoc">
</td></tr>
</table>
</div>
</div>
<a name="structai__regs__t" id="structai__regs__t"></a>
<h2 class="memtitle"><span class="permalink"><a href="#structai__regs__t">&#9670;&#160;</a></span>ai_regs_t</h2>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">struct ai_regs_t</td>
</tr>
</table>
</div><div class="memdoc">
<div class="textblock"></div><table class="fieldtable">
<tr><th colspan="3">Data Fields</th></tr>
<tr><td class="fieldtype">
<a id="ad7040a2f3fa50a932cb1d3328784ebb4" name="ad7040a2f3fa50a932cb1d3328784ebb4"></a>io32_t</td>
<td class="fieldname">
MADDR</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="ac0676d4e820604efc8b5414be5d39f18" name="ac0676d4e820604efc8b5414be5d39f18"></a>io32_t</td>
<td class="fieldname">
LEN</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="ad443725846fa9e299773a8f57b357c73" name="ad443725846fa9e299773a8f57b357c73"></a>io32_t</td>
<td class="fieldname">
CR</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a8b1251e120efe26718d3394aec73ca0c" name="a8b1251e120efe26718d3394aec73ca0c"></a>io32_t</td>
<td class="fieldname">
SR</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a05b74719e0eb214f19d2aca062baa57d" name="a05b74719e0eb214f19d2aca062baa57d"></a>io32_t</td>
<td class="fieldname">
DACRATE</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a43e0411e186298f185d39b80ea5f1d4f" name="a43e0411e186298f185d39b80ea5f1d4f"></a>io32_t</td>
<td class="fieldname">
BITRATE</td>
<td class="fielddoc">
</td></tr>
</table>
</div>
</div>
<a name="structpi__regs__t" id="structpi__regs__t"></a>
<h2 class="memtitle"><span class="permalink"><a href="#structpi__regs__t">&#9670;&#160;</a></span>pi_regs_t</h2>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">struct pi_regs_t</td>
</tr>
</table>
</div><div class="memdoc">
<div class="textblock"><p >Parallel Interface Register Structure. </p>
</div><table class="fieldtable">
<tr><th colspan="3">Data Fields</th></tr>
<tr><td class="fieldtype">
<a id="aa9504bae7269bf8facd720b4ac2d2c00" name="aa9504bae7269bf8facd720b4ac2d2c00"></a>io32_t</td>
<td class="fieldname">
MADDR</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a39dcd01f99c2ca546737cff58821a43d" name="a39dcd01f99c2ca546737cff58821a43d"></a>io32_t</td>
<td class="fieldname">
PADDR</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a6d04dc1568e8bec29264bc9a8c2e7724" name="a6d04dc1568e8bec29264bc9a8c2e7724"></a>io32_t</td>
<td class="fieldname">
RDMA</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a73468640d22e6304e6a07d5ab81a0efa" name="a73468640d22e6304e6a07d5ab81a0efa"></a>io32_t</td>
<td class="fieldname">
WDMA</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a6c4f19758b5239f5239f490a6be98262" name="a6c4f19758b5239f5239f490a6be98262"></a>io32_t</td>
<td class="fieldname">
SR</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a378681355d279b47c38f6715cfa764d9" name="a378681355d279b47c38f6715cfa764d9"></a>struct <a class="el" href="boot__io_8h.html#structpi__regs__t_8DOM">pi_regs_t.DOM</a></td>
<td class="fieldname">
DOM[2]</td>
<td class="fielddoc">
</td></tr>
</table>
</div>
</div>
<a name="structos__info__t" id="structos__info__t"></a>
<h2 class="memtitle"><span class="permalink"><a href="#structos__info__t">&#9670;&#160;</a></span>os_info_t</h2>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">struct os_info_t</td>
</tr>
</table>
</div><div class="memdoc">
<div class="textblock"></div><table class="fieldtable">
<tr><th colspan="3">Data Fields</th></tr>
<tr><td class="fieldtype">
<a id="a6455bcb3e612857ce81e65458d972d56" name="a6455bcb3e612857ce81e65458d972d56"></a>uint32_t</td>
<td class="fieldname">
tv_type</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a482d62e2efc49914fa0de486a900a466" name="a482d62e2efc49914fa0de486a900a466"></a>uint32_t</td>
<td class="fieldname">
device_type</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a40a6bca470f4f95125b8c8be80af7ea7" name="a40a6bca470f4f95125b8c8be80af7ea7"></a>uint32_t</td>
<td class="fieldname">
device_base</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a66fb65eed0574de7a4d7d8f56b32f85e" name="a66fb65eed0574de7a4d7d8f56b32f85e"></a>uint32_t</td>
<td class="fieldname">
reset_type</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="ae410fc30a4b0b526c3a59708f91838ae" name="ae410fc30a4b0b526c3a59708f91838ae"></a>uint32_t</td>
<td class="fieldname">
cic_id</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a009741d63f2a583dced5eb2336882067" name="a009741d63f2a583dced5eb2336882067"></a>uint32_t</td>
<td class="fieldname">
version</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="aa03cf4d9df48e68af54400afd9758d20" name="aa03cf4d9df48e68af54400afd9758d20"></a>uint32_t</td>
<td class="fieldname">
mem_size</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a7c097460afce5a38725b9e7ebf882eb9" name="a7c097460afce5a38725b9e7ebf882eb9"></a>uint8_t</td>
<td class="fieldname">
app_nmi_buffer[64]</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a162ac112d5d47fe70abe55df773bd002" name="a162ac112d5d47fe70abe55df773bd002"></a>uint32_t</td>
<td class="fieldname">
__reserved_1[37]</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a3c6702baa8e793a35080662bf77f0ff7" name="a3c6702baa8e793a35080662bf77f0ff7"></a>uint32_t</td>
<td class="fieldname">
mem_size_6105</td>
<td class="fielddoc">
</td></tr>
</table>
</div>
</div>
<a name="structpi__regs__t_8DOM" id="structpi__regs__t_8DOM"></a>
<h2 class="memtitle"><span class="permalink"><a href="#structpi__regs__t_8DOM">&#9670;&#160;</a></span>pi_regs_t.DOM</h2>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">struct pi_regs_t.DOM</td>
</tr>
</table>
</div><div class="memdoc">
<div class="textblock"></div><table class="fieldtable">
<tr><th colspan="3">Data Fields</th></tr>
<tr><td class="fieldtype">
<a id="ac4a8afa234be2060691c81928eb1b701" name="ac4a8afa234be2060691c81928eb1b701"></a>io32_t</td>
<td class="fieldname">
LAT</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a0d35c1f17675a8a2bf3caaacd59a65de" name="a0d35c1f17675a8a2bf3caaacd59a65de"></a>io32_t</td>
<td class="fieldname">
PWD</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a27eb8b9c1e2bbaa238edca6206308db0" name="a27eb8b9c1e2bbaa238edca6206308db0"></a>io32_t</td>
<td class="fieldname">
PGS</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="acc7f332850e8e9c1d0003ab4126c71e1" name="acc7f332850e8e9c1d0003ab4126c71e1"></a>io32_t</td>
<td class="fieldname">
RLS</td>
<td class="fielddoc">
</td></tr>
</table>
</div>
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