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fix

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This commit is contained in:
ariahiro64 2023-10-16 23:09:48 -04:00
parent dfc0a92013
commit 075a204a82
3 changed files with 61 additions and 60 deletions
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18
src/flashcart/ed64/ed64.c
View File

@ -65,7 +65,7 @@ static flashcart_err_t ed64_init (void) {
return FLASHCART_ERR_LOAD; return FLASHCART_ERR_LOAD;
} }
// everdrive doesnt care about the save type other than eeprom // everdrive doesn't care about the save type other than eeprom
// so we can just check the size // so we can just check the size
if (save_size > KiB(2)) { if (save_size > KiB(2)) {
@ -197,7 +197,7 @@ static flashcart_err_t ed64_load_save (char *save_path) {
return FLASHCART_ERR_LOAD; return FLASHCART_ERR_LOAD;
} }
size_t save_size = f_size(&fil); size_t save_size = file_get_size(strip_sd_prefix(save_path));
uint8_t cartsave_data[save_size]; uint8_t cartsave_data[save_size];
if (f_read(&fil, cartsave_data, save_size, &br) != FR_OK) { if (f_read(&fil, cartsave_data, save_size, &br) != FR_OK) {
@ -214,16 +214,15 @@ static flashcart_err_t ed64_load_save (char *save_path) {
if (save_size >= KiB(32)) { //sram and flash if (save_size >= KiB(32)) { //sram and flash
setSRAM(cartsave_data, save_size); setSRAM(cartsave_data, save_size);
} else if (save_size >= 512){ // eeprom }
else if (save_size >= 512){ // eeprom
setEeprom(cartsave_data, save_size); setEeprom(cartsave_data, save_size);
} }
FIL lsp_fil; FIL lsp_fil;
UINT lsp_bw; UINT lsp_bw;
// probably not nessacery
f_unlink(LAST_SAVE_FILE_PATH);
if (f_open(&lsp_fil, LAST_SAVE_FILE_PATH, FA_WRITE | FA_CREATE_ALWAYS) != FR_OK) { if (f_open(&lsp_fil, LAST_SAVE_FILE_PATH, FA_WRITE | FA_CREATE_ALWAYS) != FR_OK) {
return FLASHCART_ERR_LOAD; return FLASHCART_ERR_LOAD;
} }
@ -237,8 +236,6 @@ static flashcart_err_t ed64_load_save (char *save_path) {
} }
FIL rsfil; FIL rsfil;
UINT rsbr;
TCHAR reset_byte[1];
// this wries a 1 byte file as it only needs to exist to detect a reset // this wries a 1 byte file as it only needs to exist to detect a reset
@ -247,11 +244,6 @@ static flashcart_err_t ed64_load_save (char *save_path) {
return FLASHCART_ERR_LOAD; return FLASHCART_ERR_LOAD;
} }
if (f_write(&rsfil, (void *)reset_byte, 1, &rsbr) != FR_OK) {
f_close(&rsfil);
return FLASHCART_ERR_LOAD;
}
if (f_close(&rsfil) != FR_OK) { if (f_close(&rsfil) != FR_OK) {
return FLASHCART_OK; return FLASHCART_OK;
} }

91
src/flashcart/ed64/ed64_ll.c
View File

@ -119,32 +119,33 @@ void ed64_ll_set_sram_bank(uint8_t bank) {
void PI_Init(void) { void PI_Init(void) {
PI_DMAWait(); PI_DMAWait();
io_write(PI_STATUS_REG, 0x03); IO_WRITE(PI_STATUS_REG, 0x03);
} }
// Inits PI for sram transfer // Inits PI for sram transfer
void PI_Init_SRAM(void) { void PI_Init_SRAM(void) {
io_write(PI_BSD_DOM2_LAT_REG, 0x05); IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05);
io_write(PI_BSD_DOM2_PWD_REG, 0x0C); IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C);
io_write(PI_BSD_DOM2_PGS_REG, 0x0D); IO_WRITE(PI_BSD_DOM2_PGS_REG, 0x0D);
io_write(PI_BSD_DOM2_RLS_REG, 0x02); IO_WRITE(PI_BSD_DOM2_RLS_REG, 0x02);
} }
void PI_DMAWait(void) { void PI_DMAWait(void) {
while (io_read(PI_STATUS_REG) & (SP_STATUS_IO_BUSY | SP_STATUS_DMA_BUSY)); while (IO_READ(PI_STATUS_REG) & (PI_STATUS_IO_BUSY | PI_STATUS_DMA_BUSY));
} }
void PI_DMAFromSRAM(void *dest, unsigned long offset, unsigned long size) { void PI_DMAFromSRAM(void *dest, unsigned long offset, unsigned long size) {
io_write(PI_DRAM_ADDR_REG, K1_TO_PHYS(dest)); IO_WRITE(PI_DRAM_ADDR_REG, K1_TO_PHYS(dest));
io_write(PI_CART_ADDR_REG, (0xA8000000 + offset)); IO_WRITE(PI_CART_ADDR_REG, (0xA8000000 + offset));
asm volatile ("" : : : "memory"); asm volatile ("" : : : "memory");
io_write(PI_WR_LEN_REG, (size - 1)); IO_WRITE(PI_WR_LEN_REG, (size - 1));
asm volatile ("" : : : "memory"); asm volatile ("" : : : "memory");
} }
@ -153,29 +154,29 @@ void PI_DMAFromSRAM(void *dest, unsigned long offset, unsigned long size) {
void PI_DMAToSRAM(void *src, unsigned long offset, unsigned long size) { //void* void PI_DMAToSRAM(void *src, unsigned long offset, unsigned long size) { //void*
PI_DMAWait(); PI_DMAWait();
io_write(PI_STATUS_REG, 2); IO_WRITE(PI_STATUS_REG, 2);
io_write(PI_DRAM_ADDR_REG, K1_TO_PHYS(src)); IO_WRITE(PI_DRAM_ADDR_REG, K1_TO_PHYS(src));
io_write(PI_CART_ADDR_REG, (0xA8000000 + offset)); IO_WRITE(PI_CART_ADDR_REG, (0xA8000000 + offset));
io_write(PI_RD_LEN_REG, (size - 1)); IO_WRITE(PI_RD_LEN_REG, (size - 1));
} }
void PI_DMAFromCart(void* dest, void* src, unsigned long size) { void PI_DMAFromCart(void* dest, void* src, unsigned long size) {
PI_DMAWait(); PI_DMAWait();
io_write(PI_STATUS_REG, 0x03); IO_WRITE(PI_STATUS_REG, 0x03);
io_write(PI_DRAM_ADDR_REG, K1_TO_PHYS(dest)); IO_WRITE(PI_DRAM_ADDR_REG, K1_TO_PHYS(dest));
io_write(PI_CART_ADDR_REG, K0_TO_PHYS(src)); IO_WRITE(PI_CART_ADDR_REG, K0_TO_PHYS(src));
io_write(PI_WR_LEN_REG, (size - 1)); IO_WRITE(PI_WR_LEN_REG, (size - 1));
} }
void PI_DMAToCart(void* dest, void* src, unsigned long size) { void PI_DMAToCart(void* dest, void* src, unsigned long size) {
PI_DMAWait(); PI_DMAWait();
io_write(PI_STATUS_REG, 0x02); IO_WRITE(PI_STATUS_REG, 0x02);
io_write(PI_DRAM_ADDR_REG, K1_TO_PHYS(src)); IO_WRITE(PI_DRAM_ADDR_REG, K1_TO_PHYS(src));
io_write(PI_CART_ADDR_REG, K0_TO_PHYS(dest)); IO_WRITE(PI_CART_ADDR_REG, K0_TO_PHYS(dest));
io_write(PI_RD_LEN_REG, (size - 1)); IO_WRITE(PI_RD_LEN_REG, (size - 1));
} }
@ -210,10 +211,10 @@ void PI_SafeDMAFromCart(void *dest, void *src, unsigned long size) {
int getSRAM( uint8_t *buffer, int size){ int getSRAM( uint8_t *buffer, int size){
dma_wait(); dma_wait();
io_write(PI_BSD_DOM2_LAT_REG, 0x05); IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05);
io_write(PI_BSD_DOM2_PWD_REG, 0x0C); IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C);
io_write(PI_BSD_DOM2_PGS_REG, 0x0D); IO_WRITE(PI_BSD_DOM2_PGS_REG, 0x0D);
io_write(PI_BSD_DOM2_RLS_REG, 0x02); IO_WRITE(PI_BSD_DOM2_RLS_REG, 0x02);
dma_wait(); dma_wait();
@ -225,10 +226,10 @@ int getSRAM( uint8_t *buffer, int size){
dma_wait(); dma_wait();
io_write(PI_BSD_DOM2_LAT_REG, 0x40); IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x40);
io_write(PI_BSD_DOM2_PWD_REG, 0x12); IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x12);
io_write(PI_BSD_DOM2_PGS_REG, 0x07); IO_WRITE(PI_BSD_DOM2_PGS_REG, 0x07);
io_write(PI_BSD_DOM2_RLS_REG, 0x03); IO_WRITE(PI_BSD_DOM2_RLS_REG, 0x03);
return 1; return 1;
} }
@ -281,27 +282,27 @@ int setEeprom(uint8_t *buffer, int size){
void setSDTiming(void){ void setSDTiming(void){
// PI_DMAWait(); // PI_DMAWait();
io_write(PI_BSD_DOM1_LAT_REG, 0x40); IO_WRITE(PI_BSD_DOM1_LAT_REG, 0x40);
io_write(PI_BSD_DOM1_PWD_REG, 0x12); IO_WRITE(PI_BSD_DOM1_PWD_REG, 0x12);
io_write(PI_BSD_DOM1_PGS_REG, 0x07); IO_WRITE(PI_BSD_DOM1_PGS_REG, 0x07);
io_write(PI_BSD_DOM1_RLS_REG, 0x03); IO_WRITE(PI_BSD_DOM1_RLS_REG, 0x03);
io_write(PI_BSD_DOM2_LAT_REG, 0x40); IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x40);
io_write(PI_BSD_DOM2_PWD_REG, 0x12); IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x12);
io_write(PI_BSD_DOM2_PGS_REG, 0x07); IO_WRITE(PI_BSD_DOM2_PGS_REG, 0x07);
io_write(PI_BSD_DOM2_RLS_REG, 0x03); IO_WRITE(PI_BSD_DOM2_RLS_REG, 0x03);
} }
void restoreTiming(void) { void restoreTiming(void) {
//n64 timing restore :> //n64 timing restore :>
io_write(PI_BSD_DOM1_LAT_REG, 0x40); IO_WRITE(PI_BSD_DOM1_LAT_REG, 0x40);
io_write(PI_BSD_DOM1_PWD_REG, 0x12); IO_WRITE(PI_BSD_DOM1_PWD_REG, 0x12);
io_write(PI_BSD_DOM1_PGS_REG, 0x07); IO_WRITE(PI_BSD_DOM1_PGS_REG, 0x07);
io_write(PI_BSD_DOM1_RLS_REG, 0x03); IO_WRITE(PI_BSD_DOM1_RLS_REG, 0x03);
io_write(PI_BSD_DOM2_LAT_REG, 0x40); IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x40);
io_write(PI_BSD_DOM2_PWD_REG, 0x12); IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x12);
io_write(PI_BSD_DOM2_PGS_REG, 0x07); IO_WRITE(PI_BSD_DOM2_PGS_REG, 0x07);
io_write(PI_BSD_DOM2_RLS_REG, 0x03); IO_WRITE(PI_BSD_DOM2_RLS_REG, 0x03);
} }

8
src/flashcart/ed64/ed64_ll.h
View File

@ -14,8 +14,14 @@
// FIXME: redefined because its in a .c instead of a .h // FIXME: redefined because its in a .c instead of a .h
#define PI_BASE_REG 0x04600000 #define PI_BASE_REG 0x04600000
#define IO_READ(addr) (*(volatile uint32_t *)PHYS_TO_K1(addr))
#define IO_WRITE(addr,data) \
(*(volatile uint32_t *)PHYS_TO_K1(addr) = (uint32_t)(data))
#define PIF_RAM_START 0x1FC007C0 #define PIF_RAM_START 0x1FC007C0
#define PI_STATUS_ERROR 0x04
#define PI_STATUS_IO_BUSY 0x02
#define PI_STATUS_DMA_BUSY 0x01
#define PI_STATUS_REG (PI_BASE_REG+0x10) #define PI_STATUS_REG (PI_BASE_REG+0x10)
#define PI_DRAM_ADDR_REG (PI_BASE_REG+0x00) /* DRAM address */ #define PI_DRAM_ADDR_REG (PI_BASE_REG+0x00) /* DRAM address */
@ -33,7 +39,9 @@
#define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) #define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C)
#define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) #define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30)
#define PHYS_TO_K0(x) ((unsigned long)(x)|0x80000000) /* physical to kseg0 */
#define K0_TO_PHYS(x) ((unsigned long)(x)&0x1FFFFFFF) /* kseg0 to physical */ #define K0_TO_PHYS(x) ((unsigned long)(x)&0x1FFFFFFF) /* kseg0 to physical */
#define PHYS_TO_K1(x) ((unsigned long)(x)|0xA0000000) /* physical to kseg1 */
#define K1_TO_PHYS(x) ((unsigned long)(x)&0x1FFFFFFF) /* kseg1 to physical */ #define K1_TO_PHYS(x) ((unsigned long)(x)&0x1FFFFFFF) /* kseg1 to physical */