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flash ram fixed

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This commit is contained in:
ariahiro64 2023-10-17 07:32:48 -04:00
parent 075a204a82
commit 35e4727c16
4 changed files with 84 additions and 49 deletions
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11
src/flashcart/ed64/ed64.c
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@ -67,8 +67,9 @@ static flashcart_err_t ed64_init (void) {
// everdrive doesn't care about the save type other than eeprom // everdrive doesn't care about the save type other than eeprom
// so we can just check the size // so we can just check the size
if (save_size == KiB(128)) {
if (save_size > KiB(2)) { getFlashRAM(cartsave_data, save_size);
} else if (save_size > KiB(2)) {
getSRAM(cartsave_data, save_size); getSRAM(cartsave_data, save_size);
} else { } else {
getEeprom(cartsave_data, save_size); getEeprom(cartsave_data, save_size);
@ -212,7 +213,11 @@ static flashcart_err_t ed64_load_save (char *save_path) {
// everdrive doesnt care about the save type other than eeprom // everdrive doesnt care about the save type other than eeprom
// so we can just check the size // so we can just check the size
if (save_size >= KiB(32)) { //sram and flash if (save_size == KiB(128)) { //sram 128 and flash
setFlashRAM(cartsave_data, save_size);
}
else if (save_size > KiB(2)) { //sram
setSRAM(cartsave_data, save_size); setSRAM(cartsave_data, save_size);
} }

117
src/flashcart/ed64/ed64_ll.c
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@ -119,22 +119,22 @@ void ed64_ll_set_sram_bank(uint8_t bank) {
void PI_Init(void) { void PI_Init(void) {
PI_DMAWait(); PI_DMAWait();
IO_WRITE(PI_STATUS_REG, 0x03); io_write(PI_STATUS_REG, 0x03);
} }
// Inits PI for sram transfer // Inits PI for sram transfer
void PI_Init_SRAM(void) { void PI_Init_SRAM(void) {
IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05); io_write(PI_BSD_DOM2_LAT_REG, 0x05);
IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C); io_write(PI_BSD_DOM2_PWD_REG, 0x0C);
IO_WRITE(PI_BSD_DOM2_PGS_REG, 0x0D); io_write(PI_BSD_DOM2_PGS_REG, 0x0D);
IO_WRITE(PI_BSD_DOM2_RLS_REG, 0x02); io_write(PI_BSD_DOM2_RLS_REG, 0x02);
} }
void PI_DMAWait(void) { void PI_DMAWait(void) {
while (IO_READ(PI_STATUS_REG) & (PI_STATUS_IO_BUSY | PI_STATUS_DMA_BUSY)); while (io_read(PI_STATUS_REG) & (PI_STATUS_IO_BUSY | PI_STATUS_DMA_BUSY));
} }
@ -142,10 +142,10 @@ void PI_DMAWait(void) {
void PI_DMAFromSRAM(void *dest, unsigned long offset, unsigned long size) { void PI_DMAFromSRAM(void *dest, unsigned long offset, unsigned long size) {
IO_WRITE(PI_DRAM_ADDR_REG, K1_TO_PHYS(dest)); io_write(PI_DRAM_ADDR_REG, K1_TO_PHYS(dest));
IO_WRITE(PI_CART_ADDR_REG, (0xA8000000 + offset)); io_write(PI_CART_ADDR_REG, (0xA8000000 + offset));
asm volatile ("" : : : "memory"); asm volatile ("" : : : "memory");
IO_WRITE(PI_WR_LEN_REG, (size - 1)); io_write(PI_WR_LEN_REG, (size - 1));
asm volatile ("" : : : "memory"); asm volatile ("" : : : "memory");
} }
@ -154,29 +154,29 @@ void PI_DMAFromSRAM(void *dest, unsigned long offset, unsigned long size) {
void PI_DMAToSRAM(void *src, unsigned long offset, unsigned long size) { //void* void PI_DMAToSRAM(void *src, unsigned long offset, unsigned long size) { //void*
PI_DMAWait(); PI_DMAWait();
IO_WRITE(PI_STATUS_REG, 2); io_write(PI_STATUS_REG, 2);
IO_WRITE(PI_DRAM_ADDR_REG, K1_TO_PHYS(src)); io_write(PI_DRAM_ADDR_REG, K1_TO_PHYS(src));
IO_WRITE(PI_CART_ADDR_REG, (0xA8000000 + offset)); io_write(PI_CART_ADDR_REG, (0xA8000000 + offset));
IO_WRITE(PI_RD_LEN_REG, (size - 1)); io_write(PI_RD_LEN_REG, (size - 1));
} }
void PI_DMAFromCart(void* dest, void* src, unsigned long size) { void PI_DMAFromCart(void* dest, void* src, unsigned long size) {
PI_DMAWait(); PI_DMAWait();
IO_WRITE(PI_STATUS_REG, 0x03); io_write(PI_STATUS_REG, 0x03);
IO_WRITE(PI_DRAM_ADDR_REG, K1_TO_PHYS(dest)); io_write(PI_DRAM_ADDR_REG, K1_TO_PHYS(dest));
IO_WRITE(PI_CART_ADDR_REG, K0_TO_PHYS(src)); io_write(PI_CART_ADDR_REG, K0_TO_PHYS(src));
IO_WRITE(PI_WR_LEN_REG, (size - 1)); io_write(PI_WR_LEN_REG, (size - 1));
} }
void PI_DMAToCart(void* dest, void* src, unsigned long size) { void PI_DMAToCart(void* dest, void* src, unsigned long size) {
PI_DMAWait(); PI_DMAWait();
IO_WRITE(PI_STATUS_REG, 0x02); io_write(PI_STATUS_REG, 0x02);
IO_WRITE(PI_DRAM_ADDR_REG, K1_TO_PHYS(src)); io_write(PI_DRAM_ADDR_REG, K1_TO_PHYS(src));
IO_WRITE(PI_CART_ADDR_REG, K0_TO_PHYS(dest)); io_write(PI_CART_ADDR_REG, K0_TO_PHYS(dest));
IO_WRITE(PI_RD_LEN_REG, (size - 1)); io_write(PI_RD_LEN_REG, (size - 1));
} }
@ -211,10 +211,10 @@ void PI_SafeDMAFromCart(void *dest, void *src, unsigned long size) {
int getSRAM( uint8_t *buffer, int size){ int getSRAM( uint8_t *buffer, int size){
dma_wait(); dma_wait();
IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05); io_write(PI_BSD_DOM2_LAT_REG, 0x05);
IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C); io_write(PI_BSD_DOM2_PWD_REG, 0x0C);
IO_WRITE(PI_BSD_DOM2_PGS_REG, 0x0D); io_write(PI_BSD_DOM2_PGS_REG, 0x0D);
IO_WRITE(PI_BSD_DOM2_RLS_REG, 0x02); io_write(PI_BSD_DOM2_RLS_REG, 0x02);
dma_wait(); dma_wait();
@ -226,10 +226,10 @@ int getSRAM( uint8_t *buffer, int size){
dma_wait(); dma_wait();
IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x40); io_write(PI_BSD_DOM2_LAT_REG, 0x40);
IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x12); io_write(PI_BSD_DOM2_PWD_REG, 0x12);
IO_WRITE(PI_BSD_DOM2_PGS_REG, 0x07); io_write(PI_BSD_DOM2_PGS_REG, 0x07);
IO_WRITE(PI_BSD_DOM2_RLS_REG, 0x03); io_write(PI_BSD_DOM2_RLS_REG, 0x03);
return 1; return 1;
} }
@ -244,6 +244,19 @@ int getEeprom( uint8_t *buffer, int size){
} }
int getFlashRAM( uint8_t *buffer, int size){
ed64_ll_set_save_type(SAVE_TYPE_SRAM_128K); //2
PI_DMAWait();
getSRAM(buffer, size);
data_cache_hit_writeback_invalidate(buffer, size);
PI_DMAWait();
ed64_ll_set_save_type(SAVE_TYPE_FLASHRAM);
return 1;
}
/* /*
sram upload sram upload
*/ */
@ -279,30 +292,44 @@ int setEeprom(uint8_t *buffer, int size){
return 1; return 1;
} }
int setFlashRAM(uint8_t *buffer, int size){
ed64_ll_set_save_type(SAVE_TYPE_SRAM_128K); //2
PI_DMAWait();
setSRAM(buffer, size);
data_cache_hit_writeback_invalidate(buffer, size);
PI_DMAWait();
ed64_ll_set_save_type(SAVE_TYPE_FLASHRAM);
return 1;
}
void setSDTiming(void){ void setSDTiming(void){
// PI_DMAWait(); // PI_DMAWait();
IO_WRITE(PI_BSD_DOM1_LAT_REG, 0x40); io_write(PI_BSD_DOM1_LAT_REG, 0x40);
IO_WRITE(PI_BSD_DOM1_PWD_REG, 0x12); io_write(PI_BSD_DOM1_PWD_REG, 0x12);
IO_WRITE(PI_BSD_DOM1_PGS_REG, 0x07); io_write(PI_BSD_DOM1_PGS_REG, 0x07);
IO_WRITE(PI_BSD_DOM1_RLS_REG, 0x03); io_write(PI_BSD_DOM1_RLS_REG, 0x03);
IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x40); io_write(PI_BSD_DOM2_LAT_REG, 0x40);
IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x12); io_write(PI_BSD_DOM2_PWD_REG, 0x12);
IO_WRITE(PI_BSD_DOM2_PGS_REG, 0x07); io_write(PI_BSD_DOM2_PGS_REG, 0x07);
IO_WRITE(PI_BSD_DOM2_RLS_REG, 0x03); io_write(PI_BSD_DOM2_RLS_REG, 0x03);
} }
void restoreTiming(void) { void restoreTiming(void) {
//n64 timing restore :> //n64 timing restore :>
IO_WRITE(PI_BSD_DOM1_LAT_REG, 0x40); io_write(PI_BSD_DOM1_LAT_REG, 0x40);
IO_WRITE(PI_BSD_DOM1_PWD_REG, 0x12); io_write(PI_BSD_DOM1_PWD_REG, 0x12);
IO_WRITE(PI_BSD_DOM1_PGS_REG, 0x07); io_write(PI_BSD_DOM1_PGS_REG, 0x07);
IO_WRITE(PI_BSD_DOM1_RLS_REG, 0x03); io_write(PI_BSD_DOM1_RLS_REG, 0x03);
IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x40); io_write(PI_BSD_DOM2_LAT_REG, 0x40);
IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x12); io_write(PI_BSD_DOM2_PWD_REG, 0x12);
IO_WRITE(PI_BSD_DOM2_PGS_REG, 0x07); io_write(PI_BSD_DOM2_PGS_REG, 0x07);
IO_WRITE(PI_BSD_DOM2_RLS_REG, 0x03); io_write(PI_BSD_DOM2_RLS_REG, 0x03);
} }

2
src/flashcart/ed64/ed64_ll.h
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@ -92,8 +92,10 @@ void PI_DMAToSRAM(void* src, unsigned long offset, unsigned long size);
void PI_SafeDMAFromCart(void *dest, void *src, unsigned long size); void PI_SafeDMAFromCart(void *dest, void *src, unsigned long size);
int getSRAM( uint8_t *buffer, int size); int getSRAM( uint8_t *buffer, int size);
int getEeprom( uint8_t *buffer, int size); int getEeprom( uint8_t *buffer, int size);
int getFlashRAM( uint8_t *buffer, int size);
int setSRAM( uint8_t *buffer, int size); int setSRAM( uint8_t *buffer, int size);
int setEeprom( uint8_t *buffer, int size); int setEeprom( uint8_t *buffer, int size);
int setFlashRAM( uint8_t *buffer, int size);
#endif #endif

1
src/menu/cart_load.c
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@ -1,5 +1,6 @@
#include <string.h> #include <string.h>
#include <libcart/cart.h>
#include <libdragon.h> #include <libdragon.h>
#include "cart_load.h" #include "cart_load.h"