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Polprzewodnikowy 2023-09-05 22:49:26 +00:00
parent f46521728c
commit 8503882098
77 changed files with 298 additions and 284 deletions
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2
actions_8h.html
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@ -95,7 +95,7 @@ void&#160;</td><td class="memItemRight" valign="bottom"><b>actions_update</b> (<
</div></div><!-- contents -->
<!-- start footer part -->
<hr class="footer"/><address class="footer"><small>
Generated on Mon Sep 4 2023 21:34:10 for N64FlashcartMenu by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.9.5
Generated on Tue Sep 5 2023 22:49:25 for N64FlashcartMenu by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.9.5
</small></address>
</body>
</html>

2
actions_8h_source.html
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@ -93,7 +93,7 @@ $(function() {
</div><!-- fragment --></div><!-- contents -->
<!-- start footer part -->
<hr class="footer"/><address class="footer"><small>
Generated on Mon Sep 4 2023 21:34:10 for N64FlashcartMenu by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.9.5
Generated on Tue Sep 5 2023 22:49:25 for N64FlashcartMenu by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.9.5
</small></address>
</body>
</html>

2
annotated.html
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@ -110,7 +110,7 @@ $(function() {
</div><!-- contents -->
<!-- start footer part -->
<hr class="footer"/><address class="footer"><small>
Generated on Mon Sep 4 2023 21:34:11 for N64FlashcartMenu by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.9.5
Generated on Tue Sep 5 2023 22:49:25 for N64FlashcartMenu by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.9.5
</small></address>
</body>
</html>

2
boot_8h.html
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@ -169,7 +169,7 @@ detect_cic_seed</td>
</div><!-- contents -->
<!-- start footer part -->
<hr class="footer"/><address class="footer"><small>
Generated on Mon Sep 4 2023 21:34:10 for N64FlashcartMenu by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.9.5
Generated on Tue Sep 5 2023 22:49:25 for N64FlashcartMenu by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.9.5
</small></address>
</body>
</html>

2
boot_8h_source.html
View File

@ -122,7 +122,7 @@ $(function() {
</div><!-- fragment --></div><!-- contents -->
<!-- start footer part -->
<hr class="footer"/><address class="footer"><small>
Generated on Mon Sep 4 2023 21:34:10 for N64FlashcartMenu by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.9.5
Generated on Tue Sep 5 2023 22:49:25 for N64FlashcartMenu by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.9.5
</small></address>
</body>
</html>

14
boot__io_8h.html
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@ -525,6 +525,18 @@ DMA_BUSY</td>
SEMAPHORE</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="a9125fe665ff921f5ffe85ba351ed1cf1" name="a9125fe665ff921f5ffe85ba351ed1cf1"></a>io32_t</td>
<td class="fieldname">
__reserved[0xFFF8]</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a id="ae7500c0fc961a504138f271254e32d4e" name="ae7500c0fc961a504138f271254e32d4e"></a>io32_t</td>
<td class="fieldname">
PC</td>
<td class="fielddoc">
</td></tr>
</table>
</div>
@ -925,7 +937,7 @@ RLS</td>
</div><!-- contents -->
<!-- start footer part -->
<hr class="footer"/><address class="footer"><small>
Generated on Mon Sep 4 2023 21:34:10 for N64FlashcartMenu by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.9.5
Generated on Tue Sep 5 2023 22:49:25 for N64FlashcartMenu by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.9.5
</small></address>
</body>
</html>

418
boot__io_8h_source.html
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@ -110,220 +110,222 @@ $(function() {
<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"> 37</span> io32_t DMA_FULL;</div>
<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"> 38</span> io32_t DMA_BUSY;</div>
<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"> 39</span> io32_t SEMAPHORE;</div>
<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"> 40</span>} <a class="code hl_struct" href="boot__io_8h.html#structsp__regs__t">sp_regs_t</a>;</div>
<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"> 41</span> </div>
<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"> 42</span><span class="preprocessor">#define SP_BASE (0x04040000UL)</span></div>
<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"> 43</span><span class="preprocessor">#define SP ((sp_regs_t *) SP_BASE)</span></div>
<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"> 44</span> </div>
<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"> 45</span><span class="preprocessor">#define SP_SR_HALT (1 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"> 46</span><span class="preprocessor">#define SP_SR_BROKE (1 &lt;&lt; 1)</span></div>
<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"> 47</span><span class="preprocessor">#define SP_SR_DMA_BUSY (1 &lt;&lt; 2)</span></div>
<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span><span class="preprocessor">#define SP_SR_DMA_FULL (1 &lt;&lt; 3)</span></div>
<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"> 49</span><span class="preprocessor">#define SP_SR_IO_FULL (1 &lt;&lt; 4)</span></div>
<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"> 50</span><span class="preprocessor">#define SP_SR_SSTEP (1 &lt;&lt; 5)</span></div>
<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"> 51</span><span class="preprocessor">#define SP_SR_INTR_BREAK (1 &lt;&lt; 6)</span></div>
<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span><span class="preprocessor">#define SP_SR_SIG0 (1 &lt;&lt; 7)</span></div>
<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span><span class="preprocessor">#define SP_SR_SIG1 (1 &lt;&lt; 8)</span></div>
<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span><span class="preprocessor">#define SP_SR_SIG2 (1 &lt;&lt; 9)</span></div>
<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"> 55</span><span class="preprocessor">#define SP_SR_SIG3 (1 &lt;&lt; 10)</span></div>
<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span><span class="preprocessor">#define SP_SR_SIG4 (1 &lt;&lt; 11)</span></div>
<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span><span class="preprocessor">#define SP_SR_SIG5 (1 &lt;&lt; 12)</span></div>
<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"> 58</span><span class="preprocessor">#define SP_SR_SIG6 (1 &lt;&lt; 13)</span></div>
<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span><span class="preprocessor">#define SP_SR_SIG7 (1 &lt;&lt; 14)</span></div>
<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"> 60</span><span class="preprocessor">#define SP_SR_CLR_HALT (1 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"> 61</span><span class="preprocessor">#define SP_SR_SET_HALT (1 &lt;&lt; 1)</span></div>
<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"> 62</span><span class="preprocessor">#define SP_SR_CLR_BROKE (1 &lt;&lt; 2)</span></div>
<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"> 63</span><span class="preprocessor">#define SP_SR_CLR_INTR (1 &lt;&lt; 3)</span></div>
<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"> 64</span><span class="preprocessor">#define SP_SR_SET_INTR (1 &lt;&lt; 4)</span></div>
<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"> 65</span><span class="preprocessor">#define SP_SR_CLR_SSTEP (1 &lt;&lt; 5)</span></div>
<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"> 66</span><span class="preprocessor">#define SP_SR_SET_SSTEP (1 &lt;&lt; 6)</span></div>
<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span><span class="preprocessor">#define SP_SR_CLR_INTR_BREAK (1 &lt;&lt; 7)</span></div>
<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"> 68</span><span class="preprocessor">#define SP_SR_SET_INTR_BREAK (1 &lt;&lt; 8)</span></div>
<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"> 69</span><span class="preprocessor">#define SP_SR_CLR_SIG0 (1 &lt;&lt; 9)</span></div>
<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"> 70</span><span class="preprocessor">#define SP_SR_SET_SIG0 (1 &lt;&lt; 10)</span></div>
<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"> 71</span><span class="preprocessor">#define SP_SR_CLR_SIG1 (1 &lt;&lt; 11)</span></div>
<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span><span class="preprocessor">#define SP_SR_SET_SIG1 (1 &lt;&lt; 12)</span></div>
<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span><span class="preprocessor">#define SP_SR_CLR_SIG2 (1 &lt;&lt; 13)</span></div>
<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"> 74</span><span class="preprocessor">#define SP_SR_SET_SIG2 (1 &lt;&lt; 14)</span></div>
<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"> 75</span><span class="preprocessor">#define SP_SR_CLR_SIG3 (1 &lt;&lt; 15)</span></div>
<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"> 76</span><span class="preprocessor">#define SP_SR_SET_SIG3 (1 &lt;&lt; 16)</span></div>
<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"> 77</span><span class="preprocessor">#define SP_SR_CLR_SIG4 (1 &lt;&lt; 17)</span></div>
<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"> 78</span><span class="preprocessor">#define SP_SR_SET_SIG4 (1 &lt;&lt; 18)</span></div>
<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"> 79</span><span class="preprocessor">#define SP_SR_CLR_SIG5 (1 &lt;&lt; 19)</span></div>
<div class="line"><a id="l00080" name="l00080"></a><span class="lineno"> 80</span><span class="preprocessor">#define SP_SR_SET_SIG5 (1 &lt;&lt; 20)</span></div>
<div class="line"><a id="l00081" name="l00081"></a><span class="lineno"> 81</span><span class="preprocessor">#define SP_SR_CLR_SIG6 (1 &lt;&lt; 21)</span></div>
<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span><span class="preprocessor">#define SP_SR_SET_SIG6 (1 &lt;&lt; 22)</span></div>
<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"> 83</span><span class="preprocessor">#define SP_SR_CLR_SIG7 (1 &lt;&lt; 23)</span></div>
<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"> 84</span><span class="preprocessor">#define SP_SR_SET_SIG7 (1 &lt;&lt; 24)</span></div>
<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"> 85</span> </div>
<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"> 86</span> </div>
<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"><a class="line" href="boot__io_8h.html"> 88</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00089" name="l00089"></a><span class="lineno"> 89</span> io32_t START;</div>
<div class="line"><a id="l00090" name="l00090"></a><span class="lineno"> 90</span> io32_t END;</div>
<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"> 91</span> io32_t CURRENT;</div>
<div class="line"><a id="l00092" name="l00092"></a><span class="lineno"> 92</span> io32_t SR;</div>
<div class="line"><a id="l00093" name="l00093"></a><span class="lineno"> 93</span> io32_t CLOCK;</div>
<div class="line"><a id="l00094" name="l00094"></a><span class="lineno"> 94</span> io32_t BUF_BUSY;</div>
<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"> 95</span> io32_t PIPE_BUSY;</div>
<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"> 96</span> io32_t TMEM;</div>
<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"> 97</span>} <a class="code hl_struct" href="boot__io_8h.html#structdpc__regs__t">dpc_regs_t</a>;</div>
<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"> 98</span> </div>
<div class="line"><a id="l00099" name="l00099"></a><span class="lineno"> 99</span><span class="preprocessor">#define DPC_BASE (0x04100000UL)</span></div>
<div class="line"><a id="l00100" name="l00100"></a><span class="lineno"> 100</span><span class="preprocessor">#define DPC ((dpc_regs_t *) DPC_BASE)</span></div>
<div class="line"><a id="l00101" name="l00101"></a><span class="lineno"> 101</span> </div>
<div class="line"><a id="l00102" name="l00102"></a><span class="lineno"> 102</span><span class="preprocessor">#define DPC_SR_XBUS_DMEM_DMA (1 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00103" name="l00103"></a><span class="lineno"> 103</span><span class="preprocessor">#define DPC_SR_FREEZE (1 &lt;&lt; 1)</span></div>
<div class="line"><a id="l00104" name="l00104"></a><span class="lineno"> 104</span><span class="preprocessor">#define DPC_SR_FLUSH (1 &lt;&lt; 2)</span></div>
<div class="line"><a id="l00105" name="l00105"></a><span class="lineno"> 105</span><span class="preprocessor">#define DPC_SR_START_GCLK (1 &lt;&lt; 3)</span></div>
<div class="line"><a id="l00106" name="l00106"></a><span class="lineno"> 106</span><span class="preprocessor">#define DPC_SR_TMEM_BUSY (1 &lt;&lt; 4)</span></div>
<div class="line"><a id="l00107" name="l00107"></a><span class="lineno"> 107</span><span class="preprocessor">#define DPC_SR_PIPE_BUSY (1 &lt;&lt; 5)</span></div>
<div class="line"><a id="l00108" name="l00108"></a><span class="lineno"> 108</span><span class="preprocessor">#define DPC_SR_CMD_BUSY (1 &lt;&lt; 6)</span></div>
<div class="line"><a id="l00109" name="l00109"></a><span class="lineno"> 109</span><span class="preprocessor">#define DPC_SR_CBUF_READY (1 &lt;&lt; 7)</span></div>
<div class="line"><a id="l00110" name="l00110"></a><span class="lineno"> 110</span><span class="preprocessor">#define DPC_SR_DMA_BUSY (1 &lt;&lt; 8)</span></div>
<div class="line"><a id="l00111" name="l00111"></a><span class="lineno"> 111</span><span class="preprocessor">#define DPC_SR_END_VALID (1 &lt;&lt; 9)</span></div>
<div class="line"><a id="l00112" name="l00112"></a><span class="lineno"> 112</span><span class="preprocessor">#define DPC_SR_START_VALID (1 &lt;&lt; 10)</span></div>
<div class="line"><a id="l00113" name="l00113"></a><span class="lineno"> 113</span><span class="preprocessor">#define DPC_SR_CLR_XBUS_DMEM_DMA (1 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00114" name="l00114"></a><span class="lineno"> 114</span><span class="preprocessor">#define DPC_SR_SET_XBUS_DMEM_DMA (1 &lt;&lt; 1)</span></div>
<div class="line"><a id="l00115" name="l00115"></a><span class="lineno"> 115</span><span class="preprocessor">#define DPC_SR_CLR_FREEZE (1 &lt;&lt; 2)</span></div>
<div class="line"><a id="l00116" name="l00116"></a><span class="lineno"> 116</span><span class="preprocessor">#define DPC_SR_SET_FREEZE (1 &lt;&lt; 3)</span></div>
<div class="line"><a id="l00117" name="l00117"></a><span class="lineno"> 117</span><span class="preprocessor">#define DPC_SR_CLR_FLUSH (1 &lt;&lt; 4)</span></div>
<div class="line"><a id="l00118" name="l00118"></a><span class="lineno"> 118</span><span class="preprocessor">#define DPC_SR_SET_FLUSH (1 &lt;&lt; 5)</span></div>
<div class="line"><a id="l00119" name="l00119"></a><span class="lineno"> 119</span><span class="preprocessor">#define DPC_SR_CLR_TMEM_CTR (1 &lt;&lt; 6)</span></div>
<div class="line"><a id="l00120" name="l00120"></a><span class="lineno"> 120</span><span class="preprocessor">#define DPC_SR_CLR_PIPE_CTR (1 &lt;&lt; 7)</span></div>
<div class="line"><a id="l00121" name="l00121"></a><span class="lineno"> 121</span><span class="preprocessor">#define DPC_SR_CLR_CMD_CTR (1 &lt;&lt; 8)</span></div>
<div class="line"><a id="l00122" name="l00122"></a><span class="lineno"> 122</span><span class="preprocessor">#define DPC_SR_CLR_CLOCK_CTR (1 &lt;&lt; 9)</span></div>
<div class="line"><a id="l00123" name="l00123"></a><span class="lineno"> 123</span> </div>
<div class="line"><a id="l00124" name="l00124"></a><span class="lineno"> 124</span> </div>
<div class="line"><a id="l00126" name="l00126"></a><span class="lineno"><a class="line" href="boot__io_8h.html"> 126</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00127" name="l00127"></a><span class="lineno"> 127</span> io32_t CR;</div>
<div class="line"><a id="l00128" name="l00128"></a><span class="lineno"> 128</span> io32_t MADDR;</div>
<div class="line"><a id="l00129" name="l00129"></a><span class="lineno"> 129</span> io32_t H_WIDTH;</div>
<div class="line"><a id="l00130" name="l00130"></a><span class="lineno"> 130</span> io32_t V_INTR;</div>
<div class="line"><a id="l00131" name="l00131"></a><span class="lineno"> 131</span> io32_t CURR_LINE;</div>
<div class="line"><a id="l00132" name="l00132"></a><span class="lineno"> 132</span> io32_t TIMING;</div>
<div class="line"><a id="l00133" name="l00133"></a><span class="lineno"> 133</span> io32_t V_SYNC;</div>
<div class="line"><a id="l00134" name="l00134"></a><span class="lineno"> 134</span> io32_t H_SYNC;</div>
<div class="line"><a id="l00135" name="l00135"></a><span class="lineno"> 135</span> io32_t H_SYNC_LEAP;</div>
<div class="line"><a id="l00136" name="l00136"></a><span class="lineno"> 136</span> io32_t H_LIMITS;</div>
<div class="line"><a id="l00137" name="l00137"></a><span class="lineno"> 137</span> io32_t V_LIMITS;</div>
<div class="line"><a id="l00138" name="l00138"></a><span class="lineno"> 138</span> io32_t COLOR_BURST;</div>
<div class="line"><a id="l00139" name="l00139"></a><span class="lineno"> 139</span> io32_t H_SCALE;</div>
<div class="line"><a id="l00140" name="l00140"></a><span class="lineno"> 140</span> io32_t V_SCALE;</div>
<div class="line"><a id="l00141" name="l00141"></a><span class="lineno"> 141</span>} <a class="code hl_struct" href="boot__io_8h.html#structvi__regs__t">vi_regs_t</a>;</div>
<div class="line"><a id="l00142" name="l00142"></a><span class="lineno"> 142</span> </div>
<div class="line"><a id="l00143" name="l00143"></a><span class="lineno"> 143</span><span class="preprocessor">#define VI_BASE (0x04400000UL)</span></div>
<div class="line"><a id="l00144" name="l00144"></a><span class="lineno"> 144</span><span class="preprocessor">#define VI ((vi_regs_t *) VI_BASE)</span></div>
<div class="line"><a id="l00145" name="l00145"></a><span class="lineno"> 145</span> </div>
<div class="line"><a id="l00146" name="l00146"></a><span class="lineno"> 146</span><span class="preprocessor">#define VI_CR_TYPE_16 (2 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00147" name="l00147"></a><span class="lineno"> 147</span><span class="preprocessor">#define VI_CR_TYPE_32 (3 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00148" name="l00148"></a><span class="lineno"> 148</span><span class="preprocessor">#define VI_CR_GAMMA_DITHER_ON (1 &lt;&lt; 2)</span></div>
<div class="line"><a id="l00149" name="l00149"></a><span class="lineno"> 149</span><span class="preprocessor">#define VI_CR_GAMMA_ON (1 &lt;&lt; 3)</span></div>
<div class="line"><a id="l00150" name="l00150"></a><span class="lineno"> 150</span><span class="preprocessor">#define VI_CR_DIVOT_ON (1 &lt;&lt; 4)</span></div>
<div class="line"><a id="l00151" name="l00151"></a><span class="lineno"> 151</span><span class="preprocessor">#define VI_CR_SERRATE_ON (1 &lt;&lt; 6)</span></div>
<div class="line"><a id="l00152" name="l00152"></a><span class="lineno"> 152</span><span class="preprocessor">#define VI_CR_ANTIALIAS_0 (1 &lt;&lt; 8)</span></div>
<div class="line"><a id="l00153" name="l00153"></a><span class="lineno"> 153</span><span class="preprocessor">#define VI_CR_ANTIALIAS_1 (1 &lt;&lt; 9)</span></div>
<div class="line"><a id="l00154" name="l00154"></a><span class="lineno"> 154</span><span class="preprocessor">#define VI_CR_PIXEL_ADVANCE_0 (1 &lt;&lt; 12)</span></div>
<div class="line"><a id="l00155" name="l00155"></a><span class="lineno"> 155</span><span class="preprocessor">#define VI_CR_PIXEL_ADVANCE_1 (1 &lt;&lt; 13)</span></div>
<div class="line"><a id="l00156" name="l00156"></a><span class="lineno"> 156</span><span class="preprocessor">#define VI_CR_PIXEL_ADVANCE_2 (1 &lt;&lt; 14)</span></div>
<div class="line"><a id="l00157" name="l00157"></a><span class="lineno"> 157</span><span class="preprocessor">#define VI_CR_PIXEL_ADVANCE_3 (1 &lt;&lt; 15)</span></div>
<div class="line"><a id="l00158" name="l00158"></a><span class="lineno"> 158</span><span class="preprocessor">#define VI_CR_DITHER_FILTER_ON (1 &lt;&lt; 16)</span></div>
<div class="line"><a id="l00159" name="l00159"></a><span class="lineno"> 159</span> </div>
<div class="line"><a id="l00160" name="l00160"></a><span class="lineno"> 160</span><span class="preprocessor">#define VI_CURR_LINE_FIELD (1 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"> 40</span> io32_t __reserved[0xFFF8];</div>
<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"> 41</span> io32_t PC;</div>
<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"> 42</span>} <a class="code hl_struct" href="boot__io_8h.html#structsp__regs__t">sp_regs_t</a>;</div>
<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"> 43</span> </div>
<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"> 44</span><span class="preprocessor">#define SP_BASE (0x04040000UL)</span></div>
<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"> 45</span><span class="preprocessor">#define SP ((sp_regs_t *) SP_BASE)</span></div>
<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"> 46</span> </div>
<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"> 47</span><span class="preprocessor">#define SP_SR_HALT (1 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span><span class="preprocessor">#define SP_SR_BROKE (1 &lt;&lt; 1)</span></div>
<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"> 49</span><span class="preprocessor">#define SP_SR_DMA_BUSY (1 &lt;&lt; 2)</span></div>
<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"> 50</span><span class="preprocessor">#define SP_SR_DMA_FULL (1 &lt;&lt; 3)</span></div>
<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"> 51</span><span class="preprocessor">#define SP_SR_IO_FULL (1 &lt;&lt; 4)</span></div>
<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span><span class="preprocessor">#define SP_SR_SSTEP (1 &lt;&lt; 5)</span></div>
<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span><span class="preprocessor">#define SP_SR_INTR_BREAK (1 &lt;&lt; 6)</span></div>
<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span><span class="preprocessor">#define SP_SR_SIG0 (1 &lt;&lt; 7)</span></div>
<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"> 55</span><span class="preprocessor">#define SP_SR_SIG1 (1 &lt;&lt; 8)</span></div>
<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span><span class="preprocessor">#define SP_SR_SIG2 (1 &lt;&lt; 9)</span></div>
<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span><span class="preprocessor">#define SP_SR_SIG3 (1 &lt;&lt; 10)</span></div>
<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"> 58</span><span class="preprocessor">#define SP_SR_SIG4 (1 &lt;&lt; 11)</span></div>
<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span><span class="preprocessor">#define SP_SR_SIG5 (1 &lt;&lt; 12)</span></div>
<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"> 60</span><span class="preprocessor">#define SP_SR_SIG6 (1 &lt;&lt; 13)</span></div>
<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"> 61</span><span class="preprocessor">#define SP_SR_SIG7 (1 &lt;&lt; 14)</span></div>
<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"> 62</span><span class="preprocessor">#define SP_SR_CLR_HALT (1 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"> 63</span><span class="preprocessor">#define SP_SR_SET_HALT (1 &lt;&lt; 1)</span></div>
<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"> 64</span><span class="preprocessor">#define SP_SR_CLR_BROKE (1 &lt;&lt; 2)</span></div>
<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"> 65</span><span class="preprocessor">#define SP_SR_CLR_INTR (1 &lt;&lt; 3)</span></div>
<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"> 66</span><span class="preprocessor">#define SP_SR_SET_INTR (1 &lt;&lt; 4)</span></div>
<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span><span class="preprocessor">#define SP_SR_CLR_SSTEP (1 &lt;&lt; 5)</span></div>
<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"> 68</span><span class="preprocessor">#define SP_SR_SET_SSTEP (1 &lt;&lt; 6)</span></div>
<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"> 69</span><span class="preprocessor">#define SP_SR_CLR_INTR_BREAK (1 &lt;&lt; 7)</span></div>
<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"> 70</span><span class="preprocessor">#define SP_SR_SET_INTR_BREAK (1 &lt;&lt; 8)</span></div>
<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"> 71</span><span class="preprocessor">#define SP_SR_CLR_SIG0 (1 &lt;&lt; 9)</span></div>
<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span><span class="preprocessor">#define SP_SR_SET_SIG0 (1 &lt;&lt; 10)</span></div>
<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span><span class="preprocessor">#define SP_SR_CLR_SIG1 (1 &lt;&lt; 11)</span></div>
<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"> 74</span><span class="preprocessor">#define SP_SR_SET_SIG1 (1 &lt;&lt; 12)</span></div>
<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"> 75</span><span class="preprocessor">#define SP_SR_CLR_SIG2 (1 &lt;&lt; 13)</span></div>
<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"> 76</span><span class="preprocessor">#define SP_SR_SET_SIG2 (1 &lt;&lt; 14)</span></div>
<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"> 77</span><span class="preprocessor">#define SP_SR_CLR_SIG3 (1 &lt;&lt; 15)</span></div>
<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"> 78</span><span class="preprocessor">#define SP_SR_SET_SIG3 (1 &lt;&lt; 16)</span></div>
<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"> 79</span><span class="preprocessor">#define SP_SR_CLR_SIG4 (1 &lt;&lt; 17)</span></div>
<div class="line"><a id="l00080" name="l00080"></a><span class="lineno"> 80</span><span class="preprocessor">#define SP_SR_SET_SIG4 (1 &lt;&lt; 18)</span></div>
<div class="line"><a id="l00081" name="l00081"></a><span class="lineno"> 81</span><span class="preprocessor">#define SP_SR_CLR_SIG5 (1 &lt;&lt; 19)</span></div>
<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span><span class="preprocessor">#define SP_SR_SET_SIG5 (1 &lt;&lt; 20)</span></div>
<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"> 83</span><span class="preprocessor">#define SP_SR_CLR_SIG6 (1 &lt;&lt; 21)</span></div>
<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"> 84</span><span class="preprocessor">#define SP_SR_SET_SIG6 (1 &lt;&lt; 22)</span></div>
<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"> 85</span><span class="preprocessor">#define SP_SR_CLR_SIG7 (1 &lt;&lt; 23)</span></div>
<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"> 86</span><span class="preprocessor">#define SP_SR_SET_SIG7 (1 &lt;&lt; 24)</span></div>
<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"> 87</span> </div>
<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"> 88</span> </div>
<div class="line"><a id="l00090" name="l00090"></a><span class="lineno"><a class="line" href="boot__io_8h.html"> 90</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"> 91</span> io32_t START;</div>
<div class="line"><a id="l00092" name="l00092"></a><span class="lineno"> 92</span> io32_t END;</div>
<div class="line"><a id="l00093" name="l00093"></a><span class="lineno"> 93</span> io32_t CURRENT;</div>
<div class="line"><a id="l00094" name="l00094"></a><span class="lineno"> 94</span> io32_t SR;</div>
<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"> 95</span> io32_t CLOCK;</div>
<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"> 96</span> io32_t BUF_BUSY;</div>
<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"> 97</span> io32_t PIPE_BUSY;</div>
<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"> 98</span> io32_t TMEM;</div>
<div class="line"><a id="l00099" name="l00099"></a><span class="lineno"> 99</span>} <a class="code hl_struct" href="boot__io_8h.html#structdpc__regs__t">dpc_regs_t</a>;</div>
<div class="line"><a id="l00100" name="l00100"></a><span class="lineno"> 100</span> </div>
<div class="line"><a id="l00101" name="l00101"></a><span class="lineno"> 101</span><span class="preprocessor">#define DPC_BASE (0x04100000UL)</span></div>
<div class="line"><a id="l00102" name="l00102"></a><span class="lineno"> 102</span><span class="preprocessor">#define DPC ((dpc_regs_t *) DPC_BASE)</span></div>
<div class="line"><a id="l00103" name="l00103"></a><span class="lineno"> 103</span> </div>
<div class="line"><a id="l00104" name="l00104"></a><span class="lineno"> 104</span><span class="preprocessor">#define DPC_SR_XBUS_DMEM_DMA (1 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00105" name="l00105"></a><span class="lineno"> 105</span><span class="preprocessor">#define DPC_SR_FREEZE (1 &lt;&lt; 1)</span></div>
<div class="line"><a id="l00106" name="l00106"></a><span class="lineno"> 106</span><span class="preprocessor">#define DPC_SR_FLUSH (1 &lt;&lt; 2)</span></div>
<div class="line"><a id="l00107" name="l00107"></a><span class="lineno"> 107</span><span class="preprocessor">#define DPC_SR_START_GCLK (1 &lt;&lt; 3)</span></div>
<div class="line"><a id="l00108" name="l00108"></a><span class="lineno"> 108</span><span class="preprocessor">#define DPC_SR_TMEM_BUSY (1 &lt;&lt; 4)</span></div>
<div class="line"><a id="l00109" name="l00109"></a><span class="lineno"> 109</span><span class="preprocessor">#define DPC_SR_PIPE_BUSY (1 &lt;&lt; 5)</span></div>
<div class="line"><a id="l00110" name="l00110"></a><span class="lineno"> 110</span><span class="preprocessor">#define DPC_SR_CMD_BUSY (1 &lt;&lt; 6)</span></div>
<div class="line"><a id="l00111" name="l00111"></a><span class="lineno"> 111</span><span class="preprocessor">#define DPC_SR_CBUF_READY (1 &lt;&lt; 7)</span></div>
<div class="line"><a id="l00112" name="l00112"></a><span class="lineno"> 112</span><span class="preprocessor">#define DPC_SR_DMA_BUSY (1 &lt;&lt; 8)</span></div>
<div class="line"><a id="l00113" name="l00113"></a><span class="lineno"> 113</span><span class="preprocessor">#define DPC_SR_END_VALID (1 &lt;&lt; 9)</span></div>
<div class="line"><a id="l00114" name="l00114"></a><span class="lineno"> 114</span><span class="preprocessor">#define DPC_SR_START_VALID (1 &lt;&lt; 10)</span></div>
<div class="line"><a id="l00115" name="l00115"></a><span class="lineno"> 115</span><span class="preprocessor">#define DPC_SR_CLR_XBUS_DMEM_DMA (1 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00116" name="l00116"></a><span class="lineno"> 116</span><span class="preprocessor">#define DPC_SR_SET_XBUS_DMEM_DMA (1 &lt;&lt; 1)</span></div>
<div class="line"><a id="l00117" name="l00117"></a><span class="lineno"> 117</span><span class="preprocessor">#define DPC_SR_CLR_FREEZE (1 &lt;&lt; 2)</span></div>
<div class="line"><a id="l00118" name="l00118"></a><span class="lineno"> 118</span><span class="preprocessor">#define DPC_SR_SET_FREEZE (1 &lt;&lt; 3)</span></div>
<div class="line"><a id="l00119" name="l00119"></a><span class="lineno"> 119</span><span class="preprocessor">#define DPC_SR_CLR_FLUSH (1 &lt;&lt; 4)</span></div>
<div class="line"><a id="l00120" name="l00120"></a><span class="lineno"> 120</span><span class="preprocessor">#define DPC_SR_SET_FLUSH (1 &lt;&lt; 5)</span></div>
<div class="line"><a id="l00121" name="l00121"></a><span class="lineno"> 121</span><span class="preprocessor">#define DPC_SR_CLR_TMEM_CTR (1 &lt;&lt; 6)</span></div>
<div class="line"><a id="l00122" name="l00122"></a><span class="lineno"> 122</span><span class="preprocessor">#define DPC_SR_CLR_PIPE_CTR (1 &lt;&lt; 7)</span></div>
<div class="line"><a id="l00123" name="l00123"></a><span class="lineno"> 123</span><span class="preprocessor">#define DPC_SR_CLR_CMD_CTR (1 &lt;&lt; 8)</span></div>
<div class="line"><a id="l00124" name="l00124"></a><span class="lineno"> 124</span><span class="preprocessor">#define DPC_SR_CLR_CLOCK_CTR (1 &lt;&lt; 9)</span></div>
<div class="line"><a id="l00125" name="l00125"></a><span class="lineno"> 125</span> </div>
<div class="line"><a id="l00126" name="l00126"></a><span class="lineno"> 126</span> </div>
<div class="line"><a id="l00128" name="l00128"></a><span class="lineno"><a class="line" href="boot__io_8h.html"> 128</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00129" name="l00129"></a><span class="lineno"> 129</span> io32_t CR;</div>
<div class="line"><a id="l00130" name="l00130"></a><span class="lineno"> 130</span> io32_t MADDR;</div>
<div class="line"><a id="l00131" name="l00131"></a><span class="lineno"> 131</span> io32_t H_WIDTH;</div>
<div class="line"><a id="l00132" name="l00132"></a><span class="lineno"> 132</span> io32_t V_INTR;</div>
<div class="line"><a id="l00133" name="l00133"></a><span class="lineno"> 133</span> io32_t CURR_LINE;</div>
<div class="line"><a id="l00134" name="l00134"></a><span class="lineno"> 134</span> io32_t TIMING;</div>
<div class="line"><a id="l00135" name="l00135"></a><span class="lineno"> 135</span> io32_t V_SYNC;</div>
<div class="line"><a id="l00136" name="l00136"></a><span class="lineno"> 136</span> io32_t H_SYNC;</div>
<div class="line"><a id="l00137" name="l00137"></a><span class="lineno"> 137</span> io32_t H_SYNC_LEAP;</div>
<div class="line"><a id="l00138" name="l00138"></a><span class="lineno"> 138</span> io32_t H_LIMITS;</div>
<div class="line"><a id="l00139" name="l00139"></a><span class="lineno"> 139</span> io32_t V_LIMITS;</div>
<div class="line"><a id="l00140" name="l00140"></a><span class="lineno"> 140</span> io32_t COLOR_BURST;</div>
<div class="line"><a id="l00141" name="l00141"></a><span class="lineno"> 141</span> io32_t H_SCALE;</div>
<div class="line"><a id="l00142" name="l00142"></a><span class="lineno"> 142</span> io32_t V_SCALE;</div>
<div class="line"><a id="l00143" name="l00143"></a><span class="lineno"> 143</span>} <a class="code hl_struct" href="boot__io_8h.html#structvi__regs__t">vi_regs_t</a>;</div>
<div class="line"><a id="l00144" name="l00144"></a><span class="lineno"> 144</span> </div>
<div class="line"><a id="l00145" name="l00145"></a><span class="lineno"> 145</span><span class="preprocessor">#define VI_BASE (0x04400000UL)</span></div>
<div class="line"><a id="l00146" name="l00146"></a><span class="lineno"> 146</span><span class="preprocessor">#define VI ((vi_regs_t *) VI_BASE)</span></div>
<div class="line"><a id="l00147" name="l00147"></a><span class="lineno"> 147</span> </div>
<div class="line"><a id="l00148" name="l00148"></a><span class="lineno"> 148</span><span class="preprocessor">#define VI_CR_TYPE_16 (2 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00149" name="l00149"></a><span class="lineno"> 149</span><span class="preprocessor">#define VI_CR_TYPE_32 (3 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00150" name="l00150"></a><span class="lineno"> 150</span><span class="preprocessor">#define VI_CR_GAMMA_DITHER_ON (1 &lt;&lt; 2)</span></div>
<div class="line"><a id="l00151" name="l00151"></a><span class="lineno"> 151</span><span class="preprocessor">#define VI_CR_GAMMA_ON (1 &lt;&lt; 3)</span></div>
<div class="line"><a id="l00152" name="l00152"></a><span class="lineno"> 152</span><span class="preprocessor">#define VI_CR_DIVOT_ON (1 &lt;&lt; 4)</span></div>
<div class="line"><a id="l00153" name="l00153"></a><span class="lineno"> 153</span><span class="preprocessor">#define VI_CR_SERRATE_ON (1 &lt;&lt; 6)</span></div>
<div class="line"><a id="l00154" name="l00154"></a><span class="lineno"> 154</span><span class="preprocessor">#define VI_CR_ANTIALIAS_0 (1 &lt;&lt; 8)</span></div>
<div class="line"><a id="l00155" name="l00155"></a><span class="lineno"> 155</span><span class="preprocessor">#define VI_CR_ANTIALIAS_1 (1 &lt;&lt; 9)</span></div>
<div class="line"><a id="l00156" name="l00156"></a><span class="lineno"> 156</span><span class="preprocessor">#define VI_CR_PIXEL_ADVANCE_0 (1 &lt;&lt; 12)</span></div>
<div class="line"><a id="l00157" name="l00157"></a><span class="lineno"> 157</span><span class="preprocessor">#define VI_CR_PIXEL_ADVANCE_1 (1 &lt;&lt; 13)</span></div>
<div class="line"><a id="l00158" name="l00158"></a><span class="lineno"> 158</span><span class="preprocessor">#define VI_CR_PIXEL_ADVANCE_2 (1 &lt;&lt; 14)</span></div>
<div class="line"><a id="l00159" name="l00159"></a><span class="lineno"> 159</span><span class="preprocessor">#define VI_CR_PIXEL_ADVANCE_3 (1 &lt;&lt; 15)</span></div>
<div class="line"><a id="l00160" name="l00160"></a><span class="lineno"> 160</span><span class="preprocessor">#define VI_CR_DITHER_FILTER_ON (1 &lt;&lt; 16)</span></div>
<div class="line"><a id="l00161" name="l00161"></a><span class="lineno"> 161</span> </div>
<div class="line"><a id="l00162" name="l00162"></a><span class="lineno"> 162</span> </div>
<div class="line"><a id="l00163" name="l00163"></a><span class="lineno"><a class="line" href="boot__io_8h.html"> 163</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00164" name="l00164"></a><span class="lineno"> 164</span> io32_t MADDR;</div>
<div class="line"><a id="l00165" name="l00165"></a><span class="lineno"> 165</span> io32_t LEN;</div>
<div class="line"><a id="l00166" name="l00166"></a><span class="lineno"> 166</span> io32_t CR;</div>
<div class="line"><a id="l00167" name="l00167"></a><span class="lineno"> 167</span> io32_t SR;</div>
<div class="line"><a id="l00168" name="l00168"></a><span class="lineno"> 168</span> io32_t DACRATE;</div>
<div class="line"><a id="l00169" name="l00169"></a><span class="lineno"> 169</span> io32_t BITRATE;</div>
<div class="line"><a id="l00170" name="l00170"></a><span class="lineno"> 170</span>} <a class="code hl_struct" href="boot__io_8h.html#structai__regs__t">ai_regs_t</a>;</div>
<div class="line"><a id="l00171" name="l00171"></a><span class="lineno"> 171</span> </div>
<div class="line"><a id="l00172" name="l00172"></a><span class="lineno"> 172</span><span class="preprocessor">#define AI_BASE (0x04500000UL)</span></div>
<div class="line"><a id="l00173" name="l00173"></a><span class="lineno"> 173</span><span class="preprocessor">#define AI ((ai_regs_t *) AI_BASE)</span></div>
<div class="line"><a id="l00174" name="l00174"></a><span class="lineno"> 174</span> </div>
<div class="line"><a id="l00175" name="l00175"></a><span class="lineno"> 175</span><span class="preprocessor">#define AI_SR_DMA_BUSY (1 &lt;&lt; 30)</span></div>
<div class="line"><a id="l00176" name="l00176"></a><span class="lineno"> 176</span><span class="preprocessor">#define AI_SR_FIFO_FULL (1 &lt;&lt; 31)</span></div>
<div class="line"><a id="l00177" name="l00177"></a><span class="lineno"> 177</span><span class="preprocessor">#define AI_CR_DMA_ON (1 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00178" name="l00178"></a><span class="lineno"> 178</span> </div>
<div class="line"><a id="l00179" name="l00179"></a><span class="lineno"> 179</span> </div>
<div class="line"><a id="l00181" name="l00181"></a><span class="lineno"><a class="line" href="boot__io_8h.html"> 181</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00182" name="l00182"></a><span class="lineno"> 182</span> io32_t MADDR;</div>
<div class="line"><a id="l00183" name="l00183"></a><span class="lineno"> 183</span> io32_t PADDR;</div>
<div class="line"><a id="l00184" name="l00184"></a><span class="lineno"> 184</span> io32_t RDMA;</div>
<div class="line"><a id="l00185" name="l00185"></a><span class="lineno"> 185</span> io32_t WDMA;</div>
<div class="line"><a id="l00186" name="l00186"></a><span class="lineno"> 186</span> io32_t SR;</div>
<div class="line"><a id="l00187" name="l00187"></a><span class="lineno"><a class="line" href="boot__io_8h.html"> 187</a></span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00188" name="l00188"></a><span class="lineno"> 188</span> io32_t LAT;</div>
<div class="line"><a id="l00189" name="l00189"></a><span class="lineno"> 189</span> io32_t PWD;</div>
<div class="line"><a id="l00190" name="l00190"></a><span class="lineno"> 190</span> io32_t PGS;</div>
<div class="line"><a id="l00191" name="l00191"></a><span class="lineno"> 191</span> io32_t RLS;</div>
<div class="line"><a id="l00192" name="l00192"></a><span class="lineno"> 192</span> } DOM[2];</div>
<div class="line"><a id="l00193" name="l00193"></a><span class="lineno"> 193</span>} <a class="code hl_struct" href="boot__io_8h.html#structpi__regs__t">pi_regs_t</a>;</div>
<div class="line"><a id="l00194" name="l00194"></a><span class="lineno"> 194</span> </div>
<div class="line"><a id="l00195" name="l00195"></a><span class="lineno"> 195</span><span class="preprocessor">#define PI_BASE (0x04600000UL)</span></div>
<div class="line"><a id="l00196" name="l00196"></a><span class="lineno"> 196</span><span class="preprocessor">#define PI ((pi_regs_t *) PI_BASE)</span></div>
<div class="line"><a id="l00197" name="l00197"></a><span class="lineno"> 197</span> </div>
<div class="line"><a id="l00198" name="l00198"></a><span class="lineno"> 198</span><span class="preprocessor">#define PI_SR_DMA_BUSY (1 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00199" name="l00199"></a><span class="lineno"> 199</span><span class="preprocessor">#define PI_SR_IO_BUSY (1 &lt;&lt; 1)</span></div>
<div class="line"><a id="l00200" name="l00200"></a><span class="lineno"> 200</span><span class="preprocessor">#define PI_SR_DMA_ERROR (1 &lt;&lt; 2)</span></div>
<div class="line"><a id="l00201" name="l00201"></a><span class="lineno"> 201</span><span class="preprocessor">#define PI_SR_RESET (1 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00202" name="l00202"></a><span class="lineno"> 202</span><span class="preprocessor">#define PI_SR_CLR_INTR (1 &lt;&lt; 1)</span></div>
<div class="line"><a id="l00203" name="l00203"></a><span class="lineno"> 203</span> </div>
<div class="line"><a id="l00204" name="l00204"></a><span class="lineno"> 204</span> </div>
<div class="line"><a id="l00205" name="l00205"></a><span class="lineno"> 205</span><span class="preprocessor">#define ROM_DDIPL_BASE (0x06000000UL)</span></div>
<div class="line"><a id="l00206" name="l00206"></a><span class="lineno"> 206</span><span class="preprocessor">#define ROM_DDIPL ((io32_t *) ROM_DDIPL_BASE)</span></div>
<div class="line"><a id="l00207" name="l00207"></a><span class="lineno"> 207</span> </div>
<div class="line"><a id="l00208" name="l00208"></a><span class="lineno"> 208</span> </div>
<div class="line"><a id="l00209" name="l00209"></a><span class="lineno"> 209</span><span class="preprocessor">#define ROM_CART_BASE (0x10000000UL)</span></div>
<div class="line"><a id="l00210" name="l00210"></a><span class="lineno"> 210</span><span class="preprocessor">#define ROM_CART ((io32_t *) ROM_CART_BASE)</span></div>
<div class="line"><a id="l00211" name="l00211"></a><span class="lineno"> 211</span> </div>
<div class="line"><a id="l00212" name="l00212"></a><span class="lineno"> 212</span> </div>
<div class="line"><a id="l00213" name="l00213"></a><span class="lineno"><a class="line" href="boot__io_8h.html"> 213</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00214" name="l00214"></a><span class="lineno"> 214</span> uint32_t tv_type;</div>
<div class="line"><a id="l00215" name="l00215"></a><span class="lineno"> 215</span> uint32_t device_type;</div>
<div class="line"><a id="l00216" name="l00216"></a><span class="lineno"> 216</span> uint32_t device_base;</div>
<div class="line"><a id="l00217" name="l00217"></a><span class="lineno"> 217</span> uint32_t reset_type;</div>
<div class="line"><a id="l00218" name="l00218"></a><span class="lineno"> 218</span> uint32_t cic_id;</div>
<div class="line"><a id="l00219" name="l00219"></a><span class="lineno"> 219</span> uint32_t version;</div>
<div class="line"><a id="l00220" name="l00220"></a><span class="lineno"> 220</span> uint32_t mem_size;</div>
<div class="line"><a id="l00221" name="l00221"></a><span class="lineno"> 221</span> uint8_t app_nmi_buffer[64];</div>
<div class="line"><a id="l00222" name="l00222"></a><span class="lineno"> 222</span> uint32_t __reserved_1[37];</div>
<div class="line"><a id="l00223" name="l00223"></a><span class="lineno"> 223</span> uint32_t mem_size_6105;</div>
<div class="line"><a id="l00224" name="l00224"></a><span class="lineno"> 224</span>} <a class="code hl_struct" href="boot__io_8h.html#structos__info__t">os_info_t</a>;</div>
<div class="line"><a id="l00225" name="l00225"></a><span class="lineno"> 225</span> </div>
<div class="line"><a id="l00226" name="l00226"></a><span class="lineno"> 226</span><span class="preprocessor">#define OS_INFO_BASE (0x80000300UL)</span></div>
<div class="line"><a id="l00227" name="l00227"></a><span class="lineno"> 227</span><span class="preprocessor">#define OS_INFO ((os_info_t *) OS_INFO_BASE)</span></div>
<div class="line"><a id="l00228" name="l00228"></a><span class="lineno"> 228</span> </div>
<div class="line"><a id="l00229" name="l00229"></a><span class="lineno"> 229</span><span class="preprocessor">#define OS_INFO_RESET_TYPE_COLD (0)</span></div>
<div class="line"><a id="l00230" name="l00230"></a><span class="lineno"> 230</span><span class="preprocessor">#define OS_INFO_RESET_TYPE_NMI (1)</span></div>
<div class="line"><a id="l00231" name="l00231"></a><span class="lineno"> 231</span> </div>
<div class="line"><a id="l00232" name="l00232"></a><span class="lineno"> 232</span> </div>
<div class="line"><a id="l00233" name="l00233"></a><span class="lineno"> 233</span><span class="keyword">static</span> <span class="keyword">inline</span> uint32_t cpu_io_read (io32_t *address) {</div>
<div class="line"><a id="l00234" name="l00234"></a><span class="lineno"> 234</span> io32_t *uncached = UNCACHED(address);</div>
<div class="line"><a id="l00235" name="l00235"></a><span class="lineno"> 235</span> uint32_t value = *uncached;</div>
<div class="line"><a id="l00236" name="l00236"></a><span class="lineno"> 236</span> <span class="keywordflow">return</span> value;</div>
<div class="line"><a id="l00237" name="l00237"></a><span class="lineno"> 237</span>}</div>
<div class="line"><a id="l00238" name="l00238"></a><span class="lineno"> 238</span> </div>
<div class="line"><a id="l00239" name="l00239"></a><span class="lineno"> 239</span><span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> cpu_io_write (io32_t *address, uint32_t value) {</div>
<div class="line"><a id="l00240" name="l00240"></a><span class="lineno"> 240</span> io32_t *uncached = UNCACHED(address);</div>
<div class="line"><a id="l00241" name="l00241"></a><span class="lineno"> 241</span> *uncached = value;</div>
<div class="line"><a id="l00242" name="l00242"></a><span class="lineno"> 242</span>}</div>
<div class="line"><a id="l00243" name="l00243"></a><span class="lineno"> 243</span> </div>
<div class="line"><a id="l00244" name="l00244"></a><span class="lineno"> 244</span> </div>
<div class="line"><a id="l00245" name="l00245"></a><span class="lineno"> 245</span><span class="preprocessor">#endif</span></div>
<div class="ttc" id="aboot__io_8h_html_structai__regs__t"><div class="ttname"><a href="boot__io_8h.html#structai__regs__t">ai_regs_t</a></div><div class="ttdef"><b>Definition:</b> boot_io.h:163</div></div>
<div class="ttc" id="aboot__io_8h_html_structdpc__regs__t"><div class="ttname"><a href="boot__io_8h.html#structdpc__regs__t">dpc_regs_t</a></div><div class="ttdoc">DPC Registers Structure.</div><div class="ttdef"><b>Definition:</b> boot_io.h:88</div></div>
<div class="ttc" id="aboot__io_8h_html_structos__info__t"><div class="ttname"><a href="boot__io_8h.html#structos__info__t">os_info_t</a></div><div class="ttdef"><b>Definition:</b> boot_io.h:213</div></div>
<div class="ttc" id="aboot__io_8h_html_structpi__regs__t"><div class="ttname"><a href="boot__io_8h.html#structpi__regs__t">pi_regs_t</a></div><div class="ttdoc">Parallel Interface Register Structure.</div><div class="ttdef"><b>Definition:</b> boot_io.h:181</div></div>
<div class="line"><a id="l00162" name="l00162"></a><span class="lineno"> 162</span><span class="preprocessor">#define VI_CURR_LINE_FIELD (1 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00163" name="l00163"></a><span class="lineno"> 163</span> </div>
<div class="line"><a id="l00164" name="l00164"></a><span class="lineno"> 164</span> </div>
<div class="line"><a id="l00165" name="l00165"></a><span class="lineno"><a class="line" href="boot__io_8h.html"> 165</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00166" name="l00166"></a><span class="lineno"> 166</span> io32_t MADDR;</div>
<div class="line"><a id="l00167" name="l00167"></a><span class="lineno"> 167</span> io32_t LEN;</div>
<div class="line"><a id="l00168" name="l00168"></a><span class="lineno"> 168</span> io32_t CR;</div>
<div class="line"><a id="l00169" name="l00169"></a><span class="lineno"> 169</span> io32_t SR;</div>
<div class="line"><a id="l00170" name="l00170"></a><span class="lineno"> 170</span> io32_t DACRATE;</div>
<div class="line"><a id="l00171" name="l00171"></a><span class="lineno"> 171</span> io32_t BITRATE;</div>
<div class="line"><a id="l00172" name="l00172"></a><span class="lineno"> 172</span>} <a class="code hl_struct" href="boot__io_8h.html#structai__regs__t">ai_regs_t</a>;</div>
<div class="line"><a id="l00173" name="l00173"></a><span class="lineno"> 173</span> </div>
<div class="line"><a id="l00174" name="l00174"></a><span class="lineno"> 174</span><span class="preprocessor">#define AI_BASE (0x04500000UL)</span></div>
<div class="line"><a id="l00175" name="l00175"></a><span class="lineno"> 175</span><span class="preprocessor">#define AI ((ai_regs_t *) AI_BASE)</span></div>
<div class="line"><a id="l00176" name="l00176"></a><span class="lineno"> 176</span> </div>
<div class="line"><a id="l00177" name="l00177"></a><span class="lineno"> 177</span><span class="preprocessor">#define AI_SR_DMA_BUSY (1 &lt;&lt; 30)</span></div>
<div class="line"><a id="l00178" name="l00178"></a><span class="lineno"> 178</span><span class="preprocessor">#define AI_SR_FIFO_FULL (1 &lt;&lt; 31)</span></div>
<div class="line"><a id="l00179" name="l00179"></a><span class="lineno"> 179</span><span class="preprocessor">#define AI_CR_DMA_ON (1 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00180" name="l00180"></a><span class="lineno"> 180</span> </div>
<div class="line"><a id="l00181" name="l00181"></a><span class="lineno"> 181</span> </div>
<div class="line"><a id="l00183" name="l00183"></a><span class="lineno"><a class="line" href="boot__io_8h.html"> 183</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00184" name="l00184"></a><span class="lineno"> 184</span> io32_t MADDR;</div>
<div class="line"><a id="l00185" name="l00185"></a><span class="lineno"> 185</span> io32_t PADDR;</div>
<div class="line"><a id="l00186" name="l00186"></a><span class="lineno"> 186</span> io32_t RDMA;</div>
<div class="line"><a id="l00187" name="l00187"></a><span class="lineno"> 187</span> io32_t WDMA;</div>
<div class="line"><a id="l00188" name="l00188"></a><span class="lineno"> 188</span> io32_t SR;</div>
<div class="line"><a id="l00189" name="l00189"></a><span class="lineno"><a class="line" href="boot__io_8h.html"> 189</a></span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00190" name="l00190"></a><span class="lineno"> 190</span> io32_t LAT;</div>
<div class="line"><a id="l00191" name="l00191"></a><span class="lineno"> 191</span> io32_t PWD;</div>
<div class="line"><a id="l00192" name="l00192"></a><span class="lineno"> 192</span> io32_t PGS;</div>
<div class="line"><a id="l00193" name="l00193"></a><span class="lineno"> 193</span> io32_t RLS;</div>
<div class="line"><a id="l00194" name="l00194"></a><span class="lineno"> 194</span> } DOM[2];</div>
<div class="line"><a id="l00195" name="l00195"></a><span class="lineno"> 195</span>} <a class="code hl_struct" href="boot__io_8h.html#structpi__regs__t">pi_regs_t</a>;</div>
<div class="line"><a id="l00196" name="l00196"></a><span class="lineno"> 196</span> </div>
<div class="line"><a id="l00197" name="l00197"></a><span class="lineno"> 197</span><span class="preprocessor">#define PI_BASE (0x04600000UL)</span></div>
<div class="line"><a id="l00198" name="l00198"></a><span class="lineno"> 198</span><span class="preprocessor">#define PI ((pi_regs_t *) PI_BASE)</span></div>
<div class="line"><a id="l00199" name="l00199"></a><span class="lineno"> 199</span> </div>
<div class="line"><a id="l00200" name="l00200"></a><span class="lineno"> 200</span><span class="preprocessor">#define PI_SR_DMA_BUSY (1 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00201" name="l00201"></a><span class="lineno"> 201</span><span class="preprocessor">#define PI_SR_IO_BUSY (1 &lt;&lt; 1)</span></div>
<div class="line"><a id="l00202" name="l00202"></a><span class="lineno"> 202</span><span class="preprocessor">#define PI_SR_DMA_ERROR (1 &lt;&lt; 2)</span></div>
<div class="line"><a id="l00203" name="l00203"></a><span class="lineno"> 203</span><span class="preprocessor">#define PI_SR_RESET (1 &lt;&lt; 0)</span></div>
<div class="line"><a id="l00204" name="l00204"></a><span class="lineno"> 204</span><span class="preprocessor">#define PI_SR_CLR_INTR (1 &lt;&lt; 1)</span></div>
<div class="line"><a id="l00205" name="l00205"></a><span class="lineno"> 205</span> </div>
<div class="line"><a id="l00206" name="l00206"></a><span class="lineno"> 206</span> </div>
<div class="line"><a id="l00207" name="l00207"></a><span class="lineno"> 207</span><span class="preprocessor">#define ROM_DDIPL_BASE (0x06000000UL)</span></div>
<div class="line"><a id="l00208" name="l00208"></a><span class="lineno"> 208</span><span class="preprocessor">#define ROM_DDIPL ((io32_t *) ROM_DDIPL_BASE)</span></div>
<div class="line"><a id="l00209" name="l00209"></a><span class="lineno"> 209</span> </div>
<div class="line"><a id="l00210" name="l00210"></a><span class="lineno"> 210</span> </div>
<div class="line"><a id="l00211" name="l00211"></a><span class="lineno"> 211</span><span class="preprocessor">#define ROM_CART_BASE (0x10000000UL)</span></div>
<div class="line"><a id="l00212" name="l00212"></a><span class="lineno"> 212</span><span class="preprocessor">#define ROM_CART ((io32_t *) ROM_CART_BASE)</span></div>
<div class="line"><a id="l00213" name="l00213"></a><span class="lineno"> 213</span> </div>
<div class="line"><a id="l00214" name="l00214"></a><span class="lineno"> 214</span> </div>
<div class="line"><a id="l00215" name="l00215"></a><span class="lineno"><a class="line" href="boot__io_8h.html"> 215</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00216" name="l00216"></a><span class="lineno"> 216</span> uint32_t tv_type;</div>
<div class="line"><a id="l00217" name="l00217"></a><span class="lineno"> 217</span> uint32_t device_type;</div>
<div class="line"><a id="l00218" name="l00218"></a><span class="lineno"> 218</span> uint32_t device_base;</div>
<div class="line"><a id="l00219" name="l00219"></a><span class="lineno"> 219</span> uint32_t reset_type;</div>
<div class="line"><a id="l00220" name="l00220"></a><span class="lineno"> 220</span> uint32_t cic_id;</div>
<div class="line"><a id="l00221" name="l00221"></a><span class="lineno"> 221</span> uint32_t version;</div>
<div class="line"><a id="l00222" name="l00222"></a><span class="lineno"> 222</span> uint32_t mem_size;</div>
<div class="line"><a id="l00223" name="l00223"></a><span class="lineno"> 223</span> uint8_t app_nmi_buffer[64];</div>
<div class="line"><a id="l00224" name="l00224"></a><span class="lineno"> 224</span> uint32_t __reserved_1[37];</div>
<div class="line"><a id="l00225" name="l00225"></a><span class="lineno"> 225</span> uint32_t mem_size_6105;</div>
<div class="line"><a id="l00226" name="l00226"></a><span class="lineno"> 226</span>} <a class="code hl_struct" href="boot__io_8h.html#structos__info__t">os_info_t</a>;</div>
<div class="line"><a id="l00227" name="l00227"></a><span class="lineno"> 227</span> </div>
<div class="line"><a id="l00228" name="l00228"></a><span class="lineno"> 228</span><span class="preprocessor">#define OS_INFO_BASE (0x80000300UL)</span></div>
<div class="line"><a id="l00229" name="l00229"></a><span class="lineno"> 229</span><span class="preprocessor">#define OS_INFO ((os_info_t *) OS_INFO_BASE)</span></div>
<div class="line"><a id="l00230" name="l00230"></a><span class="lineno"> 230</span> </div>
<div class="line"><a id="l00231" name="l00231"></a><span class="lineno"> 231</span><span class="preprocessor">#define OS_INFO_RESET_TYPE_COLD (0)</span></div>
<div class="line"><a id="l00232" name="l00232"></a><span class="lineno"> 232</span><span class="preprocessor">#define OS_INFO_RESET_TYPE_NMI (1)</span></div>
<div class="line"><a id="l00233" name="l00233"></a><span class="lineno"> 233</span> </div>
<div class="line"><a id="l00234" name="l00234"></a><span class="lineno"> 234</span> </div>
<div class="line"><a id="l00235" name="l00235"></a><span class="lineno"> 235</span><span class="keyword">static</span> <span class="keyword">inline</span> uint32_t cpu_io_read (io32_t *address) {</div>
<div class="line"><a id="l00236" name="l00236"></a><span class="lineno"> 236</span> io32_t *uncached = UNCACHED(address);</div>
<div class="line"><a id="l00237" name="l00237"></a><span class="lineno"> 237</span> uint32_t value = *uncached;</div>
<div class="line"><a id="l00238" name="l00238"></a><span class="lineno"> 238</span> <span class="keywordflow">return</span> value;</div>
<div class="line"><a id="l00239" name="l00239"></a><span class="lineno"> 239</span>}</div>
<div class="line"><a id="l00240" name="l00240"></a><span class="lineno"> 240</span> </div>
<div class="line"><a id="l00241" name="l00241"></a><span class="lineno"> 241</span><span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> cpu_io_write (io32_t *address, uint32_t value) {</div>
<div class="line"><a id="l00242" name="l00242"></a><span class="lineno"> 242</span> io32_t *uncached = UNCACHED(address);</div>
<div class="line"><a id="l00243" name="l00243"></a><span class="lineno"> 243</span> *uncached = value;</div>
<div class="line"><a id="l00244" name="l00244"></a><span class="lineno"> 244</span>}</div>
<div class="line"><a id="l00245" name="l00245"></a><span class="lineno"> 245</span> </div>
<div class="line"><a id="l00246" name="l00246"></a><span class="lineno"> 246</span> </div>
<div class="line"><a id="l00247" name="l00247"></a><span class="lineno"> 247</span><span class="preprocessor">#endif</span></div>
<div class="ttc" id="aboot__io_8h_html_structai__regs__t"><div class="ttname"><a href="boot__io_8h.html#structai__regs__t">ai_regs_t</a></div><div class="ttdef"><b>Definition:</b> boot_io.h:165</div></div>
<div class="ttc" id="aboot__io_8h_html_structdpc__regs__t"><div class="ttname"><a href="boot__io_8h.html#structdpc__regs__t">dpc_regs_t</a></div><div class="ttdoc">DPC Registers Structure.</div><div class="ttdef"><b>Definition:</b> boot_io.h:90</div></div>
<div class="ttc" id="aboot__io_8h_html_structos__info__t"><div class="ttname"><a href="boot__io_8h.html#structos__info__t">os_info_t</a></div><div class="ttdef"><b>Definition:</b> boot_io.h:215</div></div>
<div class="ttc" id="aboot__io_8h_html_structpi__regs__t"><div class="ttname"><a href="boot__io_8h.html#structpi__regs__t">pi_regs_t</a></div><div class="ttdoc">Parallel Interface Register Structure.</div><div class="ttdef"><b>Definition:</b> boot_io.h:183</div></div>
<div class="ttc" id="aboot__io_8h_html_structsp__mem__t"><div class="ttname"><a href="boot__io_8h.html#structsp__mem__t">sp_mem_t</a></div><div class="ttdef"><b>Definition:</b> boot_io.h:22</div></div>
<div class="ttc" id="aboot__io_8h_html_structsp__regs__t"><div class="ttname"><a href="boot__io_8h.html#structsp__regs__t">sp_regs_t</a></div><div class="ttdef"><b>Definition:</b> boot_io.h:31</div></div>
<div class="ttc" id="aboot__io_8h_html_structvi__regs__t"><div class="ttname"><a href="boot__io_8h.html#structvi__regs__t">vi_regs_t</a></div><div class="ttdoc">Video Interface Registers Structure.</div><div class="ttdef"><b>Definition:</b> boot_io.h:126</div></div>
<div class="ttc" id="aboot__io_8h_html_structvi__regs__t"><div class="ttname"><a href="boot__io_8h.html#structvi__regs__t">vi_regs_t</a></div><div class="ttdoc">Video Interface Registers Structure.</div><div class="ttdef"><b>Definition:</b> boot_io.h:128</div></div>
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constants_8h.html
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constants_8h_source.html
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crc32_8h.html
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flashcart_8h.html
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flashcart_8h_source.html
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flashcart__utils_8h_source.html
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fonts_8h.html
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functions.html
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functions_vars.html
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globals_enum.html
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globals_eval.html
View File

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globals_func.html
View File

@ -75,7 +75,7 @@ $(function() {
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2
group__sc64.html
View File

@ -260,7 +260,7 @@ FLASHRAM[128]</td>
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Generated on Mon Sep 4 2023 21:34:10 for N64FlashcartMenu by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.9.5
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2
group__view.html
View File

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hdmi_8h_source.html
View File

@ -93,7 +93,7 @@ $(function() {
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index.html
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@ -161,7 +161,7 @@ Open source software and licenses used</h1>
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menu_8h.html
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menu_8h_source.html
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@ -93,7 +93,7 @@ $(function() {
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2
menu__state_8h.html
View File

@ -399,7 +399,7 @@ selected</td>
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menu__state_8h_source.html
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@ -179,7 +179,7 @@ $(function() {
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modules.html
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@ -81,7 +81,7 @@ $(function() {
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mp3__player_8h_source.html
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@ -116,7 +116,7 @@ $(function() {
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path_8h.html
View File

@ -175,7 +175,7 @@ capacity</td>
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Generated on Mon Sep 4 2023 21:34:10 for N64FlashcartMenu by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.9.5
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2
path_8h_source.html
View File

@ -112,7 +112,7 @@ $(function() {
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2
png__decoder_8h_source.html
View File

@ -106,7 +106,7 @@ $(function() {
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rom__database_8h.html
View File

@ -628,7 +628,7 @@ The ROM file release version. </td></tr>
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rom__database_8h_source.html
View File

@ -282,7 +282,7 @@ $(function() {
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sc64_8h.html
View File

@ -95,7 +95,7 @@ Functions</h2></td></tr>
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2
sc64_8h_source.html
View File

@ -93,7 +93,7 @@ $(function() {
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sc64__ll_8h.html
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@ -225,7 +225,7 @@ sc64_error_t&#160;</td><td class="memItemRight" valign="bottom"><b>sc64_ll_flash
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2
sc64__ll_8h_source.html
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settings_8h.html
View File

@ -148,7 +148,7 @@ Put saves into separate directory. </td></tr>
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settings_8h_source.html
View File

@ -105,7 +105,7 @@ $(function() {
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sound_8h.html
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sound_8h_source.html
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structcache__metadata__t.html
View File

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structcomponent__background__t.html
View File

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<!-- start footer part -->
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structcomponent__context__menu__t_8list.html
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structflashcart__t.html
View File

@ -112,7 +112,7 @@ Data Fields</h2></td></tr>
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structipl3__crc32__t.html
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structmp3player__t.html
View File

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structpng__decoder__t.html
View File

@ -221,7 +221,7 @@ void *&#160;</td><td class="memItemRight" valign="bottom"><b>callback_data</b></
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structsc64__cmd__t.html
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structsc64__regs__t.html
View File

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structusb__comm__command__t.html
View File

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usb__comm_8h.html
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usb__comm_8h_source.html
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2
utils_8h_source.html
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views_8h.html
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views_8h_source.html
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Generated on Tue Sep 5 2023 22:49:25 for N64FlashcartMenu by&#160;<a href="https://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.9.5
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