From 25e6a2e0eae3009c2678e8948c2c775d9af43788 Mon Sep 17 00:00:00 2001 From: Alex Barney Date: Mon, 1 Jul 2019 21:39:22 -0500 Subject: [PATCH] Misc cleanup (#708) * Fix typos * Remove unneeded using statements * Enforce var style more * Remove redundant qualifiers * Fix some indentation * Disable naming warnings on files with external enum names * Fix build * Mass find & replace for comments with no spacing * Standardize todo capitalization and for/if spacing --- Decoders/Condition.cs | 4 +-- Decoders/Decoder.cs | 52 ++++++++++++++-------------- Decoders/OpCode32.cs | 4 +-- Decoders/OpCode32BImm.cs | 2 +- Decoders/OpCodeMemImm64.cs | 12 +++---- Decoders/OpCodeSimdImm64.cs | 18 +++++----- Instructions/InstEmit32Helper.cs | 2 +- Instructions/InstEmitAlu.cs | 14 ++++---- Instructions/InstEmitAlu32.cs | 2 +- Instructions/InstEmitAluHelper.cs | 20 +++++------ Instructions/InstEmitBfm.cs | 4 +-- Instructions/InstEmitException.cs | 4 +-- Instructions/InstEmitFlow32.cs | 4 +-- Instructions/InstEmitFlowHelper.cs | 16 ++++----- Instructions/InstEmitMemory.cs | 8 ++--- Instructions/InstEmitMemory32.cs | 22 ++++++------ Instructions/InstEmitMemoryEx.cs | 42 +++++++++++----------- Instructions/InstEmitMemoryHelper.cs | 6 ++-- Instructions/InstEmitSimdHelper.cs | 4 +-- Instructions/InstEmitSimdMemory.cs | 2 +- Instructions/InstEmitSystem.cs | 16 ++++----- Instructions/VectorHelper.cs | 8 ++--- Memory/MemoryManagement.cs | 6 ++-- Memory/MemoryManagementUnix.cs | 14 ++++---- Memory/MemoryManager.cs | 26 +++++++------- OpCodeTable.cs | 18 +++++----- State/CpuThreadState.cs | 4 +-- Translation/ILEmitterCtx.cs | 50 +++++++++++++------------- Translation/RegisterUsage.cs | 4 +-- Translation/TranslatedSub.cs | 12 +++---- Translation/Translator.cs | 10 +++--- Translation/TranslatorCache.cs | 14 ++++---- 32 files changed, 212 insertions(+), 212 deletions(-) diff --git a/Decoders/Condition.cs b/Decoders/Condition.cs index 3f341a9..ef4b295 100644 --- a/Decoders/Condition.cs +++ b/Decoders/Condition.cs @@ -24,8 +24,8 @@ namespace ChocolArm64.Decoders { public static Condition Invert(this Condition cond) { - //Bit 0 of all conditions is basically a negation bit, so - //inverting this bit has the effect of inverting the condition. + // Bit 0 of all conditions is basically a negation bit, so + // inverting this bit has the effect of inverting the condition. return (Condition)((int)cond ^ 1); } } diff --git a/Decoders/Decoder.cs b/Decoders/Decoder.cs index 6a95bc2..a1eeee1 100644 --- a/Decoders/Decoder.cs +++ b/Decoders/Decoder.cs @@ -29,12 +29,12 @@ namespace ChocolArm64.Decoders if (IsBranch(lastOp) && !IsCall(lastOp) && lastOp is IOpCodeBImm op) { - //It's possible that the branch on this block lands on the middle of the block. - //This is more common on tight loops. In this case, we can improve the codegen - //a bit by changing the CFG and either making the branch point to the same block - //(which indicates that the block is a loop that jumps back to the start), and the - //other possible case is a jump somewhere on the middle of the block, which is - //also a loop, but in this case we need to split the block in half. + // It's possible that the branch on this block lands on the middle of the block. + // This is more common on tight loops. In this case, we can improve the codegen + // a bit by changing the CFG and either making the branch point to the same block + // (which indicates that the block is a loop that jumps back to the start), and the + // other possible case is a jump somewhere on the middle of the block, which is + // also a loop, but in this case we need to split the block in half. if ((ulong)op.Imm == address) { block.Branch = block; @@ -79,7 +79,7 @@ namespace ChocolArm64.Decoders while (workQueue.TryDequeue(out Block currBlock)) { - //Check if the current block is inside another block. + // Check if the current block is inside another block. if (BinarySearch(blocks, currBlock.Address, out int nBlkIndex)) { Block nBlock = blocks[nBlkIndex]; @@ -96,7 +96,7 @@ namespace ChocolArm64.Decoders continue; } - //If we have a block after the current one, set the limit address. + // If we have a block after the current one, set the limit address. ulong limitAddress = ulong.MaxValue; if (nBlkIndex != blocks.Count) @@ -119,10 +119,10 @@ namespace ChocolArm64.Decoders if (currBlock.OpCodes.Count != 0) { - //Set child blocks. "Branch" is the block the branch instruction - //points to (when taken), "Next" is the block at the next address, - //executed when the branch is not taken. For Unconditional Branches - //(except BL/BLR that are sub calls) or end of executable, Next is null. + // Set child blocks. "Branch" is the block the branch instruction + // points to (when taken), "Next" is the block at the next address, + // executed when the branch is not taken. For Unconditional Branches + // (except BL/BLR that are sub calls) or end of executable, Next is null. OpCode64 lastOp = currBlock.GetLastOp(); bool isCall = IsCall(lastOp); @@ -138,7 +138,7 @@ namespace ChocolArm64.Decoders } } - //Insert the new block on the list (sorted by address). + // Insert the new block on the list (sorted by address). if (blocks.Count != 0) { Block nBlock = blocks[nBlkIndex]; @@ -236,25 +236,25 @@ namespace ChocolArm64.Decoders return false; } - //Note: On ARM32, most instructions have conditional execution, - //so there's no "Always" (unconditional) branch like on ARM64. - //We need to check if the condition is "Always" instead. + // Note: On ARM32, most instructions have conditional execution, + // so there's no "Always" (unconditional) branch like on ARM64. + // We need to check if the condition is "Always" instead. return IsAarch32Branch(op) && op.Cond >= Condition.Al; } private static bool IsAarch32Branch(OpCode64 opCode) { - //Note: On ARM32, most ALU operations can write to R15 (PC), - //so we must consider such operations as a branch in potential aswell. + // Note: On ARM32, most ALU operations can write to R15 (PC), + // so we must consider such operations as a branch in potential as well. if (opCode is IOpCode32Alu opAlu && opAlu.Rd == RegisterAlias.Aarch32Pc) { return true; } - //Same thing for memory operations. We have the cases where PC is a target - //register (Rt == 15 or (mask & (1 << 15)) != 0), and cases where there is - //a write back to PC (wback == true && Rn == 15), however the later may - //be "undefined" depending on the CPU, so compilers should not produce that. + // Same thing for memory operations. We have the cases where PC is a target + // register (Rt == 15 or (mask & (1 << 15)) != 0), and cases where there is + // a write back to PC (wback == true && Rn == 15), however the later may + // be "undefined" depending on the CPU, so compilers should not produce that. if (opCode is IOpCode32Mem || opCode is IOpCode32MemMult) { int rt, rn; @@ -268,8 +268,8 @@ namespace ChocolArm64.Decoders wBack = opMem.WBack; isLoad = opMem.IsLoad; - //For the dual load, we also need to take into account the - //case were Rt2 == 15 (PC). + // For the dual load, we also need to take into account the + // case were Rt2 == 15 (PC). if (rt == 14 && opMem.Emitter == InstEmit32.Ldrd) { rt = RegisterAlias.Aarch32Pc; @@ -296,14 +296,14 @@ namespace ChocolArm64.Decoders } } - //Explicit branch instructions. + // Explicit branch instructions. return opCode is IOpCode32BImm || opCode is IOpCode32BReg; } private static bool IsCall(OpCode64 opCode) { - //TODO (CQ): ARM32 support. + // TODO (CQ): ARM32 support. return opCode.Emitter == InstEmit.Bl || opCode.Emitter == InstEmit.Blr; } diff --git a/Decoders/OpCode32.cs b/Decoders/OpCode32.cs index 8534b78..1909757 100644 --- a/Decoders/OpCode32.cs +++ b/Decoders/OpCode32.cs @@ -16,8 +16,8 @@ namespace ChocolArm64.Decoders public uint GetPc() { - //Due to backwards compatibility and legacy behavior of ARMv4 CPUs pipeline, - //the PC actually points 2 instructions ahead. + // Due to backwards compatibility and legacy behavior of ARMv4 CPUs pipeline, + // the PC actually points 2 instructions ahead. return (uint)Position + (uint)OpCodeSizeInBytes * 2; } } diff --git a/Decoders/OpCode32BImm.cs b/Decoders/OpCode32BImm.cs index 43f191e..7f3c29a 100644 --- a/Decoders/OpCode32BImm.cs +++ b/Decoders/OpCode32BImm.cs @@ -10,7 +10,7 @@ namespace ChocolArm64.Decoders { uint pc = GetPc(); - //When the codition is never, the instruction is BLX to Thumb mode. + // When the condition is never, the instruction is BLX to Thumb mode. if (Cond != Condition.Nv) { pc &= ~3u; diff --git a/Decoders/OpCodeMemImm64.cs b/Decoders/OpCodeMemImm64.cs index d9f322e..01a62ef 100644 --- a/Decoders/OpCodeMemImm64.cs +++ b/Decoders/OpCodeMemImm64.cs @@ -23,16 +23,16 @@ namespace ChocolArm64.Decoders Extend64 = ((opCode >> 22) & 3) == 2; WBack = ((opCode >> 24) & 1) == 0; - //The type is not valid for the Unsigned Immediate 12-bits encoding, - //because the bits 11:10 are used for the larger Immediate offset. + // The type is not valid for the Unsigned Immediate 12-bits encoding, + // because the bits 11:10 are used for the larger Immediate offset. MemOp type = WBack ? (MemOp)((opCode >> 10) & 3) : MemOp.Unsigned; PostIdx = type == MemOp.PostIndexed; Unscaled = type == MemOp.Unscaled || type == MemOp.Unprivileged; - //Unscaled and Unprivileged doesn't write back, - //but they do use the 9-bits Signed Immediate. + // Unscaled and Unprivileged doesn't write back, + // but they do use the 9-bits Signed Immediate. if (Unscaled) { WBack = false; @@ -40,12 +40,12 @@ namespace ChocolArm64.Decoders if (WBack || Unscaled) { - //9-bits Signed Immediate. + // 9-bits Signed Immediate. Imm = (opCode << 11) >> 23; } else { - //12-bits Unsigned Immediate. + // 12-bits Unsigned Immediate. Imm = ((opCode >> 10) & 0xfff) << Size; } } diff --git a/Decoders/OpCodeSimdImm64.cs b/Decoders/OpCodeSimdImm64.cs index 37ee504..27f586f 100644 --- a/Decoders/OpCodeSimdImm64.cs +++ b/Decoders/OpCodeSimdImm64.cs @@ -30,14 +30,14 @@ namespace ChocolArm64.Decoders switch (op | (modeLow << 1)) { case 0: - //64-bits Immediate. - //Transform abcd efgh into abcd efgh abcd efgh ... + // 64-bits Immediate. + // Transform abcd efgh into abcd efgh abcd efgh ... imm = (long)((ulong)imm * 0x0101010101010101); break; case 1: - //64-bits Immediate. - //Transform abcd efgh into aaaa aaaa bbbb bbbb ... + // 64-bits Immediate. + // Transform abcd efgh into aaaa aaaa bbbb bbbb ... imm = (imm & 0xf0) >> 4 | (imm & 0x0f) << 4; imm = (imm & 0xcc) >> 2 | (imm & 0x33) << 2; imm = (imm & 0xaa) >> 1 | (imm & 0x55) << 1; @@ -52,29 +52,29 @@ namespace ChocolArm64.Decoders case 2: case 3: - //Floating point Immediate. + // Floating point Immediate. imm = DecoderHelper.DecodeImm8Float(imm, Size); break; } } else if ((modeHigh & 0b110) == 0b100) { - //16-bits shifted Immediate. + // 16-bits shifted Immediate. Size = 1; imm <<= (modeHigh & 1) << 3; } else if ((modeHigh & 0b100) == 0b000) { - //32-bits shifted Immediate. + // 32-bits shifted Immediate. Size = 2; imm <<= modeHigh << 3; } else if ((modeHigh & 0b111) == 0b110) { - //32-bits shifted Immediate (fill with ones). + // 32-bits shifted Immediate (fill with ones). Size = 2; imm = ShlOnes(imm, 8 << modeLow); } else { - //8 bits without shift. + // 8 bits without shift. Size = 0; } diff --git a/Instructions/InstEmit32Helper.cs b/Instructions/InstEmit32Helper.cs index 4937798..c5d08b8 100644 --- a/Instructions/InstEmit32Helper.cs +++ b/Instructions/InstEmit32Helper.cs @@ -24,7 +24,7 @@ namespace ChocolArm64.Instructions } else { - context.EmitLdint(InstEmit32Helper.GetRegisterAlias(context.Mode, register)); + context.EmitLdint(GetRegisterAlias(context.Mode, register)); } } diff --git a/Instructions/InstEmitAlu.cs b/Instructions/InstEmitAlu.cs index 36ce8c7..25bd8e6 100644 --- a/Instructions/InstEmitAlu.cs +++ b/Instructions/InstEmitAlu.cs @@ -151,7 +151,7 @@ namespace ChocolArm64.Instructions public static void Extr(ILEmitterCtx context) { - //TODO: Ensure that the Shift is valid for the Is64Bits. + // TODO: Ensure that the Shift is valid for the Is64Bits. OpCodeAluRs64 op = (OpCodeAluRs64)context.CurrOp; context.EmitLdintzr(op.Rm); @@ -309,7 +309,7 @@ namespace ChocolArm64.Instructions private static void EmitDiv(ILEmitterCtx context, OpCode ilOp) { - //If Rm == 0, Rd = 0 (division by zero). + // If Rm == 0, Rd = 0 (division by zero). context.EmitLdc_I(0); EmitAluLoadRm(context); @@ -323,7 +323,7 @@ namespace ChocolArm64.Instructions if (ilOp == OpCodes.Div) { - //If Rn == INT_MIN && Rm == -1, Rd = INT_MIN (overflow). + // If Rn == INT_MIN && Rm == -1, Rd = INT_MIN (overflow). long intMin = 1L << (context.CurrOp.GetBitsCount() - 1); context.EmitLdc_I(intMin); @@ -381,10 +381,10 @@ namespace ChocolArm64.Instructions context.Emit(OpCodes.And); - //Note: Only 32-bits shift values are valid, so when the value is 64-bits - //we need to cast it to a 32-bits integer. This is fine because we - //AND the value and only keep the lower 5 or 6 bits anyway -- it - //could very well fit on a byte. + // Note: Only 32-bits shift values are valid, so when the value is 64-bits + // we need to cast it to a 32-bits integer. This is fine because we + // AND the value and only keep the lower 5 or 6 bits anyway -- it + // could very well fit on a byte. if (context.CurrOp.RegisterSize != RegisterSize.Int32) { context.Emit(OpCodes.Conv_I4); diff --git a/Instructions/InstEmitAlu32.cs b/Instructions/InstEmitAlu32.cs index 0b4bac2..94a8c75 100644 --- a/Instructions/InstEmitAlu32.cs +++ b/Instructions/InstEmitAlu32.cs @@ -87,7 +87,7 @@ namespace ChocolArm64.Instructions { if (op.SetFlags) { - //TODO: Load SPSR etc. + // TODO: Load SPSR etc. context.EmitLdflg((int)PState.TBit); diff --git a/Instructions/InstEmitAluHelper.cs b/Instructions/InstEmitAluHelper.cs index 181f645..6482208 100644 --- a/Instructions/InstEmitAluHelper.cs +++ b/Instructions/InstEmitAluHelper.cs @@ -10,7 +10,7 @@ namespace ChocolArm64.Instructions { public static void EmitAdcsCCheck(ILEmitterCtx context) { - //C = (Rd == Rn && CIn) || Rd < Rn + // C = (Rd == Rn && CIn) || Rd < Rn context.EmitSttmp(); context.EmitLdtmp(); context.EmitLdtmp(); @@ -35,7 +35,7 @@ namespace ChocolArm64.Instructions public static void EmitAddsCCheck(ILEmitterCtx context) { - //C = Rd < Rn + // C = Rd < Rn context.Emit(OpCodes.Dup); EmitAluLoadRn(context); @@ -47,7 +47,7 @@ namespace ChocolArm64.Instructions public static void EmitAddsVCheck(ILEmitterCtx context) { - //V = (Rd ^ Rn) & ~(Rn ^ Rm) < 0 + // V = (Rd ^ Rn) & ~(Rn ^ Rm) < 0 context.Emit(OpCodes.Dup); EmitAluLoadRn(context); @@ -69,7 +69,7 @@ namespace ChocolArm64.Instructions public static void EmitSbcsCCheck(ILEmitterCtx context) { - //C = (Rn == Rm && CIn) || Rn > Rm + // C = (Rn == Rm && CIn) || Rn > Rm EmitAluLoadOpers(context); context.Emit(OpCodes.Ceq); @@ -88,7 +88,7 @@ namespace ChocolArm64.Instructions public static void EmitSubsCCheck(ILEmitterCtx context) { - //C = Rn == Rm || Rn > Rm = !(Rn < Rm) + // C = Rn == Rm || Rn > Rm = !(Rn < Rm) EmitAluLoadOpers(context); context.Emit(OpCodes.Clt_Un); @@ -102,7 +102,7 @@ namespace ChocolArm64.Instructions public static void EmitSubsVCheck(ILEmitterCtx context) { - //V = (Rd ^ Rn) & (Rn ^ Rm) < 0 + // V = (Rd ^ Rn) & (Rn ^ Rm) < 0 context.Emit(OpCodes.Dup); EmitAluLoadRn(context); @@ -170,7 +170,7 @@ namespace ChocolArm64.Instructions { switch (context.CurrOp) { - //ARM32. + // ARM32. case OpCode32AluImm op: context.EmitLdc_I4(op.Imm); @@ -190,7 +190,7 @@ namespace ChocolArm64.Instructions context.EmitLdc_I4(op.Imm); break; - //ARM64. + // ARM64. case IOpCodeAluImm64 op: context.EmitLdc_I(op.Imm); break; @@ -245,7 +245,7 @@ namespace ChocolArm64.Instructions context.EmitStflg((int)PState.NBit); } - //ARM32 helpers. + // ARM32 helpers. private static void EmitLoadRmShiftedByImmediate(ILEmitterCtx context, OpCode32AluRsImm op, bool setCarry) { int shift = op.Imm; @@ -432,7 +432,7 @@ namespace ChocolArm64.Instructions private static void EmitRrxC(ILEmitterCtx context, bool setCarry) { - //Rotate right by 1 with carry. + // Rotate right by 1 with carry. if (setCarry) { context.Emit(OpCodes.Dup); diff --git a/Instructions/InstEmitBfm.cs b/Instructions/InstEmitBfm.cs index 4a03959..75e259c 100644 --- a/Instructions/InstEmitBfm.cs +++ b/Instructions/InstEmitBfm.cs @@ -13,7 +13,7 @@ namespace ChocolArm64.Instructions if (op.Pos < op.Shift) { - //BFI. + // BFI. context.EmitLdintzr(op.Rn); int shift = op.GetBitsCount() - op.Shift; @@ -39,7 +39,7 @@ namespace ChocolArm64.Instructions } else { - //BFXIL. + // BFXIL. context.EmitLdintzr(op.Rn); context.EmitLsr(op.Shift); diff --git a/Instructions/InstEmitException.cs b/Instructions/InstEmitException.cs index 7922c62..c835fb0 100644 --- a/Instructions/InstEmitException.cs +++ b/Instructions/InstEmitException.cs @@ -31,8 +31,8 @@ namespace ChocolArm64.Instructions context.EmitPrivateCall(typeof(CpuThreadState), mthdName); - //Check if the thread should still be running, if it isn't then we return 0 - //to force a return to the dispatcher and then exit the thread. + // Check if the thread should still be running, if it isn't then we return 0 + // to force a return to the dispatcher and then exit the thread. context.EmitLdarg(TranslatedSub.StateArgIdx); context.EmitCallPropGet(typeof(CpuThreadState), nameof(CpuThreadState.Running)); diff --git a/Instructions/InstEmitFlow32.cs b/Instructions/InstEmitFlow32.cs index b0b9754..133e278 100644 --- a/Instructions/InstEmitFlow32.cs +++ b/Instructions/InstEmitFlow32.cs @@ -66,8 +66,8 @@ namespace ChocolArm64.Instructions context.EmitStint(GetBankedRegisterAlias(context.Mode, RegisterAlias.Aarch32Lr)); - //If x is true, then this is a branch with link and exchange. - //In this case we need to swap the mode between Arm <-> Thumb. + // If x is true, then this is a branch with link and exchange. + // In this case we need to swap the mode between Arm <-> Thumb. if (x) { context.EmitLdc_I4(isThumb ? 0 : 1); diff --git a/Instructions/InstEmitFlowHelper.cs b/Instructions/InstEmitFlowHelper.cs index e7a6bf3..f36fe5a 100644 --- a/Instructions/InstEmitFlowHelper.cs +++ b/Instructions/InstEmitFlowHelper.cs @@ -90,10 +90,10 @@ namespace ChocolArm64.Instructions if (isJump) { - //The tail prefix allows the JIT to jump to the next function, - //while releasing the stack space used by the current one. - //This is ideal for BR ARM instructions, which are - //basically indirect tail calls. + // The tail prefix allows the JIT to jump to the next function, + // while releasing the stack space used by the current one. + // This is ideal for BR ARM instructions, which are + // basically indirect tail calls. context.Emit(OpCodes.Tailcall); } @@ -114,10 +114,10 @@ namespace ChocolArm64.Instructions private static void EmitContinueOrReturnCheck(ILEmitterCtx context) { - //Note: The return value of the called method will be placed - //at the Stack, the return value is always a Int64 with the - //return address of the function. We check if the address is - //correct, if it isn't we keep returning until we reach the dispatcher. + // Note: The return value of the called method will be placed + // at the Stack, the return value is always a Int64 with the + // return address of the function. We check if the address is + // correct, if it isn't we keep returning until we reach the dispatcher. if (context.CurrBlock.Next != null) { context.Emit(OpCodes.Dup); diff --git a/Instructions/InstEmitMemory.cs b/Instructions/InstEmitMemory.cs index ea779c8..1328f39 100644 --- a/Instructions/InstEmitMemory.cs +++ b/Instructions/InstEmitMemory.cs @@ -192,7 +192,7 @@ namespace ChocolArm64.Instructions if (!op.PostIdx) { - //Pre-indexing. + // Pre-indexing. context.EmitLdc_I(op.Imm); context.Emit(OpCodes.Add); @@ -213,7 +213,7 @@ namespace ChocolArm64.Instructions break; } - //Save address to Scratch var since the register value may change. + // Save address to Scratch var since the register value may change. context.Emit(OpCodes.Dup); context.EmitSttmp(); @@ -221,8 +221,8 @@ namespace ChocolArm64.Instructions private static void EmitWBackIfNeeded(ILEmitterCtx context) { - //Check whenever the current OpCode has post-indexed write back, if so write it. - //Note: AOpCodeMemPair inherits from AOpCodeMemImm, so this works for both. + // Check whenever the current OpCode has post-indexed write back, if so write it. + // Note: AOpCodeMemPair inherits from AOpCodeMemImm, so this works for both. if (context.CurrOp is OpCodeMemImm64 op && op.WBack) { context.EmitLdtmp(); diff --git a/Instructions/InstEmitMemory32.cs b/Instructions/InstEmitMemory32.cs index 647d575..807a65f 100644 --- a/Instructions/InstEmitMemory32.cs +++ b/Instructions/InstEmitMemory32.cs @@ -137,15 +137,15 @@ namespace ChocolArm64.Instructions EmitWriteCall(context, WordSizeLog2); - //Note: If Rn is also specified on the register list, - //and Rn is the first register on this list, then the - //value that is written to memory is the unmodified value, - //before the write back. If it is on the list, but it's - //not the first one, then the value written to memory - //varies between CPUs. + // Note: If Rn is also specified on the register list, + // and Rn is the first register on this list, then the + // value that is written to memory is the unmodified value, + // before the write back. If it is on the list, but it's + // not the first one, then the value written to memory + // varies between CPUs. if (offset == 0 && op.PostOffset != 0) { - //Emit write back after the first write. + // Emit write back after the first write. EmitLoadFromRegister(context, op.Rn); context.EmitLdc_I4(op.PostOffset); @@ -233,7 +233,7 @@ namespace ChocolArm64.Instructions context.Emit(OpCodes.Brtrue_S, lblBigEndian); - //Little endian mode. + // Little endian mode. context.Emit(OpCodes.Conv_U4); EmitStoreToRegister(context, op.Rt); @@ -246,7 +246,7 @@ namespace ChocolArm64.Instructions context.Emit(OpCodes.Br_S, lblEnd); - //Big endian mode. + // Big endian mode. context.MarkLabel(lblBigEndian); context.EmitLsr(32); @@ -288,7 +288,7 @@ namespace ChocolArm64.Instructions context.Emit(OpCodes.Brtrue_S, lblBigEndian); - //Little endian mode. + // Little endian mode. EmitLoadFromRegister(context, op.Rt | 1); context.Emit(OpCodes.Conv_U8); @@ -299,7 +299,7 @@ namespace ChocolArm64.Instructions context.Emit(OpCodes.Br_S, lblEnd); - //Big endian mode. + // Big endian mode. context.MarkLabel(lblBigEndian); context.EmitLsl(32); diff --git a/Instructions/InstEmitMemoryEx.cs b/Instructions/InstEmitMemoryEx.cs index 329fba7..5deb035 100644 --- a/Instructions/InstEmitMemoryEx.cs +++ b/Instructions/InstEmitMemoryEx.cs @@ -89,10 +89,10 @@ namespace ChocolArm64.Instructions if (pair) { - //Exclusive loads should be atomic. For pairwise loads, we need to - //read all the data at once. For a 32-bits pairwise load, we do a - //simple 64-bits load, for a 128-bits load, we need to call a special - //method to read 128-bits atomically. + // Exclusive loads should be atomic. For pairwise loads, we need to + // read all the data at once. For a 32-bits pairwise load, we do a + // simple 64-bits load, for a 128-bits load, we need to call a special + // method to read 128-bits atomically. if (op.Size == 2) { context.EmitLdtmp(); @@ -101,7 +101,7 @@ namespace ChocolArm64.Instructions context.Emit(OpCodes.Dup); - //Mask low half. + // Mask low half. context.Emit(OpCodes.Conv_U4); if (exclusive) @@ -111,7 +111,7 @@ namespace ChocolArm64.Instructions context.EmitStintzr(op.Rt); - //Shift high half. + // Shift high half. context.EmitLsr(32); context.Emit(OpCodes.Conv_U4); @@ -131,7 +131,7 @@ namespace ChocolArm64.Instructions context.Emit(OpCodes.Dup); - //Load low part of the vector. + // Load low part of the vector. context.EmitLdc_I4(0); context.EmitLdc_I4(3); @@ -144,7 +144,7 @@ namespace ChocolArm64.Instructions context.EmitStintzr(op.Rt); - //Load high part of the vector. + // Load high part of the vector. context.EmitLdc_I4(1); context.EmitLdc_I4(3); @@ -164,7 +164,7 @@ namespace ChocolArm64.Instructions } else { - //8, 16, 32 or 64-bits (non-pairwise) load. + // 8, 16, 32 or 64-bits (non-pairwise) load. context.EmitLdtmp(); EmitReadZxCall(context, op.Size); @@ -180,7 +180,7 @@ namespace ChocolArm64.Instructions public static void Pfrm(ILEmitterCtx context) { - //Memory Prefetch, execute as no-op. + // Memory Prefetch, execute as no-op. } public static void Stlr(ILEmitterCtx context) => EmitStr(context, AccessType.Ordered); @@ -223,13 +223,13 @@ namespace ChocolArm64.Instructions context.Emit(OpCodes.Brtrue_S, lblEx); - //Address check failed, set error right away and do not store anything. + // Address check failed, set error right away and do not store anything. context.EmitLdc_I4(1); context.EmitStintzr(op.Rs); context.Emit(OpCodes.Br, lblEnd); - //Address check passsed. + // Address check passed. context.MarkLabel(lblEx); context.EmitLdarg(TranslatedSub.MemoryArgIdx); @@ -241,7 +241,7 @@ namespace ChocolArm64.Instructions void EmitCast() { - //The input should be always int64. + // The input should be always int64. switch (op.Size) { case 0: context.Emit(OpCodes.Conv_U1); break; @@ -293,10 +293,10 @@ namespace ChocolArm64.Instructions } } - //The value returned is a bool, true if the values compared - //were equal and the new value was written, false otherwise. - //We need to invert this result, as on ARM 1 indicates failure, - //and 0 success on those instructions. + // The value returned is a bool, true if the values compared + // were equal and the new value was written, false otherwise. + // We need to invert this result, as on ARM 1 indicates failure, + // and 0 success on those instructions. context.EmitLdc_I4(1); context.Emit(OpCodes.Xor); @@ -305,7 +305,7 @@ namespace ChocolArm64.Instructions context.EmitStintzr(op.Rs); - //Only clear the exclusive monitor if the store was successful (Rs = false). + // Only clear the exclusive monitor if the store was successful (Rs = false). context.Emit(OpCodes.Brtrue_S, lblEnd); Clrex(context); @@ -341,9 +341,9 @@ namespace ChocolArm64.Instructions private static void EmitBarrier(ILEmitterCtx context) { - //Note: This barrier is most likely not necessary, and probably - //doesn't make any difference since we need to do a ton of stuff - //(software MMU emulation) to read or write anything anyway. + // Note: This barrier is most likely not necessary, and probably + // doesn't make any difference since we need to do a ton of stuff + // (software MMU emulation) to read or write anything anyway. context.EmitCall(typeof(Thread), nameof(Thread.MemoryBarrier)); } } diff --git a/Instructions/InstEmitMemoryHelper.cs b/Instructions/InstEmitMemoryHelper.cs index 4dc40b1..dbb5888 100644 --- a/Instructions/InstEmitMemoryHelper.cs +++ b/Instructions/InstEmitMemoryHelper.cs @@ -40,7 +40,7 @@ namespace ChocolArm64.Instructions private static void EmitReadCall(ILEmitterCtx context, Extension ext, int size) { - //Save the address into a temp. + // Save the address into a temp. context.EmitStint(_tempIntAddress); bool isSimd = IsSimd(context); @@ -99,7 +99,7 @@ namespace ChocolArm64.Instructions { bool isSimd = IsSimd(context); - //Save the value into a temp. + // Save the value into a temp. if (isSimd) { context.EmitStvec(_tempVecValue); @@ -109,7 +109,7 @@ namespace ChocolArm64.Instructions context.EmitStint(_tempIntValue); } - //Save the address into a temp. + // Save the address into a temp. context.EmitStint(_tempIntAddress); if (size < 0 || size > (isSimd ? 4 : 3)) diff --git a/Instructions/InstEmitSimdHelper.cs b/Instructions/InstEmitSimdHelper.cs index f343dba..573b804 100644 --- a/Instructions/InstEmitSimdHelper.cs +++ b/Instructions/InstEmitSimdHelper.cs @@ -1298,8 +1298,8 @@ namespace ChocolArm64.Instructions { if (Optimizations.UseSse41 && size == 0) { - //If the type is float, we can perform insertion and - //zero the upper bits with a single instruction (INSERTPS); + // If the type is float, we can perform insertion and + // zero the upper bits with a single instruction (INSERTPS); context.EmitLdvec(reg); VectorHelper.EmitCall(context, nameof(VectorHelper.Sse41VectorInsertScalarSingle)); diff --git a/Instructions/InstEmitSimdMemory.cs b/Instructions/InstEmitSimdMemory.cs index 18ec1d3..073b0f0 100644 --- a/Instructions/InstEmitSimdMemory.cs +++ b/Instructions/InstEmitSimdMemory.cs @@ -96,7 +96,7 @@ namespace ChocolArm64.Instructions if (op.Replicate) { - //Only loads uses the replicate mode. + // Only loads uses the replicate mode. if (!isLoad) { throw new InvalidOperationException(); diff --git a/Instructions/InstEmitSystem.cs b/Instructions/InstEmitSystem.cs index 5687768..d0d60b9 100644 --- a/Instructions/InstEmitSystem.cs +++ b/Instructions/InstEmitSystem.cs @@ -11,12 +11,12 @@ namespace ChocolArm64.Instructions { public static void Hint(ILEmitterCtx context) { - //Execute as no-op. + // Execute as no-op. } public static void Isb(ILEmitterCtx context) { - //Execute as no-op. + // Execute as no-op. } public static void Mrs(ILEmitterCtx context) @@ -85,21 +85,21 @@ namespace ChocolArm64.Instructions public static void Nop(ILEmitterCtx context) { - //Do nothing. + // Do nothing. } public static void Sys(ILEmitterCtx context) { - //This instruction is used to do some operations on the CPU like cache invalidation, - //address translation and the like. - //We treat it as no-op here since we don't have any cache being emulated anyway. + // This instruction is used to do some operations on the CPU like cache invalidation, + // address translation and the like. + // We treat it as no-op here since we don't have any cache being emulated anyway. OpCodeSystem64 op = (OpCodeSystem64)context.CurrOp; switch (GetPackedId(op)) { case 0b11_011_0111_0100_001: { - //DC ZVA + // DC ZVA for (int offs = 0; offs < (4 << CpuThreadState.DczSizeLog2); offs += 8) { context.EmitLdintzr(op.Rt); @@ -115,7 +115,7 @@ namespace ChocolArm64.Instructions break; } - //No-op + // No-op case 0b11_011_0111_1110_001: //DC CIVAC break; } diff --git a/Instructions/VectorHelper.cs b/Instructions/VectorHelper.cs index 3e2b258..4d57e28 100644 --- a/Instructions/VectorHelper.cs +++ b/Instructions/VectorHelper.cs @@ -583,9 +583,9 @@ namespace ChocolArm64.Instructions { if (Sse41.IsSupported) { - //Note: The if/else if is necessary to enable the JIT to - //produce a single INSERTPS instruction instead of the - //jump table fallback. + // Note: The if/else if is necessary to enable the JIT to + // produce a single INSERTPS instruction instead of the + // jump table fallback. if (index == 0) { return Sse41.Insert(vector, value, 0x00); @@ -628,7 +628,7 @@ namespace ChocolArm64.Instructions [MethodImpl(MethodImplOptions.AggressiveInlining)] public static Vector128 Sse41VectorInsertScalarSingle(float value, Vector128 vector) { - //Note: 0b1110 is the mask to zero the upper bits. + // Note: 0b1110 is the mask to zero the upper bits. return Sse41.Insert(vector, value, 0b1110); } diff --git a/Memory/MemoryManagement.cs b/Memory/MemoryManagement.cs index fa4bc4f..8058579 100644 --- a/Memory/MemoryManagement.cs +++ b/Memory/MemoryManagement.cs @@ -96,9 +96,9 @@ namespace ChocolArm64.Memory IntPtr[] addresses, out ulong count) { - //This is only supported on windows, but returning - //false (failed) is also valid for platforms without - //write tracking support on the OS. + // This is only supported on windows, but returning + // false (failed) is also valid for platforms without + // write tracking support on the OS. if (RuntimeInformation.IsOSPlatform(OSPlatform.Windows)) { return MemoryManagementWindows.GetModifiedPages(address, size, addresses, out count); diff --git a/Memory/MemoryManagementUnix.cs b/Memory/MemoryManagementUnix.cs index 9fe1aef..fe3cfb7 100644 --- a/Memory/MemoryManagementUnix.cs +++ b/Memory/MemoryManagementUnix.cs @@ -30,22 +30,22 @@ namespace ChocolArm64.Memory return ptr; } - public static bool Reprotect(IntPtr address, ulong size, Memory.MemoryProtection protection) + public static bool Reprotect(IntPtr address, ulong size, MemoryProtection protection) { MmapProts prot = GetProtection(protection); return Syscall.mprotect(address, size, prot) == 0; } - private static MmapProts GetProtection(Memory.MemoryProtection protection) + private static MmapProts GetProtection(MemoryProtection protection) { switch (protection) { - case Memory.MemoryProtection.None: return MmapProts.PROT_NONE; - case Memory.MemoryProtection.Read: return MmapProts.PROT_READ; - case Memory.MemoryProtection.ReadAndWrite: return MmapProts.PROT_READ | MmapProts.PROT_WRITE; - case Memory.MemoryProtection.ReadAndExecute: return MmapProts.PROT_READ | MmapProts.PROT_EXEC; - case Memory.MemoryProtection.Execute: return MmapProts.PROT_EXEC; + case MemoryProtection.None: return MmapProts.PROT_NONE; + case MemoryProtection.Read: return MmapProts.PROT_READ; + case MemoryProtection.ReadAndWrite: return MmapProts.PROT_READ | MmapProts.PROT_WRITE; + case MemoryProtection.ReadAndExecute: return MmapProts.PROT_READ | MmapProts.PROT_EXEC; + case MemoryProtection.Execute: return MmapProts.PROT_EXEC; default: throw new ArgumentException($"Invalid permission \"{protection}\"."); } diff --git a/Memory/MemoryManager.cs b/Memory/MemoryManager.cs index ce102e0..364f6b5 100644 --- a/Memory/MemoryManager.cs +++ b/Memory/MemoryManager.cs @@ -50,12 +50,12 @@ namespace ChocolArm64.Memory AddressSpaceBits = addressSpaceBits; AddressSpaceSize = 1L << addressSpaceBits; - //When flat page table is requested, we use a single - //array for the mappings of the entire address space. - //This has better performance, but also high memory usage. - //The multi level page table uses 9 bits per level, so - //the memory usage is lower, but the performance is also - //lower, since each address translation requires multiple reads. + // When flat page table is requested, we use a single + // array for the mappings of the entire address space. + // This has better performance, but also high memory usage. + // The multi level page table uses 9 bits per level, so + // the memory usage is lower, but the performance is also + // lower, since each address translation requires multiple reads. if (useFlatPageTable) { PtLevelBits = addressSpaceBits - PageBits; @@ -237,13 +237,13 @@ namespace ChocolArm64.Memory if (nextPtr == IntPtr.Zero) { - //Entry does not yet exist, allocate a new one. + // Entry does not yet exist, allocate a new one. IntPtr newPtr = Allocate((ulong)(PtLevelSize * IntPtr.Size)); - //Try to swap the current pointer (should be zero), with the allocated one. + // Try to swap the current pointer (should be zero), with the allocated one. nextPtr = Interlocked.Exchange(ref *ptePtr, newPtr); - //If the old pointer is not null, then another thread already has set it. + // If the old pointer is not null, then another thread already has set it. if (nextPtr != IntPtr.Zero) { Free(newPtr); @@ -533,7 +533,7 @@ namespace ChocolArm64.Memory private void AbortWithAlignmentFault(long position) { - //TODO: Abort mode and exception support on the CPU. + // TODO: Abort mode and exception support on the CPU. throw new InvalidOperationException($"Tried to compare exchange a misaligned address 0x{position:X16}."); } @@ -726,7 +726,7 @@ namespace ChocolArm64.Memory public void ReadBytes(long position, byte[] data, int startIndex, int size) { - //Note: This will be moved later. + // Note: This will be moved later. long endAddr = position + size; if ((ulong)size > int.MaxValue) @@ -924,7 +924,7 @@ namespace ChocolArm64.Memory public void WriteBytes(long position, byte[] data, int startIndex, int size) { - //Note: This will be moved later. + // Note: This will be moved later. long endAddr = position + size; if ((ulong)endAddr < (ulong)position) @@ -954,7 +954,7 @@ namespace ChocolArm64.Memory public void CopyBytes(long src, long dst, long size) { - //Note: This will be moved later. + // Note: This will be moved later. if (IsContiguous(src, size) && IsContiguous(dst, size)) { diff --git a/OpCodeTable.cs b/OpCodeTable.cs index 74cbdab..819881e 100644 --- a/OpCodeTable.cs +++ b/OpCodeTable.cs @@ -36,7 +36,7 @@ namespace ChocolArm64 static OpCodeTable() { #region "OpCode Table (AArch32)" - //Integer + // Integer SetA32("<<<<0010100xxxxxxxxxxxxxxxxxxxxx", InstEmit32.Add, typeof(OpCode32AluImm)); SetA32("<<<<0000100xxxxxxxxxxxxxxxx0xxxx", InstEmit32.Add, typeof(OpCode32AluRsImm)); SetA32("<<<<1010xxxxxxxxxxxxxxxxxxxxxxxx", InstEmit32.B, typeof(OpCode32BImm)); @@ -66,7 +66,7 @@ namespace ChocolArm64 #endregion #region "OpCode Table (AArch64)" - //Integer + // Integer SetA64("x0011010000xxxxx000000xxxxxxxxxx", InstEmit.Adc, typeof(OpCodeAluRs64)); SetA64("x0111010000xxxxx000000xxxxxxxxxx", InstEmit.Adcs, typeof(OpCodeAluRs64)); SetA64("x00100010xxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Add, typeof(OpCodeAluImm64)); @@ -217,7 +217,7 @@ namespace ChocolArm64 SetA64("10011011101xxxxx1xxxxxxxxxxxxxxx", InstEmit.Umsubl, typeof(OpCodeMul64)); SetA64("10011011110xxxxx0xxxxxxxxxxxxxxx", InstEmit.Umulh, typeof(OpCodeMul64)); - //Vector + // Vector SetA64("0101111011100000101110xxxxxxxxxx", InstEmit.Abs_S, typeof(OpCodeSimd64)); SetA64("0>001110<<100000101110xxxxxxxxxx", InstEmit.Abs_V, typeof(OpCodeSimd64)); SetA64("01011110111xxxxx100001xxxxxxxxxx", InstEmit.Add_S, typeof(OpCodeSimdReg64)); @@ -656,12 +656,12 @@ namespace ChocolArm64 for (int index = 0; index < encoding.Length; index++, bit--) { - //Note: < and > are used on special encodings. - //The < means that we should never have ALL bits with the '<' set. - //So, when the encoding has <<, it means that 00, 01, and 10 are valid, - //but not 11. <<< is 000, 001, ..., 110 but NOT 111, and so on... - //For >, the invalid value is zero. So, for >> 01, 10 and 11 are valid, - //but 00 isn't. + // Note: < and > are used on special encodings. + // The < means that we should never have ALL bits with the '<' set. + // So, when the encoding has <<, it means that 00, 01, and 10 are valid, + // but not 11. <<< is 000, 001, ..., 110 but NOT 111, and so on... + // For >, the invalid value is zero. So, for >> 01, 10 and 11 are valid, + // but 00 isn't. char chr = encoding[index]; if (chr == '1') diff --git a/State/CpuThreadState.cs b/State/CpuThreadState.cs index 1cbbcf4..424f172 100644 --- a/State/CpuThreadState.cs +++ b/State/CpuThreadState.cs @@ -126,8 +126,8 @@ namespace ChocolArm64.State [MethodImpl(MethodImplOptions.AggressiveInlining)] internal bool Synchronize() { - //Firing a interrupt frequently is expensive, so we only - //do it after a given number of instructions has executed. + // Firing a interrupt frequently is expensive, so we only + // do it after a given number of instructions has executed. _syncCount++; if (_syncCount >= MinCountForCheck) diff --git a/Translation/ILEmitterCtx.cs b/Translation/ILEmitterCtx.cs index b4360fd..0deb29b 100644 --- a/Translation/ILEmitterCtx.cs +++ b/Translation/ILEmitterCtx.cs @@ -56,10 +56,10 @@ namespace ChocolArm64.Translation private OpCode64 _optOpLastCompare; private OpCode64 _optOpLastFlagSet; - //This is the index of the temporary register, used to store temporary - //values needed by some functions, since IL doesn't have a swap instruction. - //You can use any value here as long it doesn't conflict with the indices - //for the other registers. Any value >= 64 or < 0 will do. + // This is the index of the temporary register, used to store temporary + // values needed by some functions, since IL doesn't have a swap instruction. + // You can use any value here as long it doesn't conflict with the indices + // for the other registers. Any value >= 64 or < 0 will do. private const int ReservedLocalsCount = 64; private const int RorTmpIndex = ReservedLocalsCount + 0; @@ -69,7 +69,7 @@ namespace ChocolArm64.Translation private const int IntGpTmp2Index = ReservedLocalsCount + 4; private const int UserIntTempStart = ReservedLocalsCount + 5; - //Vectors are part of another "set" of locals. + // Vectors are part of another "set" of locals. private const int VecGpTmp1Index = ReservedLocalsCount + 0; private const int VecGpTmp2Index = ReservedLocalsCount + 1; private const int VecGpTmp3Index = ReservedLocalsCount + 2; @@ -139,10 +139,10 @@ namespace ChocolArm64.Translation public void ResetBlockStateForPredicatedOp() { - //Check if this is a predicated instruction that modifies flags, - //in this case the value of the flags is unknown as we don't know - //in advance if the instruction is going to be executed or not. - //So, we reset the block state to prevent an invalid optimization. + // Check if this is a predicated instruction that modifies flags, + // in this case the value of the flags is unknown as we don't know + // in advance if the instruction is going to be executed or not. + // So, we reset the block state to prevent an invalid optimization. if (CurrOp == _optOpLastFlagSet) { ResetBlockState(); @@ -167,8 +167,8 @@ namespace ChocolArm64.Translation public bool TryOptEmitSubroutineCall() { - //Calls should always have a next block, unless - //we're translating a single basic block. + // Calls should always have a next block, unless + // we're translating a single basic block. if (_currBlock.Next == null) { return false; @@ -239,15 +239,15 @@ namespace ChocolArm64.Translation && cond != Condition.GtUn && cond != Condition.LeUn) { - //There are several limitations that needs to be taken into account for CMN comparisons: - //- The unsigned comparisons are not valid, as they depend on the - //carry flag value, and they will have different values for addition and - //subtraction. For addition, it's carry, and for subtraction, it's borrow. - //So, we need to make sure we're not doing a unsigned compare for the CMN case. - //- We can only do the optimization for the immediate variants, - //because when the second operand value is exactly INT_MIN, we can't - //negate the value as theres no positive counterpart. - //Such invalid values can't be encoded on the immediate encodings. + // There are several limitations that needs to be taken into account for CMN comparisons: + // - The unsigned comparisons are not valid, as they depend on the + // carry flag value, and they will have different values for addition and + // subtraction. For addition, it's carry, and for subtraction, it's borrow. + // So, we need to make sure we're not doing a unsigned compare for the CMN case. + // - We can only do the optimization for the immediate variants, + // because when the second operand value is exactly INT_MIN, we can't + // negate the value as theres no positive counterpart. + // Such invalid values can't be encoded on the immediate encodings. if (_optOpLastCompare is IOpCodeAluImm64 op) { Ldloc(CmpOptTmp1Index, RegisterType.Int, _optOpLastCompare.RegisterSize); @@ -513,11 +513,11 @@ namespace ChocolArm64.Translation public void EmitLdflg(int index) => Ldloc(index, RegisterType.Flag); public void EmitStflg(int index) { - //Set this only if any of the NZCV flag bits were modified. - //This is used to ensure that when emiting a direct IL branch - //instruction for compare + branch sequences, we're not expecting - //to use comparison values from an old instruction, when in fact - //the flags were already overwritten by another instruction further along. + // Set this only if any of the NZCV flag bits were modified. + // This is used to ensure that when emiting a direct IL branch + // instruction for compare + branch sequences, we're not expecting + // to use comparison values from an old instruction, when in fact + // the flags were already overwritten by another instruction further along. if (index >= (int)PState.VBit) { _optOpLastFlagSet = CurrOp; diff --git a/Translation/RegisterUsage.cs b/Translation/RegisterUsage.cs index fe0c865..f88fa0c 100644 --- a/Translation/RegisterUsage.cs +++ b/Translation/RegisterUsage.cs @@ -153,7 +153,7 @@ namespace ChocolArm64.Translation public static long ClearCallerSavedIntRegs(long mask, ExecutionMode mode) { - //TODO: ARM32 support. + // TODO: ARM32 support. if (mode == ExecutionMode.Aarch64) { mask &= ~(CallerSavedIntRegistersMask | PStateNzcvFlagsMask); @@ -164,7 +164,7 @@ namespace ChocolArm64.Translation public static long ClearCallerSavedVecRegs(long mask, ExecutionMode mode) { - //TODO: ARM32 support. + // TODO: ARM32 support. if (mode == ExecutionMode.Aarch64) { mask &= ~CallerSavedVecRegistersMask; diff --git a/Translation/TranslatedSub.cs b/Translation/TranslatedSub.cs index 704e3b4..cf42e20 100644 --- a/Translation/TranslatedSub.cs +++ b/Translation/TranslatedSub.cs @@ -10,9 +10,9 @@ namespace ChocolArm64.Translation class TranslatedSub { - //This is the minimum amount of calls needed for the method - //to be retranslated with higher quality code. It's only worth - //doing that for hot code. + // This is the minimum amount of calls needed for the method + // to be retranslated with higher quality code. It's only worth + // doing that for hot code. private const int MinCallCountForOpt = 30; public ArmSubroutine Delegate { get; private set; } @@ -32,7 +32,7 @@ namespace ChocolArm64.Translation public TranslatedSub(DynamicMethod method, TranslationTier tier, bool rejit) { - Method = method ?? throw new ArgumentNullException(nameof(method));; + Method = method ?? throw new ArgumentNullException(nameof(method)); Tier = tier; _rejit = rejit; } @@ -74,7 +74,7 @@ namespace ChocolArm64.Translation public bool Rejit() { - if (!_rejit) + if (!_rejit) { return false; } @@ -84,7 +84,7 @@ namespace ChocolArm64.Translation return false; } - //Only return true once, so that it is added to the queue only once. + // Only return true once, so that it is added to the queue only once. _rejit = false; return true; diff --git a/Translation/Translator.cs b/Translation/Translator.cs index 2f88aaf..0803df0 100644 --- a/Translation/Translator.cs +++ b/Translation/Translator.cs @@ -209,11 +209,11 @@ namespace ChocolArm64.Translation context.ResetBlockStateForPredicatedOp(); - //If this is the last op on the block, and there's no "next" block - //after this one, then we have to return right now, with the address - //of the next instruction to be executed (in the case that the condition - //is false, and the branch was not taken, as all basic blocks should end - //with some kind of branch). + // If this is the last op on the block, and there's no "next" block + // after this one, then we have to return right now, with the address + // of the next instruction to be executed (in the case that the condition + // is false, and the branch was not taken, as all basic blocks should end + // with some kind of branch). if (isLastOp && block.Next == null) { context.EmitStoreContext(); diff --git a/Translation/TranslatorCache.cs b/Translation/TranslatorCache.cs index d10d675..cf6510a 100644 --- a/Translation/TranslatorCache.cs +++ b/Translation/TranslatorCache.cs @@ -8,13 +8,13 @@ namespace ChocolArm64.Translation { class TranslatorCache { - //Maximum size of the cache, the unit used is completely arbitrary. + // Maximum size of the cache, the unit used is completely arbitrary. private const int MaxTotalSize = 0x800000; - //Minimum time required in milliseconds for a method to be eligible for deletion. + // Minimum time required in milliseconds for a method to be eligible for deletion. private const int MinTimeDelta = 2 * 60000; - //Minimum number of calls required to update the timestamp. + // Minimum number of calls required to update the timestamp. private const int MinCallCountForUpdate = 250; private class CacheBucket @@ -122,10 +122,10 @@ namespace ChocolArm64.Translation { try { - //The bucket value on the dictionary may have changed between the - //time we get the value from the dictionary, and we acquire the - //lock. So we need to ensure we are working with the latest value, - //we can do that by getting the value again, inside the lock. + // The bucket value on the dictionary may have changed between the + // time we get the value from the dictionary, and we acquire the + // lock. So we need to ensure we are working with the latest value, + // we can do that by getting the value again, inside the lock. if (_cache.TryGetValue(position, out CacheBucket latestBucket)) { latestBucket.CallCount = 0;