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Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104)

Browse Source 
* Update AOpCodeTable.cs

* Update AInstEmitSimdLogical.cs

* Update AInstEmitSimdArithmetic.cs

* Update ASoftFallback.cs

* Update AInstEmitAlu.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs
This commit is contained in:
LDj3SNuD 2018-04-26 04:20:22 +02:00 committed by gdkchan
parent 27ed5ed039
commit 966f6b7203
5 changed files with 58 additions and 25 deletions
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3
AOpCodeTable.cs
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@ -148,6 +148,8 @@ namespace ChocolArm64
Set("0x101110111xxxxx000111xxxxxxxxxx", AInstEmit.Bif_V, typeof(AOpCodeSimdReg));
Set("0x101110101xxxxx000111xxxxxxxxxx", AInstEmit.Bit_V, typeof(AOpCodeSimdReg));
Set("0x101110011xxxxx000111xxxxxxxxxx", AInstEmit.Bsl_V, typeof(AOpCodeSimdReg));
Set("0x001110<<100000010010xxxxxxxxxx", AInstEmit.Cls_V, typeof(AOpCodeSimd));
Set("0x101110<<100000010010xxxxxxxxxx", AInstEmit.Clz_V, typeof(AOpCodeSimd));
Set("0>101110<<1xxxxx100011xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimdReg));
Set("0>001110<<100000100110xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimd));
Set("0>001110<<1xxxxx001111xxxxxxxxxx", AInstEmit.Cmge_V, typeof(AOpCodeSimdReg));
@ -289,6 +291,7 @@ namespace ChocolArm64
Set("0111111011100000101110xxxxxxxxxx", AInstEmit.Neg_S, typeof(AOpCodeSimd));
Set("0>101110<<100000101110xxxxxxxxxx", AInstEmit.Neg_V, typeof(AOpCodeSimd));
Set("0x10111000100000010110xxxxxxxxxx", AInstEmit.Not_V, typeof(AOpCodeSimd));
Set("0x001110111xxxxx000111xxxxxxxxxx", AInstEmit.Orn_V, typeof(AOpCodeSimdReg));
Set("0x001110101xxxxx000111xxxxxxxxxx", AInstEmit.Orr_V, typeof(AOpCodeSimdReg));
Set("0x00111100000xxx<<x101xxxxxxxxxx", AInstEmit.Orr_Vi, typeof(AOpCodeSimdImm));
Set("0x101110<<1xxxxx010000xxxxxxxxxx", AInstEmit.Raddhn_V, typeof(AOpCodeSimdReg));

22
Instruction/AInstEmitAlu.cs
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@ -106,14 +106,9 @@ namespace ChocolArm64.Instruction
Context.EmitLdintzr(Op.Rn);
if (Op.RegisterSize == ARegisterSize.Int32)
{
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingSigns32));
}
else
{
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingSigns64));
}
Context.EmitLdc_I4(Op.RegisterSize == ARegisterSize.Int32 ? 32 : 64);
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingSigns));
Context.EmitStintzr(Op.Rd);
}
@ -124,14 +119,9 @@ namespace ChocolArm64.Instruction
Context.EmitLdintzr(Op.Rn);
if (Op.RegisterSize == ARegisterSize.Int32)
{
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingZeros32));
}
else
{
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingZeros64));
}
Context.EmitLdc_I4(Op.RegisterSize == ARegisterSize.Int32 ? 32 : 64);
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingZeros));
Context.EmitStintzr(Op.Rd);
}

37
Instruction/AInstEmitSimdArithmetic.cs
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@ -109,6 +109,43 @@ namespace ChocolArm64.Instruction
EmitScalarSet(Context, Op.Rd, Op.Size);
}
public static void Cls_V(AILEmitterCtx Context)
{
MethodInfo MthdInfo = typeof(ASoftFallback).GetMethod(nameof(ASoftFallback.CountLeadingSigns));
EmitCountLeadingBits(Context, () => Context.EmitCall(MthdInfo));
}
public static void Clz_V(AILEmitterCtx Context)
{
MethodInfo MthdInfo = typeof(ASoftFallback).GetMethod(nameof(ASoftFallback.CountLeadingZeros));
EmitCountLeadingBits(Context, () => Context.EmitCall(MthdInfo));
}
private static void EmitCountLeadingBits(AILEmitterCtx Context, Action Emit)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
{
EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size);
Context.EmitLdc_I4(8 << Op.Size);
Emit();
EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
}
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
public static void Cnt_V(AILEmitterCtx Context)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;

11
Instruction/AInstEmitSimdLogical.cs
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@ -103,6 +103,15 @@ namespace ChocolArm64.Instruction
EmitVectorUnaryOpZx(Context, () => Context.Emit(OpCodes.Not));
}
public static void Orn_V(AILEmitterCtx Context)
{
EmitVectorBinaryOpZx(Context, () =>
{
Context.Emit(OpCodes.Not);
Context.Emit(OpCodes.Or);
});
}
public static void Orr_V(AILEmitterCtx Context)
{
EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Or));
@ -136,4 +145,4 @@ namespace ChocolArm64.Instruction
}
}
}
}
}

10
Instruction/ASoftFallback.cs
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@ -20,18 +20,12 @@ namespace ChocolArm64.Instruction
Context.EmitCall(typeof(ASoftFallback), MthdName);
}
public static uint CountLeadingSigns32(uint Value) => (uint)CountLeadingSigns(Value, 32);
public static ulong CountLeadingSigns64(ulong Value) => (ulong)CountLeadingSigns(Value, 64);
private static ulong CountLeadingSigns(ulong Value, int Size)
public static ulong CountLeadingSigns(ulong Value, int Size)
{
return CountLeadingZeros((Value >> 1) ^ Value, Size - 1);
}
public static uint CountLeadingZeros32(uint Value) => (uint)CountLeadingZeros(Value, 32);
public static ulong CountLeadingZeros64(ulong Value) => (ulong)CountLeadingZeros(Value, 64);
private static ulong CountLeadingZeros(ulong Value, int Size)
public static ulong CountLeadingZeros(ulong Value, int Size)
{
int HighBit = Size - 1;