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Ryujinx-ChocolArm64
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  • 170793a2ca Remove missing reference master Mary 2021-02-26 23:46:17 +0100
  • a710cfa9e2
         Initialize repository Thog 2019-10-31 17:32:51 +0100
  • 7dddfbf688 Add Saddlv_V Inst. Improve Cnt_V, Dup_Gp & Ins_Gp Tests. Tuneup Cls_V & Clz_V Tests. (#720) LDj3SNuD 2019-07-08 16:55:37 +0200
  • 25e6a2e0ea Misc cleanup (#708) Alex Barney 2019-07-01 21:39:22 -0500
  • a250878bfe Implement the remaining tests for Simd and Fp instructions of data processing type. Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. (#709) LDj3SNuD 2019-06-30 01:02:48 +0200
  • aa2a84998c Add FCVT <Hd>, <Sn> and FCVT <Sd>, <Hn> Inst.; add Tests. (#692) LDj3SNuD 2019-05-31 00:51:39 +0200
  • 54e780a803 Add Smaxv_V, Sminv_V, Umaxv_V, Uminv_V Inst.; add Tests. (#691) LDj3SNuD 2019-05-30 02:29:24 +0200
  • 538b1006e0 Refactoring and optimization on CPU translation (#661) gdkchan 2019-04-26 01:55:12 -0300
  • 98b0026340 Built in profiling (#567) BaronKiko 2019-04-26 05:53:10 +0100
  • 041a5e0301 Sse optimized the Scalar & Vector fp-to-fp conversion instructions (MNPZ & IX); added the related Tests (AMNPZ & IX). Small refactoring of existing instructions. (#676) LDj3SNuD 2019-04-26 00:58:29 +0200
  • f62521ef11 Sse optimized the 32-bit Vector & Scalar integer-to-fp conversion instructions (signed & unsigned); added the related Gp & V_Fixed Tests (signed & unsigned). (#662) LDj3SNuD 2019-04-21 04:07:35 +0200
  • c33c574a24 Sse optimized the Vector & Scalar fp-to-integer conversion instructions (unsigned); improved the related Tests. (#656) LDj3SNuD 2019-04-12 18:14:16 +0200
  • 063d423db5 Sse optimized all the fp to integer conversion instructions (signed) with Tests (signed & unsigned). (#655) LDj3SNuD 2019-04-03 14:21:22 +0200
  • 57659ad0d2 Add Cmeq_V, Cmge_V, Cmgt_V, Cmle_V & Cmlt_V (Z & ~Z) Sse opt.. (#646) LDj3SNuD 2019-03-25 00:23:27 +0100
  • d9561f41eb Add Tbl_V Sse opt. with Tests. (#651) LDj3SNuD 2019-03-23 19:50:19 +0100
  • 8c08547a9f Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. (#614) LDj3SNuD 2019-03-13 09:23:52 +0100
  • 8d5a48ba0a Misc. CPU optimizations (#575) gdkchan 2019-02-27 23:03:31 -0300
  • f2d37d52f7 Optimize MOVI/MVNI instructions using intrinsics (#606) gdkchan 2019-02-26 09:50:36 -0300
  • fca693a696 Optmize BFM instruction (#607) gdkchan 2019-02-26 06:16:50 -0300
  • f1217a4ce9 Remove all the calls to StaticCast methods (#605) gdkchan 2019-02-25 20:46:34 -0300
  • 9bb400dfea Optimize address translation and write tracking on the MMU (#571) gdkchan 2019-02-24 04:24:35 -0300
  • 5ba8c8bedc Implement fixed-point variant of the UCVTF and SCVTF instructions (#578) gdkchan 2019-02-23 20:52:48 -0300
  • 0be1f5b45a ARM exclusive monitor and multicore fixes (#589) gdkchan 2019-02-18 20:52:06 -0300
  • b447d59c25 Optimize CMN/ADDS to do a single comparision like CMP/SUBS (#576) gdkchan 2019-02-18 01:17:34 -0300
  • 8be183f41d Implement speculative translation on the CPU (#515) gdkchan 2019-02-04 18:26:05 -0300
  • 0cda6b3cdf Implement some ARM32 memory instructions and CMP (#565) gdkchan 2019-01-29 13:06:11 -0300
  • 64a12b8eb5 Add Smlal_Ve, Smlsl_Ve, Smull_Ve, Umlal_Ve, Umlsl_Ve, Umull_Ve Inst.; add Tests. Add Sse Opt. for Trn1/2_V and Uzp1/2_V Inst. Nits. (#566) LDj3SNuD 2019-01-29 14:54:39 +0100
  • b0e1e505da Add ARM32 support on the translator (#561) gdkchan 2019-01-24 23:59:53 -0200
  • 9260ebd268 Fix Frecpe_S/V and Frsqrte_S/V (full FP emu.). Add Sse Opt. & SoftFloat Impl. for Fcmeq/ge/gt/le/lt_S/V (Reg & Zero), Faddp_S/V, Fmaxp_V, Fminp_V Inst.; add Sse Opt. for Shll_V, S/Ushll_V Inst.; improve Sse Opt. for Xtn_V Inst.. Add Tests. (#543) LDj3SNuD 2018-12-26 18:11:36 +0100
  • 31ef8d404a Add Frintz_S/V opcode and unit test, correction of some unit tests (#523) MS-DOS1999 2018-12-18 01:29:47 +0100
  • 63ae8679a3 Optimized memory modified check (#538) Roderick Sieben 2018-12-12 02:48:54 +0100
  • 01d9716d20 Misc. CPU improvements (#519) gdkchan 2018-12-10 22:58:52 -0200
  • 5ed6e570cf Fix Sshl_V; Add S/Uqrshl_V, S/Uqshl_V, S/Urshl_V; Add Tests. (#516) LDj3SNuD 2018-12-02 01:34:43 +0100
  • c0dc0f2c3f Better process implementation (#491) gdkchan 2018-11-28 20:18:09 -0200
  • 7e98b0f6b2 Add Sse Opt. for S/Umax_V, S/Umin_V, S/Uaddw_V, S/Usubw_V, Fabs_S/V, Fneg_S/V Inst.; for Fcvtl_V, Fcvtn_V Inst.; and for Fcmp_S Inst.. Add/Improve other Sse Opt.. Add Tests. (#496) LDj3SNuD 2018-11-18 03:41:16 +0100
  • 5357291c36 Improved GPU command lists decoding (#499) gdkchan 2018-11-17 02:01:31 -0200
  • a56f7e8f68 Fix BLR when the source reg is X30 (#493) gdkchan 2018-11-09 16:41:20 -0200
  • ecf67bdcef Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489) LDj3SNuD 2018-11-01 05:22:09 +0100
  • d527632d1c Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) Alex Barney 2018-10-30 19:43:02 -0600
  • d817eff2cb Fix regression caused by wrong time delta calculation on cache deletion methods gdkchan 2018-10-30 11:42:27 -0300
  • 0183f5e1a1 Fix the rotate right method on ABitUtils (#486) gdkchan 2018-10-28 22:18:58 -0300
  • c2aaf78d4c Timing: Optimize Timestamp Aquisition (#479) jduncanator 2018-10-29 09:31:13 +1100
  • d69f900f29 Add SHA1C, SHA1H, SHA1M, SHA1P, SHA1SU0, SHA1SU1 and Isb instructions; add 6 Tests (closed box). (#483) LDj3SNuD 2018-10-28 23:27:50 +0100
  • 5ffeeaed02 Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480) LDj3SNuD 2018-10-26 00:10:41 +0200
  • 28e6b93634 Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468) LDj3SNuD 2018-10-23 16:12:45 +0200
  • 374e660b78 Print stack trace on invalid memory accesses (#461) gdkchan 2018-10-20 19:07:52 -0300
  • 9533b338ac Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449) LDj3SNuD 2018-10-14 04:35:16 +0200
  • f1e01ed47b Tweak cpu cache deletion policy values (#433) gdkchan 2018-10-07 23:40:37 -0300
  • f6fa73b965 Add 9+7 fast/slow FP inst. impls.; add 14 FP Tests. (#437) LDj3SNuD 2018-10-06 03:45:59 +0200
  • 88af0e2966 Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405) gdkchan 2018-09-26 23:30:21 -0300
  • f88763fcd4 Add FMAXP and FMINP (Vector) instructions on the CPU (#412) gdkchan 2018-09-22 17:26:18 -0300
  • 0cf462669d Remove cold methods from the CPU cache (#224) gdkchan 2018-09-19 17:07:56 -0300
  • c08479877e Fix performance regression caused by the new scheduler changes (#422) gdkchan 2018-09-19 12:16:20 -0300
  • f07e1fa8af Thread scheduler rewrite (#393) gdkchan 2018-09-18 20:36:43 -0300
  • 193bf223ec Allow "reinterpretation" of framebuffer/zeta formats (#418) gdkchan 2018-09-18 01:30:35 -0300
  • 3d16dbe12c Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; add 14 Tests. Add 6 Tests for PR#405. Add 2 Tests for PR#412. (#409) LDj3SNuD 2018-09-17 06:54:05 +0200
  • 80836050ef Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407) LDj3SNuD 2018-09-08 19:24:29 +0200
  • 1be39f720f Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390) LDj3SNuD 2018-09-01 16:52:51 +0200
  • d567d15ff3 Add SHADD, SHSUB, UHSUB, SRHADD, URHADD, instructions; add 12 Tests. (#380) LDj3SNuD 2018-08-27 08:44:01 +0200
  • 29563c17b2 Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365) LDj3SNuD 2018-08-20 06:20:26 +0200
  • 10e04ace2f Add SHA256H, SHA256H2, SHA256SU0, SHA256SU1 instructions; add 4 Tests (closed box). (#352) LDj3SNuD 2018-08-17 02:44:44 +0200
  • a7dbe84a68 Code style fixes and nits on the HLE project (#355) gdkchan 2018-08-16 20:47:36 -0300
  • 178effbad9 More flexible memory manager (#307) gdkchan 2018-08-15 15:59:51 -0300
  • 9f004c3139 Zero out bits 63:32 of scalar float operations with SSE intrinsics (#273) gdkchan 2018-08-14 23:54:12 -0300
  • fc015322bc Add Sadalp_V, Saddlp_V, Uadalp_V, Uaddlp_V instructions; add 8 Tests. (#340) LDj3SNuD 2018-08-13 23:10:02 +0200
  • ce286149c6 Add Sqdmulh_S, Sqdmulh_V, Sqrdmulh_S, Sqrdmulh_V instructions; add 6 Tests. Now all saturating methods are on ASoftFallback. (#334) LDj3SNuD 2018-08-10 19:27:15 +0200
  • d2aeeacf08 Fix load/store exclusive/atomic pairwise instructions (#337) gdkchan 2018-08-10 01:14:27 -0300
  • e26d5f3f59 Fix silly copy/paste error on float variant of the FMINNM instruction gdkchan 2018-08-05 18:56:30 -0300
  • 21fa932514 More accurate impl of FMINNM/FMAXNM, add vector variants (#296) gdkchan 2018-08-05 02:54:21 -0300
  • f736be2efb Add SQADD, UQADD, SQSUB, UQSUB, SUQADD, USQADD, SQABS, SQNEG (Scalar, Vector) instructions; add 24 Tests. Most saturation instructions now on ASoftFallback. (#314) LDj3SNuD 2018-08-04 21:58:54 +0200
  • e51ccf206b Cache changes (#302) ReinUsesLisp 2018-07-29 01:39:15 -0300
  • dcbeed72c4 update encoding for branch instruction (#305) Arthur Chen 2018-07-27 00:46:05 +0800
  • 34ebf2acbe Send data to OpenGL host without client-side copies (#285) ReinUsesLisp 2018-07-19 16:02:51 -0300
  • ee2452c136 AOpCodeTable: Speed up instruction decoding (#284) Merry 2018-07-19 06:32:37 +0100
  • a3a5545c05 Implement Ssubw_V and Usubw_V instructions. (#287) LDj3SNuD 2018-07-19 02:06:28 +0200
  • 02b8d80068 Fix LDXP/LDAXP when Rt == Rn (#274) gdkchan 2018-07-16 15:57:15 -0300
  • 1f2400ed18 Fix EmitHighNarrow(), EmitSaturatingNarrowOp() when Rd == Rn || Rd == Rm (& Part != 0). Optimization of EmitVectorTranspose(), EmitVectorUnzip(), EmitVectorZip() algorithms (reduction of the number of operations and their complexity). Add 12 Tests about Trn1/2, Uzp1/2, Zip1/2 (V) instructions. (#268) LDj3SNuD 2018-07-15 05:53:26 +0200
  • 97e469e315 Improve CountLeadingZeros() algorithm, nits. (#219) LDj3SNuD 2018-07-14 20:07:44 +0200
  • e64f484521 Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225) gdkchan 2018-07-14 13:13:02 -0300
  • 1e35b99f74 AInstEmitSimdCvt: Half-precision to single-precision conversion (#235) Merry 2018-07-12 19:51:02 +0100
  • c590201b2a Fix ZIP/UZP/TRN instructions when Rd == Rn || Rd == Rm (#239) gdkchan 2018-07-09 22:48:28 -0300
  • 0daf70a1d9 Query multiple pages at once with GetWriteWatch (#222) gdkchan 2018-07-08 16:55:15 -0300
  • a47b96571e ChocolArm64: More accurate implementation of Frecpe & Frecps (#228) Merry 2018-07-08 20:54:47 +0100
  • 666e7e2e4c ASoftFloat: Fix InvSqrtEstimate for negative values (#233) Merry 2018-07-08 16:41:46 +0100
  • 8aee846940 Remove broken adds/cmn with condition check optimization (#218) gdkchan 2018-07-03 21:54:05 -0300
  • 392c5b7d98 Add SMAXP, SMINP, UMAX, UMAXP, UMIN and UMINP cpu instructions (#200) gdkchan 2018-07-03 03:31:48 -0300
  • 8d7582a918 Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. (#212) LDj3SNuD 2018-07-03 08:31:16 +0200
  • 051740f344 Add linux-x64 to RID property to make tests works on linux (#205) Thomas Guillemard 2018-06-30 17:43:04 +0200
  • ac5c1e5107 Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, Uabdl_V. Add 16 tests. (#204) LDj3SNuD 2018-06-30 17:40:41 +0200
  • 7e59d1b639 Add Sse2 fallback to Vector{Extract|Insert}Single methods on the CPU (#193) gdkchan 2018-06-28 20:52:32 -0300
  • f58651d009 Add support for the FMLA (by element/scalar) instruction (#187) gdkchan 2018-06-28 20:51:38 -0300
  • a12f31867c Implement SvcGetThreadContext3 gdkchan 2018-06-26 01:09:32 -0300
  • 31871077e2 Add Sqxtun_S, Sqxtun_V with 3 tests. (#188) LDj3SNuD 2018-06-26 04:36:20 +0200
  • 86aae79b9d Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183) LDj3SNuD 2018-06-26 03:32:29 +0200
  • 216bcd7a65 Add REV16/32 (vector) instructions and fix REV64 gdkchan 2018-06-25 18:40:55 -0300
  • 3f81e1c795 Add opcodes SQXTUN_S and SQXTUN_V (#184) Rygnus 2018-06-25 18:23:46 +0100
  • c9813159d1 Small OpenGL Renderer refactoring (#177) gdkchan 2018-06-23 21:39:25 -0300
  • f6ff678834 Fix some thread sync issues (#172) gdkchan 2018-06-21 23:05:42 -0300
  • 32900cc223 Rework signed multiplication. Fixed an edge case and passes all tests. (#174) riperiperi 2018-06-20 14:45:20 +0100
  • 7084bf58a4 Add Cmeq_S, Cmge_S, Cmgt_S, Cmhi_S, Cmhs_S, Cmle_S, Cmlt_S (Reg, Zero) & Cmtst_S compare instructions. Add 22 compare tests (Scalar, Vector). Add Eor_V, Not_V tests. (#171) LDj3SNuD 2018-06-18 19:55:26 +0200