147 lines
4.8 KiB
C#
147 lines
4.8 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.IntermediateRepresentation;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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namespace ChocolArm64.Instructions
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{
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static class InstEmit32Helper
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{
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public static bool IsThumb(OpCode64 op)
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{
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return op is OpCodeT16;
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}
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public static void EmitLoadFromRegister(ILEmitterCtx context, int register)
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{
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if (register == RegisterAlias.Aarch32Pc)
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{
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OpCode32 op = (OpCode32)context.CurrOp;
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context.EmitLdc_I4((int)op.GetPc());
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}
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else
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{
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context.EmitLdint(GetRegisterAlias(context.Mode, register));
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}
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}
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public static void EmitStoreToRegister(ILEmitterCtx context, int register)
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{
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if (register == RegisterAlias.Aarch32Pc)
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{
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context.EmitStoreContext();
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EmitBxWritePc(context);
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}
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else
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{
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context.EmitStint(GetRegisterAlias(context.Mode, register));
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}
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}
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public static void EmitBxWritePc(ILEmitterCtx context)
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{
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context.Emit(OpCodes.Dup);
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context.EmitLdc_I4(1);
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context.Emit(OpCodes.And);
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context.Emit(OpCodes.Dup);
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context.EmitStflg((int)PState.TBit);
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ILLabel lblArmMode = new ILLabel();
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ILLabel lblEnd = new ILLabel();
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context.Emit(OpCodes.Brtrue_S, lblArmMode);
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context.EmitLdc_I4(~1);
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context.Emit(OpCodes.Br_S, lblEnd);
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context.MarkLabel(lblArmMode);
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context.EmitLdc_I4(~3);
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context.MarkLabel(lblEnd);
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context.Emit(OpCodes.And);
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context.Emit(OpCodes.Conv_U8);
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context.Emit(OpCodes.Ret);
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}
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public static int GetRegisterAlias(Aarch32Mode mode, int register)
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{
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//Only registers >= 8 are banked, with registers in the range [8, 12] being
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//banked for the FIQ mode, and registers 13 and 14 being banked for all modes.
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if ((uint)register < 8)
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{
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return register;
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}
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return GetBankedRegisterAlias(mode, register);
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}
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public static int GetBankedRegisterAlias(Aarch32Mode mode, int register)
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{
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switch (register)
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{
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case 8: return mode == Aarch32Mode.Fiq
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? RegisterAlias.R8Fiq
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: RegisterAlias.R8Usr;
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case 9: return mode == Aarch32Mode.Fiq
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? RegisterAlias.R9Fiq
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: RegisterAlias.R9Usr;
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case 10: return mode == Aarch32Mode.Fiq
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? RegisterAlias.R10Fiq
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: RegisterAlias.R10Usr;
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case 11: return mode == Aarch32Mode.Fiq
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? RegisterAlias.R11Fiq
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: RegisterAlias.R11Usr;
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case 12: return mode == Aarch32Mode.Fiq
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? RegisterAlias.R12Fiq
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: RegisterAlias.R12Usr;
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case 13:
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switch (mode)
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{
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case Aarch32Mode.User:
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case Aarch32Mode.System: return RegisterAlias.SpUsr;
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case Aarch32Mode.Fiq: return RegisterAlias.SpFiq;
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case Aarch32Mode.Irq: return RegisterAlias.SpIrq;
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case Aarch32Mode.Supervisor: return RegisterAlias.SpSvc;
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case Aarch32Mode.Abort: return RegisterAlias.SpAbt;
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case Aarch32Mode.Hypervisor: return RegisterAlias.SpHyp;
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case Aarch32Mode.Undefined: return RegisterAlias.SpUnd;
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default: throw new ArgumentException(nameof(mode));
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}
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case 14:
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switch (mode)
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{
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case Aarch32Mode.User:
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case Aarch32Mode.Hypervisor:
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case Aarch32Mode.System: return RegisterAlias.LrUsr;
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case Aarch32Mode.Fiq: return RegisterAlias.LrFiq;
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case Aarch32Mode.Irq: return RegisterAlias.LrIrq;
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case Aarch32Mode.Supervisor: return RegisterAlias.LrSvc;
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case Aarch32Mode.Abort: return RegisterAlias.LrAbt;
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case Aarch32Mode.Undefined: return RegisterAlias.LrUnd;
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default: throw new ArgumentException(nameof(mode));
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}
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default: throw new ArgumentOutOfRangeException(nameof(register));
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}
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}
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}
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}
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