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Ryujinx-ChocolArm64
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A C# ARM64 emulator that works translating ARM code to CIL
168 Commits 1 Branch 0 Tags 888 KiB
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gdkchan 0be1f5b45a ARM exclusive monitor and multicore fixes (#589) 
* Implement ARM exclusive load/store with compare exchange insts, and enable multicore by default

* Fix comment typo

* Support Linux and OSX on MemoryAlloc and CompareExchange128, some cleanup

* Use intel syntax on assembly code

* Adjust identation

* Add CPUID check and fix exclusive reservation granule size

* Update schema multicore scheduling default value

* Make the cpu id check code lower case aswell
 		2019-02-19 10:52:06 +11:00
Decoders Implement speculative translation on the CPU (#515) 2019-02-04 18:26:05 -03:00
Events Optimized memory modified check (#538) 2018-12-11 23:48:54 -02:00
Exceptions Better process implementation (#491) 2018-11-28 20:18:09 -02:00
Instructions ARM exclusive monitor and multicore fixes (#589) 2019-02-19 10:52:06 +11:00
Memory ARM exclusive monitor and multicore fixes (#589) 2019-02-19 10:52:06 +11:00
State ARM exclusive monitor and multicore fixes (#589) 2019-02-19 10:52:06 +11:00
Translation ARM exclusive monitor and multicore fixes (#589) 2019-02-19 10:52:06 +11:00
ChocolArm64.csproj ARM exclusive monitor and multicore fixes (#589) 2019-02-19 10:52:06 +11:00
CpuThread.cs ARM exclusive monitor and multicore fixes (#589) 2019-02-19 10:52:06 +11:00
OpCodeTable.cs Implement some ARM32 memory instructions and CMP (#565) 2019-01-29 13:06:11 -03:00
Optimizations.cs Fix Frecpe_S/V and Frsqrte_S/V (full FP emu.). Add Sse Opt. & SoftFloat Impl. for Fcmeq/ge/gt/le/lt_S/V (Reg & Zero), Faddp_S/V, Fmaxp_V, Fminp_V Inst.; add Sse Opt. for Shll_V, S/Ushll_V Inst.; improve Sse Opt. for Xtn_V Inst.. Add Tests. (#543) 2018-12-26 15:11:36 -02:00