379 lines
12 KiB
C#
379 lines
12 KiB
C#
using ChocolArm64.Instructions;
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using ChocolArm64.Memory;
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using ChocolArm64.State;
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using System;
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using System.Collections.Concurrent;
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using System.Collections.Generic;
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using System.Reflection.Emit;
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namespace ChocolArm64.Decoders
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{
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static class Decoder
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{
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private delegate object OpActivator(Inst inst, long position, int opCode);
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private static ConcurrentDictionary<Type, OpActivator> _opActivators;
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static Decoder()
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{
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_opActivators = new ConcurrentDictionary<Type, OpActivator>();
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}
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public static Block[] DecodeBasicBlock(MemoryManager memory, ulong address, ExecutionMode mode)
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{
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Block block = new Block(address);
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FillBlock(memory, mode, block, ulong.MaxValue);
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OpCode64 lastOp = block.GetLastOp();
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if (IsBranch(lastOp) && !IsCall(lastOp) && lastOp is IOpCodeBImm op)
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{
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//It's possible that the branch on this block lands on the middle of the block.
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//This is more common on tight loops. In this case, we can improve the codegen
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//a bit by changing the CFG and either making the branch point to the same block
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//(which indicates that the block is a loop that jumps back to the start), and the
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//other possible case is a jump somewhere on the middle of the block, which is
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//also a loop, but in this case we need to split the block in half.
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if ((ulong)op.Imm == address)
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{
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block.Branch = block;
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}
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else if ((ulong)op.Imm > address &&
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(ulong)op.Imm < block.EndAddress)
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{
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Block rightBlock = new Block((ulong)op.Imm);
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block.Split(rightBlock);
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return new Block[] { block, rightBlock };
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}
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}
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return new Block[] { block };
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}
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public static Block[] DecodeSubroutine(MemoryManager memory, ulong address, ExecutionMode mode)
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{
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List<Block> blocks = new List<Block>();
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Queue<Block> workQueue = new Queue<Block>();
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Dictionary<ulong, Block> visited = new Dictionary<ulong, Block>();
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Block GetBlock(ulong blkAddress)
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{
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if (!visited.TryGetValue(blkAddress, out Block block))
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{
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block = new Block(blkAddress);
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workQueue.Enqueue(block);
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visited.Add(blkAddress, block);
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}
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return block;
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}
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GetBlock(address);
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while (workQueue.TryDequeue(out Block currBlock))
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{
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//Check if the current block is inside another block.
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if (BinarySearch(blocks, currBlock.Address, out int nBlkIndex))
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{
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Block nBlock = blocks[nBlkIndex];
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if (nBlock.Address == currBlock.Address)
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{
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throw new InvalidOperationException("Found duplicate block address on the list.");
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}
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nBlock.Split(currBlock);
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blocks.Insert(nBlkIndex + 1, currBlock);
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continue;
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}
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//If we have a block after the current one, set the limit address.
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ulong limitAddress = ulong.MaxValue;
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if (nBlkIndex != blocks.Count)
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{
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Block nBlock = blocks[nBlkIndex];
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int nextIndex = nBlkIndex + 1;
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if (nBlock.Address < currBlock.Address && nextIndex < blocks.Count)
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{
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limitAddress = blocks[nextIndex].Address;
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}
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else if (nBlock.Address > currBlock.Address)
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{
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limitAddress = blocks[nBlkIndex].Address;
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}
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}
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FillBlock(memory, mode, currBlock, limitAddress);
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if (currBlock.OpCodes.Count != 0)
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{
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//Set child blocks. "Branch" is the block the branch instruction
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//points to (when taken), "Next" is the block at the next address,
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//executed when the branch is not taken. For Unconditional Branches
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//(except BL/BLR that are sub calls) or end of executable, Next is null.
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OpCode64 lastOp = currBlock.GetLastOp();
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bool isCall = IsCall(lastOp);
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if (lastOp is IOpCodeBImm op && !isCall)
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{
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currBlock.Branch = GetBlock((ulong)op.Imm);
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}
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if (!IsUnconditionalBranch(lastOp) || isCall)
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{
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currBlock.Next = GetBlock(currBlock.EndAddress);
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}
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}
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//Insert the new block on the list (sorted by address).
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if (blocks.Count != 0)
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{
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Block nBlock = blocks[nBlkIndex];
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blocks.Insert(nBlkIndex + (nBlock.Address < currBlock.Address ? 1 : 0), currBlock);
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}
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else
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{
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blocks.Add(currBlock);
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}
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}
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return blocks.ToArray();
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}
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private static bool BinarySearch(List<Block> blocks, ulong address, out int index)
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{
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index = 0;
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int left = 0;
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int right = blocks.Count - 1;
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while (left <= right)
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{
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int size = right - left;
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int middle = left + (size >> 1);
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Block block = blocks[middle];
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index = middle;
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if (address >= block.Address && address < block.EndAddress)
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{
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return true;
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}
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if (address < block.Address)
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{
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right = middle - 1;
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}
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else
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{
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left = middle + 1;
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}
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}
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return false;
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}
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private static void FillBlock(
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MemoryManager memory,
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ExecutionMode mode,
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Block block,
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ulong limitAddress)
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{
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ulong address = block.Address;
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OpCode64 opCode;
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do
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{
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if (address >= limitAddress)
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{
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break;
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}
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opCode = DecodeOpCode(memory, address, mode);
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block.OpCodes.Add(opCode);
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address += (ulong)opCode.OpCodeSizeInBytes;
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}
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while (!(IsBranch(opCode) || IsException(opCode)));
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block.EndAddress = address;
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}
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private static bool IsBranch(OpCode64 opCode)
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{
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return opCode is OpCodeBImm64 ||
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opCode is OpCodeBReg64 || IsAarch32Branch(opCode);
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}
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private static bool IsUnconditionalBranch(OpCode64 opCode)
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{
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return opCode is OpCodeBImmAl64 ||
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opCode is OpCodeBReg64 || IsAarch32UnconditionalBranch(opCode);
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}
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private static bool IsAarch32UnconditionalBranch(OpCode64 opCode)
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{
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if (!(opCode is OpCode32 op))
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{
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return false;
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}
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//Note: On ARM32, most instructions have conditional execution,
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//so there's no "Always" (unconditional) branch like on ARM64.
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//We need to check if the condition is "Always" instead.
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return IsAarch32Branch(op) && op.Cond >= Condition.Al;
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}
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private static bool IsAarch32Branch(OpCode64 opCode)
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{
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//Note: On ARM32, most ALU operations can write to R15 (PC),
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//so we must consider such operations as a branch in potential aswell.
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if (opCode is IOpCode32Alu opAlu && opAlu.Rd == RegisterAlias.Aarch32Pc)
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{
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return true;
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}
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//Same thing for memory operations. We have the cases where PC is a target
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//register (Rt == 15 or (mask & (1 << 15)) != 0), and cases where there is
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//a write back to PC (wback == true && Rn == 15), however the later may
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//be "undefined" depending on the CPU, so compilers should not produce that.
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if (opCode is IOpCode32Mem || opCode is IOpCode32MemMult)
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{
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int rt, rn;
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bool wBack, isLoad;
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if (opCode is IOpCode32Mem opMem)
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{
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rt = opMem.Rt;
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rn = opMem.Rn;
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wBack = opMem.WBack;
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isLoad = opMem.IsLoad;
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//For the dual load, we also need to take into account the
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//case were Rt2 == 15 (PC).
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if (rt == 14 && opMem.Emitter == InstEmit32.Ldrd)
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{
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rt = RegisterAlias.Aarch32Pc;
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}
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}
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else if (opCode is IOpCode32MemMult opMemMult)
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{
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const int pcMask = 1 << RegisterAlias.Aarch32Pc;
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rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0;
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rn = opMemMult.Rn;
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wBack = opMemMult.PostOffset != 0;
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isLoad = opMemMult.IsLoad;
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}
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else
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{
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throw new NotImplementedException($"The type \"{opCode.GetType().Name}\" is not implemented on the decoder.");
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}
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if ((rt == RegisterAlias.Aarch32Pc && isLoad) ||
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(rn == RegisterAlias.Aarch32Pc && wBack))
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{
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return true;
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}
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}
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//Explicit branch instructions.
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return opCode is IOpCode32BImm ||
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opCode is IOpCode32BReg;
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}
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private static bool IsCall(OpCode64 opCode)
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{
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//TODO (CQ): ARM32 support.
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return opCode.Emitter == InstEmit.Bl ||
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opCode.Emitter == InstEmit.Blr;
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}
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private static bool IsException(OpCode64 opCode)
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{
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return opCode.Emitter == InstEmit.Brk ||
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opCode.Emitter == InstEmit.Svc ||
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opCode.Emitter == InstEmit.Und;
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}
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public static OpCode64 DecodeOpCode(MemoryManager memory, ulong address, ExecutionMode mode)
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{
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int opCode = memory.ReadInt32((long)address);
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Inst inst;
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if (mode == ExecutionMode.Aarch64)
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{
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inst = OpCodeTable.GetInstA64(opCode);
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}
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else
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{
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if (mode == ExecutionMode.Aarch32Arm)
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{
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inst = OpCodeTable.GetInstA32(opCode);
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}
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else /* if (mode == ExecutionMode.Aarch32Thumb) */
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{
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inst = OpCodeTable.GetInstT32(opCode);
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}
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}
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OpCode64 decodedOpCode = new OpCode64(Inst.Undefined, (long)address, opCode);
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if (inst.Type != null)
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{
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decodedOpCode = MakeOpCode(inst.Type, inst, (long)address, opCode);
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}
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return decodedOpCode;
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}
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private static OpCode64 MakeOpCode(Type type, Inst inst, long position, int opCode)
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{
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if (type == null)
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{
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throw new ArgumentNullException(nameof(type));
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}
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OpActivator createInstance = _opActivators.GetOrAdd(type, CacheOpActivator);
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return (OpCode64)createInstance(inst, position, opCode);
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}
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private static OpActivator CacheOpActivator(Type type)
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{
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Type[] argTypes = new Type[] { typeof(Inst), typeof(long), typeof(int) };
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DynamicMethod mthd = new DynamicMethod($"Make{type.Name}", type, argTypes);
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ILGenerator generator = mthd.GetILGenerator();
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generator.Emit(OpCodes.Ldarg_0);
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generator.Emit(OpCodes.Ldarg_1);
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generator.Emit(OpCodes.Ldarg_2);
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generator.Emit(OpCodes.Newobj, type.GetConstructor(argTypes));
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generator.Emit(OpCodes.Ret);
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return (OpActivator)mthd.CreateDelegate(typeof(OpActivator));
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}
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}
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} |