mirror of
https://github.com/Ryujinx/ChocolArm64.git
synced 2024-06-03 01:38:51 +02:00
5ffeeaed02
* Update AILEmitterCtx.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdShift.cs
866 lines
28 KiB
C#
866 lines
28 KiB
C#
// https://github.com/intel/ARM_NEON_2_x86_SSE/blob/master/NEON_2_SSE.h
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using ChocolArm64.Decoder;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using System.Runtime.Intrinsics.X86;
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using static ChocolArm64.Instruction.AInstEmitSimdHelper;
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namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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public static void Rshrn_V(AILEmitterCtx Context)
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{
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EmitVectorShrImmNarrowOpZx(Context, Round: true);
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}
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public static void Shl_S(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitScalarUnaryOpZx(Context, () =>
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{
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Context.EmitLdc_I4(GetImmShl(Op));
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Context.Emit(OpCodes.Shl);
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});
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}
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public static void Shl_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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if (AOptimizations.UseSse2 && Op.Size > 0)
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{
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Type[] TypesSll = new Type[] { VectorUIntTypesPerSizeLog2[Op.Size], typeof(byte) };
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EmitLdvecWithUnsignedCast(Context, Op.Rn, Op.Size);
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Context.EmitLdc_I4(GetImmShl(Op));
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftLeftLogical), TypesSll));
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EmitStvecWithUnsignedCast(Context, Op.Rd, Op.Size);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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else
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{
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EmitVectorUnaryOpZx(Context, () =>
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{
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Context.EmitLdc_I4(GetImmShl(Op));
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Context.Emit(OpCodes.Shl);
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});
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}
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}
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public static void Shll_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Shift = 8 << Op.Size;
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EmitVectorShImmWidenBinaryZx(Context, () => Context.Emit(OpCodes.Shl), Shift);
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}
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public static void Shrn_V(AILEmitterCtx Context)
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{
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EmitVectorShrImmNarrowOpZx(Context, Round: false);
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}
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public static void Sli_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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int Shift = GetImmShl(Op);
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ulong Mask = Shift != 0 ? ulong.MaxValue >> (64 - Shift) : 0;
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size);
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Context.EmitLdc_I4(Shift);
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Context.Emit(OpCodes.Shl);
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EmitVectorExtractZx(Context, Op.Rd, Index, Op.Size);
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Context.EmitLdc_I8((long)Mask);
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Context.Emit(OpCodes.And);
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Context.Emit(OpCodes.Or);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void Sqrshrn_S(AILEmitterCtx Context)
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{
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarSxSx);
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}
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public static void Sqrshrn_V(AILEmitterCtx Context)
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{
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorSxSx);
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}
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public static void Sqrshrun_S(AILEmitterCtx Context)
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{
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarSxZx);
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}
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public static void Sqrshrun_V(AILEmitterCtx Context)
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{
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorSxZx);
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}
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public static void Sqshrn_S(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarSxSx);
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}
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public static void Sqshrn_V(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorSxSx);
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}
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public static void Sqshrun_S(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarSxZx);
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}
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public static void Sqshrun_V(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorSxZx);
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}
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public static void Srshr_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpSx(Context, ShrImmFlags.Round);
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}
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public static void Srshr_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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if (AOptimizations.UseSse2 && Op.Size > 0
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&& Op.Size < 3)
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{
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Type[] TypesShs = new Type[] { VectorIntTypesPerSizeLog2[Op.Size], typeof(byte) };
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Type[] TypesAdd = new Type[] { VectorIntTypesPerSizeLog2[Op.Size], VectorIntTypesPerSizeLog2[Op.Size] };
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int Shift = GetImmShr(Op);
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int ESize = 8 << Op.Size;
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EmitLdvecWithSignedCast(Context, Op.Rn, Op.Size);
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Context.Emit(OpCodes.Dup);
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Context.EmitStvectmp();
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Context.EmitLdc_I4(ESize - Shift);
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftLeftLogical), TypesShs));
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Context.EmitLdc_I4(ESize - 1);
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical), TypesShs));
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Context.EmitLdvectmp();
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Context.EmitLdc_I4(Shift);
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightArithmetic), TypesShs));
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), TypesAdd));
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EmitStvecWithSignedCast(Context, Op.Rd, Op.Size);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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else
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{
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EmitVectorShrImmOpSx(Context, ShrImmFlags.Round);
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}
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}
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public static void Srsra_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpSx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate);
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}
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public static void Srsra_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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if (AOptimizations.UseSse2 && Op.Size > 0
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&& Op.Size < 3)
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{
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Type[] TypesShs = new Type[] { VectorIntTypesPerSizeLog2[Op.Size], typeof(byte) };
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Type[] TypesAdd = new Type[] { VectorIntTypesPerSizeLog2[Op.Size], VectorIntTypesPerSizeLog2[Op.Size] };
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int Shift = GetImmShr(Op);
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int ESize = 8 << Op.Size;
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EmitLdvecWithSignedCast(Context, Op.Rd, Op.Size);
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EmitLdvecWithSignedCast(Context, Op.Rn, Op.Size);
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Context.Emit(OpCodes.Dup);
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Context.EmitStvectmp();
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Context.EmitLdc_I4(ESize - Shift);
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftLeftLogical), TypesShs));
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Context.EmitLdc_I4(ESize - 1);
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical), TypesShs));
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Context.EmitLdvectmp();
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Context.EmitLdc_I4(Shift);
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightArithmetic), TypesShs));
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), TypesAdd));
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), TypesAdd));
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EmitStvecWithSignedCast(Context, Op.Rd, Op.Size);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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else
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{
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EmitVectorShrImmOpSx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate);
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}
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}
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public static void Sshl_V(AILEmitterCtx Context)
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{
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EmitVectorShl(Context, Signed: true);
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}
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public static void Sshll_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorShImmWidenBinarySx(Context, () => Context.Emit(OpCodes.Shl), GetImmShl(Op));
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}
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public static void Sshr_S(AILEmitterCtx Context)
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{
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EmitShrImmOp(Context, ShrImmFlags.ScalarSx);
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}
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public static void Sshr_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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if (AOptimizations.UseSse2 && Op.Size > 0
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&& Op.Size < 3)
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{
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Type[] TypesSra = new Type[] { VectorIntTypesPerSizeLog2[Op.Size], typeof(byte) };
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EmitLdvecWithSignedCast(Context, Op.Rn, Op.Size);
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Context.EmitLdc_I4(GetImmShr(Op));
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightArithmetic), TypesSra));
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EmitStvecWithSignedCast(Context, Op.Rd, Op.Size);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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else
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{
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EmitShrImmOp(Context, ShrImmFlags.VectorSx);
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}
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}
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public static void Ssra_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpSx(Context, ShrImmFlags.Accumulate);
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}
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public static void Ssra_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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if (AOptimizations.UseSse2 && Op.Size > 0
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&& Op.Size < 3)
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{
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Type[] TypesSra = new Type[] { VectorIntTypesPerSizeLog2[Op.Size], typeof(byte) };
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Type[] TypesAdd = new Type[] { VectorIntTypesPerSizeLog2[Op.Size], VectorIntTypesPerSizeLog2[Op.Size] };
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EmitLdvecWithSignedCast(Context, Op.Rd, Op.Size);
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EmitLdvecWithSignedCast(Context, Op.Rn, Op.Size);
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Context.EmitLdc_I4(GetImmShr(Op));
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightArithmetic), TypesSra));
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), TypesAdd));
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EmitStvecWithSignedCast(Context, Op.Rd, Op.Size);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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else
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{
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EmitVectorShrImmOpSx(Context, ShrImmFlags.Accumulate);
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}
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}
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public static void Uqrshrn_S(AILEmitterCtx Context)
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{
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarZxZx);
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}
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public static void Uqrshrn_V(AILEmitterCtx Context)
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{
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorZxZx);
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}
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public static void Uqshrn_S(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarZxZx);
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}
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public static void Uqshrn_V(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorZxZx);
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}
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public static void Urshr_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpZx(Context, ShrImmFlags.Round);
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}
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public static void Urshr_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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if (AOptimizations.UseSse2 && Op.Size > 0)
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{
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Type[] TypesShs = new Type[] { VectorUIntTypesPerSizeLog2[Op.Size], typeof(byte) };
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Type[] TypesAdd = new Type[] { VectorUIntTypesPerSizeLog2[Op.Size], VectorUIntTypesPerSizeLog2[Op.Size] };
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int Shift = GetImmShr(Op);
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int ESize = 8 << Op.Size;
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EmitLdvecWithUnsignedCast(Context, Op.Rn, Op.Size);
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Context.Emit(OpCodes.Dup);
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Context.EmitStvectmp();
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Context.EmitLdc_I4(ESize - Shift);
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftLeftLogical), TypesShs));
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Context.EmitLdc_I4(ESize - 1);
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical), TypesShs));
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Context.EmitLdvectmp();
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Context.EmitLdc_I4(Shift);
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical), TypesShs));
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), TypesAdd));
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EmitStvecWithUnsignedCast(Context, Op.Rd, Op.Size);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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else
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{
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EmitVectorShrImmOpZx(Context, ShrImmFlags.Round);
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}
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}
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public static void Ursra_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpZx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate);
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}
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public static void Ursra_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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if (AOptimizations.UseSse2 && Op.Size > 0)
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{
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Type[] TypesShs = new Type[] { VectorUIntTypesPerSizeLog2[Op.Size], typeof(byte) };
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Type[] TypesAdd = new Type[] { VectorUIntTypesPerSizeLog2[Op.Size], VectorUIntTypesPerSizeLog2[Op.Size] };
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int Shift = GetImmShr(Op);
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int ESize = 8 << Op.Size;
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EmitLdvecWithUnsignedCast(Context, Op.Rd, Op.Size);
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EmitLdvecWithUnsignedCast(Context, Op.Rn, Op.Size);
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Context.Emit(OpCodes.Dup);
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Context.EmitStvectmp();
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Context.EmitLdc_I4(ESize - Shift);
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftLeftLogical), TypesShs));
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Context.EmitLdc_I4(ESize - 1);
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical), TypesShs));
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Context.EmitLdvectmp();
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Context.EmitLdc_I4(Shift);
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical), TypesShs));
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), TypesAdd));
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), TypesAdd));
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EmitStvecWithUnsignedCast(Context, Op.Rd, Op.Size);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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else
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{
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EmitVectorShrImmOpZx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate);
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}
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}
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public static void Ushl_V(AILEmitterCtx Context)
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{
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EmitVectorShl(Context, Signed: false);
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}
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public static void Ushll_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorShImmWidenBinaryZx(Context, () => Context.Emit(OpCodes.Shl), GetImmShl(Op));
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}
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public static void Ushr_S(AILEmitterCtx Context)
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{
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EmitShrImmOp(Context, ShrImmFlags.ScalarZx);
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}
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public static void Ushr_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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if (AOptimizations.UseSse2 && Op.Size > 0)
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{
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Type[] TypesSrl = new Type[] { VectorUIntTypesPerSizeLog2[Op.Size], typeof(byte) };
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EmitLdvecWithUnsignedCast(Context, Op.Rn, Op.Size);
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Context.EmitLdc_I4(GetImmShr(Op));
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical), TypesSrl));
|
|
|
|
EmitStvecWithUnsignedCast(Context, Op.Rd, Op.Size);
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
{
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
EmitShrImmOp(Context, ShrImmFlags.VectorZx);
|
|
}
|
|
}
|
|
|
|
public static void Usra_S(AILEmitterCtx Context)
|
|
{
|
|
EmitScalarShrImmOpZx(Context, ShrImmFlags.Accumulate);
|
|
}
|
|
|
|
public static void Usra_V(AILEmitterCtx Context)
|
|
{
|
|
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
|
|
|
|
if (AOptimizations.UseSse2 && Op.Size > 0)
|
|
{
|
|
Type[] TypesSrl = new Type[] { VectorUIntTypesPerSizeLog2[Op.Size], typeof(byte) };
|
|
Type[] TypesAdd = new Type[] { VectorUIntTypesPerSizeLog2[Op.Size], VectorUIntTypesPerSizeLog2[Op.Size] };
|
|
|
|
EmitLdvecWithUnsignedCast(Context, Op.Rd, Op.Size);
|
|
EmitLdvecWithUnsignedCast(Context, Op.Rn, Op.Size);
|
|
|
|
Context.EmitLdc_I4(GetImmShr(Op));
|
|
|
|
Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical), TypesSrl));
|
|
Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), TypesAdd));
|
|
|
|
EmitStvecWithUnsignedCast(Context, Op.Rd, Op.Size);
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
{
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
EmitVectorShrImmOpZx(Context, ShrImmFlags.Accumulate);
|
|
}
|
|
}
|
|
|
|
private static void EmitVectorShl(AILEmitterCtx Context, bool Signed)
|
|
{
|
|
//This instruction shifts the value on vector A by the number of bits
|
|
//specified on the signed, lower 8 bits of vector B. If the shift value
|
|
//is greater or equal to the data size of each lane, then the result is zero.
|
|
//Additionally, negative shifts produces right shifts by the negated shift value.
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
|
|
|
int MaxShift = 8 << Op.Size;
|
|
|
|
Action Emit = () =>
|
|
{
|
|
AILLabel LblShl = new AILLabel();
|
|
AILLabel LblZero = new AILLabel();
|
|
AILLabel LblEnd = new AILLabel();
|
|
|
|
void EmitShift(OpCode ILOp)
|
|
{
|
|
Context.Emit(OpCodes.Dup);
|
|
|
|
Context.EmitLdc_I4(MaxShift);
|
|
|
|
Context.Emit(OpCodes.Bge_S, LblZero);
|
|
Context.Emit(ILOp);
|
|
Context.Emit(OpCodes.Br_S, LblEnd);
|
|
}
|
|
|
|
Context.Emit(OpCodes.Conv_I1);
|
|
Context.Emit(OpCodes.Dup);
|
|
|
|
Context.EmitLdc_I4(0);
|
|
|
|
Context.Emit(OpCodes.Bge_S, LblShl);
|
|
Context.Emit(OpCodes.Neg);
|
|
|
|
EmitShift(Signed
|
|
? OpCodes.Shr
|
|
: OpCodes.Shr_Un);
|
|
|
|
Context.MarkLabel(LblShl);
|
|
|
|
EmitShift(OpCodes.Shl);
|
|
|
|
Context.MarkLabel(LblZero);
|
|
|
|
Context.Emit(OpCodes.Pop);
|
|
Context.Emit(OpCodes.Pop);
|
|
|
|
Context.EmitLdc_I8(0);
|
|
|
|
Context.MarkLabel(LblEnd);
|
|
};
|
|
|
|
if (Signed)
|
|
{
|
|
EmitVectorBinaryOpSx(Context, Emit);
|
|
}
|
|
else
|
|
{
|
|
EmitVectorBinaryOpZx(Context, Emit);
|
|
}
|
|
}
|
|
|
|
[Flags]
|
|
private enum ShrImmFlags
|
|
{
|
|
Scalar = 1 << 0,
|
|
Signed = 1 << 1,
|
|
|
|
Round = 1 << 2,
|
|
Accumulate = 1 << 3,
|
|
|
|
ScalarSx = Scalar | Signed,
|
|
ScalarZx = Scalar,
|
|
|
|
VectorSx = Signed,
|
|
VectorZx = 0
|
|
}
|
|
|
|
private static void EmitScalarShrImmOpSx(AILEmitterCtx Context, ShrImmFlags Flags)
|
|
{
|
|
EmitShrImmOp(Context, ShrImmFlags.ScalarSx | Flags);
|
|
}
|
|
|
|
private static void EmitScalarShrImmOpZx(AILEmitterCtx Context, ShrImmFlags Flags)
|
|
{
|
|
EmitShrImmOp(Context, ShrImmFlags.ScalarZx | Flags);
|
|
}
|
|
|
|
private static void EmitVectorShrImmOpSx(AILEmitterCtx Context, ShrImmFlags Flags)
|
|
{
|
|
EmitShrImmOp(Context, ShrImmFlags.VectorSx | Flags);
|
|
}
|
|
|
|
private static void EmitVectorShrImmOpZx(AILEmitterCtx Context, ShrImmFlags Flags)
|
|
{
|
|
EmitShrImmOp(Context, ShrImmFlags.VectorZx | Flags);
|
|
}
|
|
|
|
private static void EmitShrImmOp(AILEmitterCtx Context, ShrImmFlags Flags)
|
|
{
|
|
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
|
|
|
|
bool Scalar = (Flags & ShrImmFlags.Scalar) != 0;
|
|
bool Signed = (Flags & ShrImmFlags.Signed) != 0;
|
|
bool Round = (Flags & ShrImmFlags.Round) != 0;
|
|
bool Accumulate = (Flags & ShrImmFlags.Accumulate) != 0;
|
|
|
|
int Shift = GetImmShr(Op);
|
|
|
|
long RoundConst = 1L << (Shift - 1);
|
|
|
|
int Bytes = Op.GetBitsCount() >> 3;
|
|
int Elems = !Scalar ? Bytes >> Op.Size : 1;
|
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
|
{
|
|
EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
|
|
|
|
if (Op.Size <= 2)
|
|
{
|
|
if (Round)
|
|
{
|
|
Context.EmitLdc_I8(RoundConst);
|
|
|
|
Context.Emit(OpCodes.Add);
|
|
}
|
|
|
|
Context.EmitLdc_I4(Shift);
|
|
|
|
Context.Emit(Signed ? OpCodes.Shr : OpCodes.Shr_Un);
|
|
}
|
|
else /* if (Op.Size == 3) */
|
|
{
|
|
EmitShrImm_64(Context, Signed, Round ? RoundConst : 0L, Shift);
|
|
}
|
|
|
|
if (Accumulate)
|
|
{
|
|
EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
|
|
|
|
Context.Emit(OpCodes.Add);
|
|
}
|
|
|
|
EmitVectorInsertTmp(Context, Index, Op.Size);
|
|
}
|
|
|
|
Context.EmitLdvectmp();
|
|
Context.EmitStvec(Op.Rd);
|
|
|
|
if ((Op.RegisterSize == ARegisterSize.SIMD64) || Scalar)
|
|
{
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
}
|
|
}
|
|
|
|
private static void EmitVectorShrImmNarrowOpZx(AILEmitterCtx Context, bool Round)
|
|
{
|
|
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
|
|
|
|
int Shift = GetImmShr(Op);
|
|
|
|
long RoundConst = 1L << (Shift - 1);
|
|
|
|
int Elems = 8 >> Op.Size;
|
|
|
|
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
|
|
|
|
if (Part != 0)
|
|
{
|
|
Context.EmitLdvec(Op.Rd);
|
|
Context.EmitStvectmp();
|
|
}
|
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
|
{
|
|
EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size + 1);
|
|
|
|
if (Round)
|
|
{
|
|
Context.EmitLdc_I8(RoundConst);
|
|
|
|
Context.Emit(OpCodes.Add);
|
|
}
|
|
|
|
Context.EmitLdc_I4(Shift);
|
|
|
|
Context.Emit(OpCodes.Shr_Un);
|
|
|
|
EmitVectorInsertTmp(Context, Part + Index, Op.Size);
|
|
}
|
|
|
|
Context.EmitLdvectmp();
|
|
Context.EmitStvec(Op.Rd);
|
|
|
|
if (Part == 0)
|
|
{
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
}
|
|
}
|
|
|
|
[Flags]
|
|
private enum ShrImmSaturatingNarrowFlags
|
|
{
|
|
Scalar = 1 << 0,
|
|
SignedSrc = 1 << 1,
|
|
SignedDst = 1 << 2,
|
|
|
|
Round = 1 << 3,
|
|
|
|
ScalarSxSx = Scalar | SignedSrc | SignedDst,
|
|
ScalarSxZx = Scalar | SignedSrc,
|
|
ScalarZxZx = Scalar,
|
|
|
|
VectorSxSx = SignedSrc | SignedDst,
|
|
VectorSxZx = SignedSrc,
|
|
VectorZxZx = 0
|
|
}
|
|
|
|
private static void EmitRoundShrImmSaturatingNarrowOp(AILEmitterCtx Context, ShrImmSaturatingNarrowFlags Flags)
|
|
{
|
|
EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.Round | Flags);
|
|
}
|
|
|
|
private static void EmitShrImmSaturatingNarrowOp(AILEmitterCtx Context, ShrImmSaturatingNarrowFlags Flags)
|
|
{
|
|
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
|
|
|
|
bool Scalar = (Flags & ShrImmSaturatingNarrowFlags.Scalar) != 0;
|
|
bool SignedSrc = (Flags & ShrImmSaturatingNarrowFlags.SignedSrc) != 0;
|
|
bool SignedDst = (Flags & ShrImmSaturatingNarrowFlags.SignedDst) != 0;
|
|
bool Round = (Flags & ShrImmSaturatingNarrowFlags.Round) != 0;
|
|
|
|
int Shift = GetImmShr(Op);
|
|
|
|
long RoundConst = 1L << (Shift - 1);
|
|
|
|
int Elems = !Scalar ? 8 >> Op.Size : 1;
|
|
|
|
int Part = !Scalar && (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0;
|
|
|
|
if (Scalar)
|
|
{
|
|
EmitVectorZeroLowerTmp(Context);
|
|
}
|
|
|
|
if (Part != 0)
|
|
{
|
|
Context.EmitLdvec(Op.Rd);
|
|
Context.EmitStvectmp();
|
|
}
|
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
|
{
|
|
EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, SignedSrc);
|
|
|
|
if (Op.Size <= 1 || !Round)
|
|
{
|
|
if (Round)
|
|
{
|
|
Context.EmitLdc_I8(RoundConst);
|
|
|
|
Context.Emit(OpCodes.Add);
|
|
}
|
|
|
|
Context.EmitLdc_I4(Shift);
|
|
|
|
Context.Emit(SignedSrc ? OpCodes.Shr : OpCodes.Shr_Un);
|
|
}
|
|
else /* if (Op.Size == 2 && Round) */
|
|
{
|
|
EmitShrImm_64(Context, SignedSrc, RoundConst, Shift); // Shift <= 32
|
|
}
|
|
|
|
EmitSatQ(Context, Op.Size, SignedSrc, SignedDst);
|
|
|
|
EmitVectorInsertTmp(Context, Part + Index, Op.Size);
|
|
}
|
|
|
|
Context.EmitLdvectmp();
|
|
Context.EmitStvec(Op.Rd);
|
|
|
|
if (Part == 0)
|
|
{
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
}
|
|
}
|
|
|
|
// Dst_64 = (Int(Src_64, Signed) + RoundConst) >> Shift;
|
|
private static void EmitShrImm_64(
|
|
AILEmitterCtx Context,
|
|
bool Signed,
|
|
long RoundConst,
|
|
int Shift)
|
|
{
|
|
Context.EmitLdc_I8(RoundConst);
|
|
Context.EmitLdc_I4(Shift);
|
|
|
|
ASoftFallback.EmitCall(Context, Signed
|
|
? nameof(ASoftFallback.SignedShrImm_64)
|
|
: nameof(ASoftFallback.UnsignedShrImm_64));
|
|
}
|
|
|
|
private static void EmitVectorShImmWidenBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
|
|
{
|
|
EmitVectorShImmWidenBinaryOp(Context, Emit, Imm, true);
|
|
}
|
|
|
|
private static void EmitVectorShImmWidenBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
|
|
{
|
|
EmitVectorShImmWidenBinaryOp(Context, Emit, Imm, false);
|
|
}
|
|
|
|
private static void EmitVectorShImmWidenBinaryOp(AILEmitterCtx Context, Action Emit, int Imm, bool Signed)
|
|
{
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
|
|
|
int Elems = 8 >> Op.Size;
|
|
|
|
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
|
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
|
{
|
|
EmitVectorExtract(Context, Op.Rn, Part + Index, Op.Size, Signed);
|
|
|
|
Context.EmitLdc_I4(Imm);
|
|
|
|
Emit();
|
|
|
|
EmitVectorInsertTmp(Context, Index, Op.Size + 1);
|
|
}
|
|
|
|
Context.EmitLdvectmp();
|
|
Context.EmitStvec(Op.Rd);
|
|
}
|
|
}
|
|
}
|