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Ryujinx-ChocolArm64
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A C# ARM64 emulator that works translating ARM code to CIL
174 Commits 1 Branch 0 Tags 888 KiB
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gdkchan 8d5a48ba0a Misc. CPU optimizations (#575) 
* Add optimizations related to caller/callee saved registers, thread synchronization and disable tier 0

* Refactoring

* Add a config entry to enable or disable the reg load/store opt.

* Remove unnecessary register state stores for calls when the callee is know

* Rename IoType to VarType

* Enable tier 0 while fixing some perf issues related to tier 0

* Small tweak -- Compile before adding to the cache, to avoid lags

* Add required config entry
 		2019-02-28 13:03:31 +11:00
Decoders Implement fixed-point variant of the UCVTF and SCVTF instructions (#578) 2019-02-23 20:52:48 -03:00
Events Optimize address translation and write tracking on the MMU (#571) 2019-02-24 18:24:35 +11:00
Instructions Misc. CPU optimizations (#575) 2019-02-28 13:03:31 +11:00
Memory Optimize address translation and write tracking on the MMU (#571) 2019-02-24 18:24:35 +11:00
State ARM exclusive monitor and multicore fixes (#589) 2019-02-19 10:52:06 +11:00
Translation Misc. CPU optimizations (#575) 2019-02-28 13:03:31 +11:00
ChocolArm64.csproj ARM exclusive monitor and multicore fixes (#589) 2019-02-19 10:52:06 +11:00
CpuThread.cs ARM exclusive monitor and multicore fixes (#589) 2019-02-19 10:52:06 +11:00
OpCodeTable.cs Implement fixed-point variant of the UCVTF and SCVTF instructions (#578) 2019-02-23 20:52:48 -03:00
Optimizations.cs Misc. CPU optimizations (#575) 2019-02-28 13:03:31 +11:00