Ryujinx/ARMeilleure/State/V128.cs

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Add a new JIT compiler for CPU code (#693) * Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
using System;
namespace ARMeilleure.State
{
public struct V128 : IEquatable<V128>
{
private ulong _e0;
private ulong _e1;
private static V128 _zero = new V128(0, 0);
public static V128 Zero => _zero;
public V128(float value) : this(value, 0, 0, 0) { }
public V128(double value) : this(value, 0) { }
public V128(float e0, float e1, float e2, float e3)
{
_e0 = (ulong)(uint)BitConverter.SingleToInt32Bits(e0) << 0;
_e0 |= (ulong)(uint)BitConverter.SingleToInt32Bits(e1) << 32;
_e1 = (ulong)(uint)BitConverter.SingleToInt32Bits(e2) << 0;
_e1 |= (ulong)(uint)BitConverter.SingleToInt32Bits(e3) << 32;
}
public V128(double e0, double e1)
{
_e0 = (ulong)BitConverter.DoubleToInt64Bits(e0);
_e1 = (ulong)BitConverter.DoubleToInt64Bits(e1);
}
public V128(int e0, int e1, int e2, int e3)
{
_e0 = (ulong)(uint)e0 << 0;
_e0 |= (ulong)(uint)e1 << 32;
_e1 = (ulong)(uint)e2 << 0;
_e1 |= (ulong)(uint)e3 << 32;
}
public V128(uint e0, uint e1, uint e2, uint e3)
{
_e0 = (ulong)e0 << 0;
_e0 |= (ulong)e1 << 32;
_e1 = (ulong)e2 << 0;
_e1 |= (ulong)e3 << 32;
}
public V128(long e0, long e1)
{
_e0 = (ulong)e0;
_e1 = (ulong)e1;
}
public V128(ulong e0, ulong e1)
{
_e0 = e0;
_e1 = e1;
}
public V128(byte[] data)
{
_e0 = (ulong)BitConverter.ToInt64(data, 0);
_e1 = (ulong)BitConverter.ToInt64(data, 8);
}
public void Insert(int index, uint value)
{
switch (index)
{
case 0: _e0 = (_e0 & 0xffffffff00000000) | ((ulong)value << 0); break;
case 1: _e0 = (_e0 & 0x00000000ffffffff) | ((ulong)value << 32); break;
case 2: _e1 = (_e1 & 0xffffffff00000000) | ((ulong)value << 0); break;
case 3: _e1 = (_e1 & 0x00000000ffffffff) | ((ulong)value << 32); break;
default: throw new ArgumentOutOfRangeException(nameof(index));
}
}
public void Insert(int index, ulong value)
{
switch (index)
{
case 0: _e0 = value; break;
case 1: _e1 = value; break;
default: throw new ArgumentOutOfRangeException(nameof(index));
}
}
public float AsFloat()
{
return GetFloat(0);
}
public double AsDouble()
{
return GetDouble(0);
}
public float GetFloat(int index)
{
return BitConverter.Int32BitsToSingle(GetInt32(index));
}
public double GetDouble(int index)
{
return BitConverter.Int64BitsToDouble(GetInt64(index));
}
public int GetInt32(int index) => (int)GetUInt32(index);
public long GetInt64(int index) => (long)GetUInt64(index);
public uint GetUInt32(int index)
{
switch (index)
{
case 0: return (uint)(_e0 >> 0);
case 1: return (uint)(_e0 >> 32);
case 2: return (uint)(_e1 >> 0);
case 3: return (uint)(_e1 >> 32);
}
throw new ArgumentOutOfRangeException(nameof(index));
}
public ulong GetUInt64(int index)
{
switch (index)
{
case 0: return _e0;
case 1: return _e1;
}
throw new ArgumentOutOfRangeException(nameof(index));
}
public byte[] ToArray()
{
byte[] e0Data = BitConverter.GetBytes(_e0);
byte[] e1Data = BitConverter.GetBytes(_e1);
byte[] data = new byte[16];
Buffer.BlockCopy(e0Data, 0, data, 0, 8);
Buffer.BlockCopy(e1Data, 0, data, 8, 8);
return data;
}
public override int GetHashCode()
{
return HashCode.Combine(_e0, _e1);
}
public static V128 operator ~(V128 x)
{
return new V128(~x._e0, ~x._e1);
}
public static V128 operator &(V128 x, V128 y)
{
return new V128(x._e0 & y._e0, x._e1 & y._e1);
}
public static V128 operator |(V128 x, V128 y)
{
return new V128(x._e0 | y._e0, x._e1 | y._e1);
}
public static V128 operator ^(V128 x, V128 y)
{
return new V128(x._e0 ^ y._e0, x._e1 ^ y._e1);
}
public static V128 operator <<(V128 x, int shift)
{
ulong shiftOut = x._e0 >> (64 - shift);
return new V128(x._e0 << shift, (x._e1 << shift) | shiftOut);
}
public static V128 operator >>(V128 x, int shift)
{
ulong shiftOut = x._e1 & ((1UL << shift) - 1);
return new V128((x._e0 >> shift) | (shiftOut << (64 - shift)), x._e1 >> shift);
}
public static bool operator ==(V128 x, V128 y)
{
return x.Equals(y);
}
public static bool operator !=(V128 x, V128 y)
{
return !x.Equals(y);
}
public override bool Equals(object obj)
{
return obj is V128 vector && Equals(vector);
}
public bool Equals(V128 other)
{
return other._e0 == _e0 && other._e1 == _e1;
}
public override string ToString()
{
return $"0x{_e1:X16}{_e0:X16}";
}
}
}