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Add BIC/ORR Vd.T, #imm
fast path (#2279)
* Add fast path for BIC Vd.T, #imm * Add fast path for ORR Vd.T, #imm * Set PTC version * Fixup Exception to InvalidOperationException
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@ -190,6 +190,15 @@ namespace ARMeilleure.Instructions
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return X86GetAllElements(context, BitConverter.DoubleToInt64Bits(value));
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}
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public static Operand X86GetAllElements(ArmEmitterContext context, short value)
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{
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ulong value1 = (ushort)value;
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ulong value2 = value1 << 16 | value1;
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ulong value4 = value2 << 32 | value2;
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return X86GetAllElements(context, (long)value4);
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}
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public static Operand X86GetAllElements(ArmEmitterContext context, int value)
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{
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Operand vector = context.VectorCreateScalar(Const(value));
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@ -1,6 +1,7 @@
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using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System;
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using System.Diagnostics;
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using static ARMeilleure.Instructions.InstEmitHelper;
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@ -64,10 +65,35 @@ namespace ARMeilleure.Instructions
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public static void Bic_Vi(ArmEmitterContext context)
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{
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EmitVectorImmBinaryOp(context, (op1, op2) =>
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if (Optimizations.UseSse2)
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{
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return context.BitwiseAnd(op1, context.BitwiseNot(op2));
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});
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OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
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int eSize = 8 << op.Size;
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Operand d = GetVec(op.Rd);
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Operand imm = eSize switch {
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16 => X86GetAllElements(context, (short)~op.Immediate),
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32 => X86GetAllElements(context, (int)~op.Immediate),
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_ => throw new InvalidOperationException($"Invalid element size {eSize}.")
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};
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Operand res = context.AddIntrinsic(Intrinsic.X86Pand, d, imm);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitVectorImmBinaryOp(context, (op1, op2) =>
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{
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return context.BitwiseAnd(op1, context.BitwiseNot(op2));
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});
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}
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}
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public static void Bif_V(ArmEmitterContext context)
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@ -278,7 +304,32 @@ namespace ARMeilleure.Instructions
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public static void Orr_Vi(ArmEmitterContext context)
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{
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EmitVectorImmBinaryOp(context, (op1, op2) => context.BitwiseOr(op1, op2));
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if (Optimizations.UseSse2)
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{
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OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
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int eSize = 8 << op.Size;
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Operand d = GetVec(op.Rd);
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Operand imm = eSize switch {
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16 => X86GetAllElements(context, (short)op.Immediate),
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32 => X86GetAllElements(context, (int)op.Immediate),
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_ => throw new InvalidOperationException($"Invalid element size {eSize}.")
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};
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Operand res = context.AddIntrinsic(Intrinsic.X86Por, d, imm);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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EmitVectorImmBinaryOp(context, (op1, op2) => context.BitwiseOr(op1, op2));
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}
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}
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public static void Rbit_V(ArmEmitterContext context)
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@ -28,7 +28,7 @@ namespace ARMeilleure.Translation.PTC
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private const string OuterHeaderMagicString = "PTCohd\0\0";
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private const string InnerHeaderMagicString = "PTCihd\0\0";
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private const uint InternalVersion = 2285; //! To be incremented manually for each change to the ARMeilleure project.
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private const uint InternalVersion = 2279; //! To be incremented manually for each change to the ARMeilleure project.
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private const string ActualDir = "0";
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private const string BackupDir = "1";
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