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https://github.com/Ryujinx/Ryujinx.git
synced 2024-09-10 13:43:17 +02:00
Add Sqdmulh_S, Sqdmulh_V, Sqrdmulh_S, Sqrdmulh_V instructions; add 6 Tests. Now all saturating methods are on ASoftFallback. (#334)
* Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update ASoftFallback.cs * Update CpuTestAlu.cs * Update CpuTestAluImm.cs * Update CpuTestAluRs.cs * Update CpuTestAluRx.cs * Update CpuTestBfm.cs * Update CpuTestCcmpImm.cs * Update CpuTestCcmpReg.cs * Update CpuTestCsel.cs * Update CpuTestMov.cs * Update CpuTestMul.cs * Update Ryujinx.Tests.csproj * Update Ryujinx.csproj * Update Luea.csproj * Update Ryujinx.ShaderTools.csproj * Address PR feedback (further tested). * Address PR feedback.
This commit is contained in:
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@ -380,8 +380,16 @@ namespace ChocolArm64
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SetA64("0>001110<<100000011110xxxxxxxxxx", AInstEmit.Sqabs_V, typeof(AOpCodeSimd));
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SetA64("0>001110<<100000011110xxxxxxxxxx", AInstEmit.Sqabs_V, typeof(AOpCodeSimd));
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SetA64("01011110xx1xxxxx000011xxxxxxxxxx", AInstEmit.Sqadd_S, typeof(AOpCodeSimdReg));
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SetA64("01011110xx1xxxxx000011xxxxxxxxxx", AInstEmit.Sqadd_S, typeof(AOpCodeSimdReg));
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SetA64("0>001110<<1xxxxx000011xxxxxxxxxx", AInstEmit.Sqadd_V, typeof(AOpCodeSimdReg));
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SetA64("0>001110<<1xxxxx000011xxxxxxxxxx", AInstEmit.Sqadd_V, typeof(AOpCodeSimdReg));
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SetA64("01011110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_S, typeof(AOpCodeSimdReg));
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SetA64("01011110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_S, typeof(AOpCodeSimdReg));
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SetA64("0x001110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_V, typeof(AOpCodeSimdReg));
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SetA64("01111110xx100000011110xxxxxxxxxx", AInstEmit.Sqneg_S, typeof(AOpCodeSimd));
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SetA64("01111110xx100000011110xxxxxxxxxx", AInstEmit.Sqneg_S, typeof(AOpCodeSimd));
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SetA64("0>101110<<100000011110xxxxxxxxxx", AInstEmit.Sqneg_V, typeof(AOpCodeSimd));
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SetA64("0>101110<<100000011110xxxxxxxxxx", AInstEmit.Sqneg_V, typeof(AOpCodeSimd));
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SetA64("01111110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_S, typeof(AOpCodeSimdReg));
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SetA64("01111110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_S, typeof(AOpCodeSimdReg));
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SetA64("0x101110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_V, typeof(AOpCodeSimdReg));
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SetA64("0x00111100>>>xxx100111xxxxxxxxxx", AInstEmit.Sqrshrn_V, typeof(AOpCodeSimdShImm));
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SetA64("0x00111100>>>xxx100111xxxxxxxxxx", AInstEmit.Sqrshrn_V, typeof(AOpCodeSimdShImm));
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SetA64("01011110xx1xxxxx001011xxxxxxxxxx", AInstEmit.Sqsub_S, typeof(AOpCodeSimdReg));
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SetA64("01011110xx1xxxxx001011xxxxxxxxxx", AInstEmit.Sqsub_S, typeof(AOpCodeSimdReg));
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SetA64("0>001110<<1xxxxx001011xxxxxxxxxx", AInstEmit.Sqsub_V, typeof(AOpCodeSimdReg));
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SetA64("0>001110<<1xxxxx001011xxxxxxxxxx", AInstEmit.Sqsub_V, typeof(AOpCodeSimdReg));
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@ -158,6 +158,42 @@ namespace ChocolArm64.Instruction
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Context.MarkLabel(LblTrue);
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Context.MarkLabel(LblTrue);
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}
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}
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private static void EmitDoublingMultiplyHighHalf(AILEmitterCtx Context, bool Round)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int ESize = 8 << Op.Size;
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Context.Emit(OpCodes.Mul);
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if (!Round)
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{
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Context.EmitAsr(ESize - 1);
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}
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else
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{
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long RoundConst = 1L << (ESize - 1);
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AILLabel LblTrue = new AILLabel();
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Context.EmitLsl(1);
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Context.EmitLdc_I8(RoundConst);
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Context.Emit(OpCodes.Add);
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Context.EmitAsr(ESize);
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Context.Emit(OpCodes.Dup);
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Context.EmitLdc_I8((long)int.MinValue);
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Context.Emit(OpCodes.Bne_Un_S, LblTrue);
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Context.Emit(OpCodes.Neg);
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Context.MarkLabel(LblTrue);
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}
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}
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private static void EmitHighNarrow(AILEmitterCtx Context, Action Emit, bool Round)
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private static void EmitHighNarrow(AILEmitterCtx Context, Action Emit, bool Round)
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{
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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@ -1040,6 +1076,16 @@ namespace ChocolArm64.Instruction
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EmitVectorSaturatingBinaryOpSx(Context, SaturatingFlags.Add);
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EmitVectorSaturatingBinaryOpSx(Context, SaturatingFlags.Add);
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}
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}
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public static void Sqdmulh_S(AILEmitterCtx Context)
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{
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EmitSaturatingBinaryOp(Context, () => EmitDoublingMultiplyHighHalf(Context, Round: false), SaturatingFlags.ScalarSx);
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}
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public static void Sqdmulh_V(AILEmitterCtx Context)
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{
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EmitSaturatingBinaryOp(Context, () => EmitDoublingMultiplyHighHalf(Context, Round: false), SaturatingFlags.VectorSx);
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}
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public static void Sqneg_S(AILEmitterCtx Context)
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public static void Sqneg_S(AILEmitterCtx Context)
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{
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{
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EmitScalarSaturatingUnaryOpSx(Context, () => Context.Emit(OpCodes.Neg));
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EmitScalarSaturatingUnaryOpSx(Context, () => Context.Emit(OpCodes.Neg));
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@ -1050,6 +1096,16 @@ namespace ChocolArm64.Instruction
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EmitVectorSaturatingUnaryOpSx(Context, () => Context.Emit(OpCodes.Neg));
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EmitVectorSaturatingUnaryOpSx(Context, () => Context.Emit(OpCodes.Neg));
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}
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}
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public static void Sqrdmulh_S(AILEmitterCtx Context)
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{
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EmitSaturatingBinaryOp(Context, () => EmitDoublingMultiplyHighHalf(Context, Round: true), SaturatingFlags.ScalarSx);
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}
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public static void Sqrdmulh_V(AILEmitterCtx Context)
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{
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EmitSaturatingBinaryOp(Context, () => EmitDoublingMultiplyHighHalf(Context, Round: true), SaturatingFlags.VectorSx);
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}
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public static void Sqsub_S(AILEmitterCtx Context)
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public static void Sqsub_S(AILEmitterCtx Context)
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{
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{
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EmitScalarSaturatingBinaryOpSx(Context, SaturatingFlags.Sub);
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EmitScalarSaturatingBinaryOpSx(Context, SaturatingFlags.Sub);
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@ -804,7 +804,7 @@ namespace ChocolArm64.Instruction
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ScalarZx = Scalar,
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ScalarZx = Scalar,
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VectorSx = Signed,
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VectorSx = Signed,
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VectorZx = 0,
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VectorZx = 0
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}
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}
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public static void EmitScalarSaturatingUnaryOpSx(AILEmitterCtx Context, Action Emit)
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public static void EmitScalarSaturatingUnaryOpSx(AILEmitterCtx Context, Action Emit)
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@ -837,7 +837,14 @@ namespace ChocolArm64.Instruction
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Emit();
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Emit();
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EmitUnarySignedSatQAbsOrNeg(Context, Op.Size);
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if (Op.Size <= 2)
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{
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EmitSatQ(Context, Op.Size, true, true);
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}
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else /* if (Op.Size == 3) */
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{
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EmitUnarySignedSatQAbsOrNeg(Context);
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}
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EmitVectorInsertTmp(Context, Index, Op.Size);
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EmitVectorInsertTmp(Context, Index, Op.Size);
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}
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}
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@ -853,25 +860,25 @@ namespace ChocolArm64.Instruction
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public static void EmitScalarSaturatingBinaryOpSx(AILEmitterCtx Context, SaturatingFlags Flags)
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public static void EmitScalarSaturatingBinaryOpSx(AILEmitterCtx Context, SaturatingFlags Flags)
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{
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{
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EmitSaturatingBinaryOp(Context, SaturatingFlags.ScalarSx | Flags);
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EmitSaturatingBinaryOp(Context, () => { }, SaturatingFlags.ScalarSx | Flags);
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}
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}
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public static void EmitScalarSaturatingBinaryOpZx(AILEmitterCtx Context, SaturatingFlags Flags)
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public static void EmitScalarSaturatingBinaryOpZx(AILEmitterCtx Context, SaturatingFlags Flags)
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{
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{
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EmitSaturatingBinaryOp(Context, SaturatingFlags.ScalarZx | Flags);
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EmitSaturatingBinaryOp(Context, () => { }, SaturatingFlags.ScalarZx | Flags);
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}
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}
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public static void EmitVectorSaturatingBinaryOpSx(AILEmitterCtx Context, SaturatingFlags Flags)
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public static void EmitVectorSaturatingBinaryOpSx(AILEmitterCtx Context, SaturatingFlags Flags)
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{
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{
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EmitSaturatingBinaryOp(Context, SaturatingFlags.VectorSx | Flags);
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EmitSaturatingBinaryOp(Context, () => { }, SaturatingFlags.VectorSx | Flags);
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}
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}
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public static void EmitVectorSaturatingBinaryOpZx(AILEmitterCtx Context, SaturatingFlags Flags)
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public static void EmitVectorSaturatingBinaryOpZx(AILEmitterCtx Context, SaturatingFlags Flags)
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{
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{
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EmitSaturatingBinaryOp(Context, SaturatingFlags.VectorZx | Flags);
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EmitSaturatingBinaryOp(Context, () => { }, SaturatingFlags.VectorZx | Flags);
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}
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}
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public static void EmitSaturatingBinaryOp(AILEmitterCtx Context, SaturatingFlags Flags)
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public static void EmitSaturatingBinaryOp(AILEmitterCtx Context, Action Emit, SaturatingFlags Flags)
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{
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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@ -940,6 +947,20 @@ namespace ChocolArm64.Instruction
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EmitVectorInsertTmp(Context, Index, Op.Size);
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EmitVectorInsertTmp(Context, Index, Op.Size);
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}
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}
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}
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}
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else
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{
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
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EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, Index, Op.Size, Signed);
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Emit();
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EmitSatQ(Context, Op.Size, true, Signed);
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EmitVectorInsertTmp(Context, Index, Op.Size);
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}
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}
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Context.EmitLdvectmp();
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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Context.EmitStvec(Op.Rd);
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@ -1080,29 +1101,17 @@ namespace ChocolArm64.Instruction
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}
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}
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}
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}
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// TSrc (8bit, 16bit, 32bit, 64bit) == TDst (8bit, 16bit, 32bit, 64bit); signed.
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// TSrc (64bit) == TDst (64bit); signed.
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public static void EmitUnarySignedSatQAbsOrNeg(AILEmitterCtx Context, int Size)
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public static void EmitUnarySignedSatQAbsOrNeg(AILEmitterCtx Context)
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{
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{
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int ESize = 8 << Size;
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if (((AOpCodeSimd)Context.CurrOp).Size < 3)
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{
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throw new InvalidOperationException();
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}
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long TMaxValue = (1L << (ESize - 1)) - 1L;
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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long TMinValue = -(1L << (ESize - 1));
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AILLabel LblFalse = new AILLabel();
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.UnarySignedSatQAbsOrNeg));
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Context.Emit(OpCodes.Dup);
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Context.Emit(OpCodes.Neg);
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Context.EmitLdc_I8(TMinValue);
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Context.Emit(OpCodes.Ceq);
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Context.Emit(OpCodes.Brfalse_S, LblFalse);
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Context.Emit(OpCodes.Pop);
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EmitSetFpsrQCFlag(Context);
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Context.EmitLdc_I8(TMaxValue);
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Context.MarkLabel(LblFalse);
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}
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}
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// TSrcs (64bit) == TDst (64bit); signed, unsigned.
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// TSrcs (64bit) == TDst (64bit); signed, unsigned.
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@ -1150,22 +1159,6 @@ namespace ChocolArm64.Instruction
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: nameof(ASoftFallback.BinaryUnsignedSatQAcc));
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: nameof(ASoftFallback.BinaryUnsignedSatQAcc));
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}
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}
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public static void EmitSetFpsrQCFlag(AILEmitterCtx Context)
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{
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const int QCFlagBit = 27;
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Fpsr));
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Context.EmitLdc_I4(1 << QCFlagBit);
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Context.Emit(OpCodes.Or);
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Context.EmitCallPropSet(typeof(AThreadState), nameof(AThreadState.Fpsr));
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}
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public static void EmitScalarSet(AILEmitterCtx Context, int Reg, int Size)
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public static void EmitScalarSet(AILEmitterCtx Context, int Reg, int Size)
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{
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{
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EmitVectorZeroAll(Context, Reg);
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EmitVectorZeroAll(Context, Reg);
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@ -11,6 +11,107 @@ namespace ChocolArm64.Instruction
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Context.EmitCall(typeof(ASoftFallback), MthdName);
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Context.EmitCall(typeof(ASoftFallback), MthdName);
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}
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}
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#region "Saturating"
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public static long SignedSrcSignedDstSatQ(long op, int Size, AThreadState State)
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{
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int ESize = 8 << Size;
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long TMaxValue = (1L << (ESize - 1)) - 1L;
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long TMinValue = -(1L << (ESize - 1));
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if (op > TMaxValue)
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{
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SetFpsrQCFlag(State);
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return TMaxValue;
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}
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else if (op < TMinValue)
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{
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SetFpsrQCFlag(State);
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return TMinValue;
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}
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else
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{
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return op;
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}
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}
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public static ulong SignedSrcUnsignedDstSatQ(long op, int Size, AThreadState State)
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{
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int ESize = 8 << Size;
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ulong TMaxValue = (1UL << ESize) - 1UL;
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ulong TMinValue = 0UL;
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if (op > (long)TMaxValue)
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{
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SetFpsrQCFlag(State);
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return TMaxValue;
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}
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else if (op < (long)TMinValue)
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{
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SetFpsrQCFlag(State);
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return TMinValue;
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}
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else
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{
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return (ulong)op;
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}
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}
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public static long UnsignedSrcSignedDstSatQ(ulong op, int Size, AThreadState State)
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{
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int ESize = 8 << Size;
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long TMaxValue = (1L << (ESize - 1)) - 1L;
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if (op > (ulong)TMaxValue)
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{
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SetFpsrQCFlag(State);
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return TMaxValue;
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}
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else
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{
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return (long)op;
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}
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}
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public static ulong UnsignedSrcUnsignedDstSatQ(ulong op, int Size, AThreadState State)
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{
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int ESize = 8 << Size;
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ulong TMaxValue = (1UL << ESize) - 1UL;
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if (op > TMaxValue)
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{
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SetFpsrQCFlag(State);
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return TMaxValue;
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}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return op;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
public static long UnarySignedSatQAbsOrNeg(long op, AThreadState State)
|
||||||
|
{
|
||||||
|
if (op == long.MinValue)
|
||||||
|
{
|
||||||
|
SetFpsrQCFlag(State);
|
||||||
|
|
||||||
|
return long.MaxValue;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return op;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
public static long BinarySignedSatQAdd(long op1, long op2, AThreadState State)
|
public static long BinarySignedSatQAdd(long op1, long op2, AThreadState State)
|
||||||
{
|
{
|
||||||
long Add = op1 + op2;
|
long Add = op1 + op2;
|
||||||
@ -185,99 +286,15 @@ namespace ChocolArm64.Instruction
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
public static long SignedSrcSignedDstSatQ(long op, int Size, AThreadState State)
|
|
||||||
{
|
|
||||||
int ESize = 8 << Size;
|
|
||||||
|
|
||||||
long TMaxValue = (1L << (ESize - 1)) - 1L;
|
|
||||||
long TMinValue = -(1L << (ESize - 1));
|
|
||||||
|
|
||||||
if (op > TMaxValue)
|
|
||||||
{
|
|
||||||
SetFpsrQCFlag(State);
|
|
||||||
|
|
||||||
return TMaxValue;
|
|
||||||
}
|
|
||||||
else if (op < TMinValue)
|
|
||||||
{
|
|
||||||
SetFpsrQCFlag(State);
|
|
||||||
|
|
||||||
return TMinValue;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
return op;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
public static ulong SignedSrcUnsignedDstSatQ(long op, int Size, AThreadState State)
|
|
||||||
{
|
|
||||||
int ESize = 8 << Size;
|
|
||||||
|
|
||||||
ulong TMaxValue = (1UL << ESize) - 1UL;
|
|
||||||
ulong TMinValue = 0UL;
|
|
||||||
|
|
||||||
if (op > (long)TMaxValue)
|
|
||||||
{
|
|
||||||
SetFpsrQCFlag(State);
|
|
||||||
|
|
||||||
return TMaxValue;
|
|
||||||
}
|
|
||||||
else if (op < (long)TMinValue)
|
|
||||||
{
|
|
||||||
SetFpsrQCFlag(State);
|
|
||||||
|
|
||||||
return TMinValue;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
return (ulong)op;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
public static long UnsignedSrcSignedDstSatQ(ulong op, int Size, AThreadState State)
|
|
||||||
{
|
|
||||||
int ESize = 8 << Size;
|
|
||||||
|
|
||||||
long TMaxValue = (1L << (ESize - 1)) - 1L;
|
|
||||||
|
|
||||||
if (op > (ulong)TMaxValue)
|
|
||||||
{
|
|
||||||
SetFpsrQCFlag(State);
|
|
||||||
|
|
||||||
return TMaxValue;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
return (long)op;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
public static ulong UnsignedSrcUnsignedDstSatQ(ulong op, int Size, AThreadState State)
|
|
||||||
{
|
|
||||||
int ESize = 8 << Size;
|
|
||||||
|
|
||||||
ulong TMaxValue = (1UL << ESize) - 1UL;
|
|
||||||
|
|
||||||
if (op > TMaxValue)
|
|
||||||
{
|
|
||||||
SetFpsrQCFlag(State);
|
|
||||||
|
|
||||||
return TMaxValue;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
return op;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
private static void SetFpsrQCFlag(AThreadState State)
|
private static void SetFpsrQCFlag(AThreadState State)
|
||||||
{
|
{
|
||||||
const int QCFlagBit = 27;
|
const int QCFlagBit = 27;
|
||||||
|
|
||||||
State.Fpsr |= 1 << QCFlagBit;
|
State.Fpsr |= 1 << QCFlagBit;
|
||||||
}
|
}
|
||||||
|
#endregion
|
||||||
|
|
||||||
|
#region "Count"
|
||||||
public static ulong CountLeadingSigns(ulong Value, int Size)
|
public static ulong CountLeadingSigns(ulong Value, int Size)
|
||||||
{
|
{
|
||||||
Value ^= Value >> 1;
|
Value ^= Value >> 1;
|
||||||
@ -325,7 +342,9 @@ namespace ChocolArm64.Instruction
|
|||||||
|
|
||||||
return (Value >> 4) + (Value & 0x0f);
|
return (Value >> 4) + (Value & 0x0f);
|
||||||
}
|
}
|
||||||
|
#endregion
|
||||||
|
|
||||||
|
#region "Crc32"
|
||||||
private const uint Crc32RevPoly = 0xedb88320;
|
private const uint Crc32RevPoly = 0xedb88320;
|
||||||
private const uint Crc32cRevPoly = 0x82f63b78;
|
private const uint Crc32cRevPoly = 0x82f63b78;
|
||||||
|
|
||||||
@ -384,7 +403,9 @@ namespace ChocolArm64.Instruction
|
|||||||
|
|
||||||
return Crc;
|
return Crc;
|
||||||
}
|
}
|
||||||
|
#endregion
|
||||||
|
|
||||||
|
#region "Reverse"
|
||||||
public static uint ReverseBits8(uint Value)
|
public static uint ReverseBits8(uint Value)
|
||||||
{
|
{
|
||||||
Value = ((Value & 0xaa) >> 1) | ((Value & 0x55) << 1);
|
Value = ((Value & 0xaa) >> 1) | ((Value & 0x55) << 1);
|
||||||
@ -453,7 +474,9 @@ namespace ChocolArm64.Instruction
|
|||||||
|
|
||||||
throw new ArgumentException(nameof(Size));
|
throw new ArgumentException(nameof(Size));
|
||||||
}
|
}
|
||||||
|
#endregion
|
||||||
|
|
||||||
|
#region "MultiplyHigh"
|
||||||
public static long SMulHi128(long LHS, long RHS)
|
public static long SMulHi128(long LHS, long RHS)
|
||||||
{
|
{
|
||||||
long Result = (long)UMulHi128((ulong)LHS, (ulong)RHS);
|
long Result = (long)UMulHi128((ulong)LHS, (ulong)RHS);
|
||||||
@ -479,5 +502,6 @@ namespace ChocolArm64.Instruction
|
|||||||
|
|
||||||
return LHigh * RHigh + Z0 + (Z1 >> 32);
|
return LHigh * RHigh + Z0 + (Z1 >> 32);
|
||||||
}
|
}
|
||||||
|
#endregion
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -1,9 +1,9 @@
|
|||||||
<Project Sdk="Microsoft.NET.Sdk">
|
<Project Sdk="Microsoft.NET.Sdk">
|
||||||
|
|
||||||
<PropertyGroup>
|
<PropertyGroup>
|
||||||
<OutputType>Exe</OutputType>
|
|
||||||
<TargetFramework>netcoreapp2.1</TargetFramework>
|
<TargetFramework>netcoreapp2.1</TargetFramework>
|
||||||
<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
|
<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
|
||||||
|
<OutputType>Exe</OutputType>
|
||||||
</PropertyGroup>
|
</PropertyGroup>
|
||||||
|
|
||||||
</Project>
|
</Project>
|
||||||
|
@ -1,13 +1,13 @@
|
|||||||
<Project Sdk="Microsoft.NET.Sdk">
|
<Project Sdk="Microsoft.NET.Sdk">
|
||||||
|
|
||||||
|
<PropertyGroup>
|
||||||
|
<TargetFramework>netcoreapp2.1</TargetFramework>
|
||||||
|
<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
|
||||||
|
<OutputType>Exe</OutputType>
|
||||||
|
</PropertyGroup>
|
||||||
|
|
||||||
<ItemGroup>
|
<ItemGroup>
|
||||||
<ProjectReference Include="..\Ryujinx.Graphics\Ryujinx.Graphics.csproj" />
|
<ProjectReference Include="..\Ryujinx.Graphics\Ryujinx.Graphics.csproj" />
|
||||||
</ItemGroup>
|
</ItemGroup>
|
||||||
|
|
||||||
<PropertyGroup>
|
|
||||||
<OutputType>Exe</OutputType>
|
|
||||||
<TargetFramework>netcoreapp2.1</TargetFramework>
|
|
||||||
<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
|
|
||||||
</PropertyGroup>
|
|
||||||
|
|
||||||
</Project>
|
</Project>
|
||||||
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
using Tester;
|
using Tester;
|
||||||
using Tester.Types;
|
using Tester.Types;
|
||||||
|
|
||||||
[Category("Alu"), Ignore("Tested: first half of 2018.")]
|
[Category("Alu"), Ignore("Tested: second half of 2018.")]
|
||||||
public sealed class CpuTestAlu : CpuTest
|
public sealed class CpuTestAlu : CpuTest
|
||||||
{
|
{
|
||||||
#if Alu
|
#if Alu
|
||||||
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
using Tester;
|
using Tester;
|
||||||
using Tester.Types;
|
using Tester.Types;
|
||||||
|
|
||||||
[Category("AluImm"), Ignore("Tested: first half of 2018.")]
|
[Category("AluImm"), Ignore("Tested: second half of 2018.")]
|
||||||
public sealed class CpuTestAluImm : CpuTest
|
public sealed class CpuTestAluImm : CpuTest
|
||||||
{
|
{
|
||||||
#if AluImm
|
#if AluImm
|
||||||
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
using Tester;
|
using Tester;
|
||||||
using Tester.Types;
|
using Tester.Types;
|
||||||
|
|
||||||
[Category("AluRs"), Ignore("Tested: first half of 2018.")]
|
[Category("AluRs"), Ignore("Tested: second half of 2018.")]
|
||||||
public sealed class CpuTestAluRs : CpuTest
|
public sealed class CpuTestAluRs : CpuTest
|
||||||
{
|
{
|
||||||
#if AluRs
|
#if AluRs
|
||||||
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
using Tester;
|
using Tester;
|
||||||
using Tester.Types;
|
using Tester.Types;
|
||||||
|
|
||||||
[Category("AluRx"), Ignore("Tested: first half of 2018.")]
|
[Category("AluRx"), Ignore("Tested: second half of 2018.")]
|
||||||
public sealed class CpuTestAluRx : CpuTest
|
public sealed class CpuTestAluRx : CpuTest
|
||||||
{
|
{
|
||||||
#if AluRx
|
#if AluRx
|
||||||
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
using Tester;
|
using Tester;
|
||||||
using Tester.Types;
|
using Tester.Types;
|
||||||
|
|
||||||
[Category("Bfm"), Ignore("Tested: first half of 2018.")]
|
[Category("Bfm"), Ignore("Tested: second half of 2018.")]
|
||||||
public sealed class CpuTestBfm : CpuTest
|
public sealed class CpuTestBfm : CpuTest
|
||||||
{
|
{
|
||||||
#if Bfm
|
#if Bfm
|
||||||
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
using Tester;
|
using Tester;
|
||||||
using Tester.Types;
|
using Tester.Types;
|
||||||
|
|
||||||
[Category("CcmpImm"), Ignore("Tested: first half of 2018.")]
|
[Category("CcmpImm"), Ignore("Tested: second half of 2018.")]
|
||||||
public sealed class CpuTestCcmpImm : CpuTest
|
public sealed class CpuTestCcmpImm : CpuTest
|
||||||
{
|
{
|
||||||
#if CcmpImm
|
#if CcmpImm
|
||||||
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
using Tester;
|
using Tester;
|
||||||
using Tester.Types;
|
using Tester.Types;
|
||||||
|
|
||||||
[Category("CcmpReg"), Ignore("Tested: first half of 2018.")]
|
[Category("CcmpReg"), Ignore("Tested: second half of 2018.")]
|
||||||
public sealed class CpuTestCcmpReg : CpuTest
|
public sealed class CpuTestCcmpReg : CpuTest
|
||||||
{
|
{
|
||||||
#if CcmpReg
|
#if CcmpReg
|
||||||
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
using Tester;
|
using Tester;
|
||||||
using Tester.Types;
|
using Tester.Types;
|
||||||
|
|
||||||
[Category("Csel"), Ignore("Tested: first half of 2018.")]
|
[Category("Csel"), Ignore("Tested: second half of 2018.")]
|
||||||
public sealed class CpuTestCsel : CpuTest
|
public sealed class CpuTestCsel : CpuTest
|
||||||
{
|
{
|
||||||
#if Csel
|
#if Csel
|
||||||
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
using Tester;
|
using Tester;
|
||||||
using Tester.Types;
|
using Tester.Types;
|
||||||
|
|
||||||
[Category("Mov"), Ignore("Tested: first half of 2018.")]
|
[Category("Mov"), Ignore("Tested: second half of 2018.")]
|
||||||
public sealed class CpuTestMov : CpuTest
|
public sealed class CpuTestMov : CpuTest
|
||||||
{
|
{
|
||||||
#if Mov
|
#if Mov
|
||||||
|
@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
using Tester;
|
using Tester;
|
||||||
using Tester.Types;
|
using Tester.Types;
|
||||||
|
|
||||||
[Category("Mul"), Ignore("Tested: first half of 2018.")]
|
[Category("Mul"), Ignore("Tested: second half of 2018.")]
|
||||||
public sealed class CpuTestMul : CpuTest
|
public sealed class CpuTestMul : CpuTest
|
||||||
{
|
{
|
||||||
#if Mul
|
#if Mul
|
||||||
|
@ -90,7 +90,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
private const int RndCnt = 1;
|
private const int RndCnt = 1;
|
||||||
|
|
||||||
[Test, Description("ABS <V><d>, <V><n>")]
|
[Test, Description("ABS <V><d>, <V><n>")]
|
||||||
public void Abs_S_D([Values(0u)] uint Rd,
|
public void Abs_S_D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
||||||
@ -115,7 +115,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("ABS <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("ABS <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Abs_V_8B_4H_2S([Values(0u)] uint Rd,
|
public void Abs_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -142,7 +142,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("ABS <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("ABS <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Abs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
public void Abs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -169,7 +169,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("ADDP <V><d>, <Vn>.<T>")]
|
[Test, Description("ADDP <V><d>, <Vn>.<T>")]
|
||||||
public void Addp_S_2DD([Values(0u)] uint Rd,
|
public void Addp_S_2DD([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
||||||
@ -194,7 +194,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("ADDV <V><d>, <Vn>.<T>")]
|
[Test, Description("ADDV <V><d>, <Vn>.<T>")]
|
||||||
public void Addv_V_8BB_4HH([Values(0u)] uint Rd,
|
public void Addv_V_8BB_4HH([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong A,
|
||||||
@ -221,7 +221,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("ADDV <V><d>, <Vn>.<T>")]
|
[Test, Description("ADDV <V><d>, <Vn>.<T>")]
|
||||||
public void Addv_V_16BB_8HH_4SS([Values(0u)] uint Rd,
|
public void Addv_V_16BB_8HH_4SS([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -248,7 +248,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CLS <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("CLS <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Cls_V_8B_4H_2S([Values(0u)] uint Rd,
|
public void Cls_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -275,7 +275,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CLS <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("CLS <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Cls_V_16B_8H_4S([Values(0u)] uint Rd,
|
public void Cls_V_16B_8H_4S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -302,7 +302,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CLZ <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("CLZ <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Clz_V_8B_4H_2S([Values(0u)] uint Rd,
|
public void Clz_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -329,7 +329,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CLZ <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("CLZ <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Clz_V_16B_8H_4S([Values(0u)] uint Rd,
|
public void Clz_V_16B_8H_4S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -356,7 +356,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CMEQ <V><d>, <V><n>, #0")]
|
[Test, Description("CMEQ <V><d>, <V><n>, #0")]
|
||||||
public void Cmeq_S_D([Values(0u)] uint Rd,
|
public void Cmeq_S_D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
||||||
@ -381,7 +381,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CMEQ <Vd>.<T>, <Vn>.<T>, #0")]
|
[Test, Description("CMEQ <Vd>.<T>, <Vn>.<T>, #0")]
|
||||||
public void Cmeq_V_8B_4H_2S([Values(0u)] uint Rd,
|
public void Cmeq_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -408,7 +408,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CMEQ <Vd>.<T>, <Vn>.<T>, #0")]
|
[Test, Description("CMEQ <Vd>.<T>, <Vn>.<T>, #0")]
|
||||||
public void Cmeq_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
public void Cmeq_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -435,7 +435,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CMGE <V><d>, <V><n>, #0")]
|
[Test, Description("CMGE <V><d>, <V><n>, #0")]
|
||||||
public void Cmge_S_D([Values(0u)] uint Rd,
|
public void Cmge_S_D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
||||||
@ -460,7 +460,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CMGE <Vd>.<T>, <Vn>.<T>, #0")]
|
[Test, Description("CMGE <Vd>.<T>, <Vn>.<T>, #0")]
|
||||||
public void Cmge_V_8B_4H_2S([Values(0u)] uint Rd,
|
public void Cmge_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -487,7 +487,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CMGE <Vd>.<T>, <Vn>.<T>, #0")]
|
[Test, Description("CMGE <Vd>.<T>, <Vn>.<T>, #0")]
|
||||||
public void Cmge_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
public void Cmge_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -514,7 +514,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CMGT <V><d>, <V><n>, #0")]
|
[Test, Description("CMGT <V><d>, <V><n>, #0")]
|
||||||
public void Cmgt_S_D([Values(0u)] uint Rd,
|
public void Cmgt_S_D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
||||||
@ -539,7 +539,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CMGT <Vd>.<T>, <Vn>.<T>, #0")]
|
[Test, Description("CMGT <Vd>.<T>, <Vn>.<T>, #0")]
|
||||||
public void Cmgt_V_8B_4H_2S([Values(0u)] uint Rd,
|
public void Cmgt_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -566,7 +566,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CMGT <Vd>.<T>, <Vn>.<T>, #0")]
|
[Test, Description("CMGT <Vd>.<T>, <Vn>.<T>, #0")]
|
||||||
public void Cmgt_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
public void Cmgt_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -593,7 +593,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CMLE <V><d>, <V><n>, #0")]
|
[Test, Description("CMLE <V><d>, <V><n>, #0")]
|
||||||
public void Cmle_S_D([Values(0u)] uint Rd,
|
public void Cmle_S_D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
||||||
@ -618,7 +618,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CMLE <Vd>.<T>, <Vn>.<T>, #0")]
|
[Test, Description("CMLE <Vd>.<T>, <Vn>.<T>, #0")]
|
||||||
public void Cmle_V_8B_4H_2S([Values(0u)] uint Rd,
|
public void Cmle_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -645,7 +645,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CMLE <Vd>.<T>, <Vn>.<T>, #0")]
|
[Test, Description("CMLE <Vd>.<T>, <Vn>.<T>, #0")]
|
||||||
public void Cmle_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
public void Cmle_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -672,7 +672,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CMLT <V><d>, <V><n>, #0")]
|
[Test, Description("CMLT <V><d>, <V><n>, #0")]
|
||||||
public void Cmlt_S_D([Values(0u)] uint Rd,
|
public void Cmlt_S_D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
||||||
@ -697,7 +697,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CMLT <Vd>.<T>, <Vn>.<T>, #0")]
|
[Test, Description("CMLT <Vd>.<T>, <Vn>.<T>, #0")]
|
||||||
public void Cmlt_V_8B_4H_2S([Values(0u)] uint Rd,
|
public void Cmlt_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -724,7 +724,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CMLT <Vd>.<T>, <Vn>.<T>, #0")]
|
[Test, Description("CMLT <Vd>.<T>, <Vn>.<T>, #0")]
|
||||||
public void Cmlt_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
public void Cmlt_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -751,7 +751,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CNT <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("CNT <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Cnt_V_8B([Values(0u)] uint Rd,
|
public void Cnt_V_8B([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
||||||
@ -776,7 +776,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("CNT <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("CNT <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Cnt_V_16B([Values(0u)] uint Rd,
|
public void Cnt_V_16B([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
||||||
@ -801,7 +801,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("NEG <V><d>, <V><n>")]
|
[Test, Description("NEG <V><d>, <V><n>")]
|
||||||
public void Neg_S_D([Values(0u)] uint Rd,
|
public void Neg_S_D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
|
||||||
@ -826,7 +826,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("NEG <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("NEG <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Neg_V_8B_4H_2S([Values(0u)] uint Rd,
|
public void Neg_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -853,7 +853,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("NEG <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("NEG <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Neg_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
public void Neg_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -880,7 +880,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("NOT <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("NOT <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Not_V_8B([Values(0u)] uint Rd,
|
public void Not_V_8B([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
||||||
@ -905,7 +905,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("NOT <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("NOT <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Not_V_16B([Values(0u)] uint Rd,
|
public void Not_V_16B([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
||||||
@ -930,7 +930,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("RBIT <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("RBIT <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Rbit_V_8B([Values(0u)] uint Rd,
|
public void Rbit_V_8B([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
||||||
@ -955,7 +955,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("RBIT <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("RBIT <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Rbit_V_16B([Values(0u)] uint Rd,
|
public void Rbit_V_16B([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
||||||
@ -980,7 +980,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("REV16 <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("REV16 <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Rev16_V_8B([Values(0u)] uint Rd,
|
public void Rev16_V_8B([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
||||||
@ -1005,7 +1005,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("REV16 <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("REV16 <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Rev16_V_16B([Values(0u)] uint Rd,
|
public void Rev16_V_16B([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
|
||||||
@ -1030,7 +1030,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("REV32 <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("REV32 <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Rev32_V_8B_4H([Values(0u)] uint Rd,
|
public void Rev32_V_8B_4H([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1057,7 +1057,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("REV32 <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("REV32 <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Rev32_V_16B_8H([Values(0u)] uint Rd,
|
public void Rev32_V_16B_8H([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1084,7 +1084,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("REV64 <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("REV64 <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Rev64_V_8B_4H_2S([Values(0u)] uint Rd,
|
public void Rev64_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1111,7 +1111,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("REV64 <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("REV64 <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Rev64_V_16B_8H_4S([Values(0u)] uint Rd,
|
public void Rev64_V_16B_8H_4S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1138,7 +1138,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("SQABS <V><d>, <V><n>")]
|
[Test, Description("SQABS <V><d>, <V><n>")]
|
||||||
public void Sqabs_S_B_H_S_D([Values(0u)] uint Rd,
|
public void Sqabs_S_B_H_S_D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1169,7 +1169,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("SQABS <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("SQABS <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Sqabs_V_8B_4H_2S([Values(0u)] uint Rd,
|
public void Sqabs_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1200,7 +1200,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("SQABS <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("SQABS <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Sqabs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
public void Sqabs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1231,7 +1231,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("SQNEG <V><d>, <V><n>")]
|
[Test, Description("SQNEG <V><d>, <V><n>")]
|
||||||
public void Sqneg_S_B_H_S_D([Values(0u)] uint Rd,
|
public void Sqneg_S_B_H_S_D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1262,7 +1262,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("SQNEG <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("SQNEG <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Sqneg_V_8B_4H_2S([Values(0u)] uint Rd,
|
public void Sqneg_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1293,7 +1293,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("SQNEG <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("SQNEG <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Sqneg_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
public void Sqneg_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1324,7 +1324,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("SQXTN <Vb><d>, <Va><n>")]
|
[Test, Description("SQXTN <Vb><d>, <Va><n>")]
|
||||||
public void Sqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
|
public void Sqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1355,7 +1355,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("SQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
[Test, Description("SQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
||||||
public void Sqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
|
public void Sqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1386,7 +1386,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("SQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
[Test, Description("SQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
||||||
public void Sqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
|
public void Sqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1417,7 +1417,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("SQXTUN <Vb><d>, <Va><n>")]
|
[Test, Description("SQXTUN <Vb><d>, <Va><n>")]
|
||||||
public void Sqxtun_S_HB_SH_DS([Values(0u)] uint Rd,
|
public void Sqxtun_S_HB_SH_DS([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1448,7 +1448,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
[Test, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
||||||
public void Sqxtun_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
|
public void Sqxtun_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1479,7 +1479,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
[Test, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
||||||
public void Sqxtun_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
|
public void Sqxtun_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1510,7 +1510,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("SUQADD <V><d>, <V><n>")]
|
[Test, Description("SUQADD <V><d>, <V><n>")]
|
||||||
public void Suqadd_S_B_H_S_D([Values(0u)] uint Rd,
|
public void Suqadd_S_B_H_S_D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1541,7 +1541,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("SUQADD <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("SUQADD <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Suqadd_V_8B_4H_2S([Values(0u)] uint Rd,
|
public void Suqadd_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1572,7 +1572,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("SUQADD <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("SUQADD <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Suqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
public void Suqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1603,7 +1603,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("UQXTN <Vb><d>, <Va><n>")]
|
[Test, Description("UQXTN <Vb><d>, <Va><n>")]
|
||||||
public void Uqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
|
public void Uqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1634,7 +1634,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("UQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
[Test, Description("UQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
||||||
public void Uqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
|
public void Uqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1665,7 +1665,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("UQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
[Test, Description("UQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
||||||
public void Uqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
|
public void Uqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1696,7 +1696,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("USQADD <V><d>, <V><n>")]
|
[Test, Description("USQADD <V><d>, <V><n>")]
|
||||||
public void Usqadd_S_B_H_S_D([Values(0u)] uint Rd,
|
public void Usqadd_S_B_H_S_D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1727,7 +1727,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("USQADD <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("USQADD <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Usqadd_V_8B_4H_2S([Values(0u)] uint Rd,
|
public void Usqadd_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1758,7 +1758,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("USQADD <Vd>.<T>, <Vn>.<T>")]
|
[Test, Description("USQADD <Vd>.<T>, <Vn>.<T>")]
|
||||||
public void Usqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
public void Usqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1789,7 +1789,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("XTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
[Test, Description("XTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
||||||
public void Xtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
|
public void Xtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
@ -1816,7 +1816,7 @@ namespace Ryujinx.Tests.Cpu
|
|||||||
}
|
}
|
||||||
|
|
||||||
[Test, Description("XTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
[Test, Description("XTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
||||||
public void Xtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
|
public void Xtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
|
||||||
[Values(1u, 0u)] uint Rn,
|
[Values(1u, 0u)] uint Rn,
|
||||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||||
|
File diff suppressed because it is too large
Load Diff
@ -5075,6 +5075,210 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||||||
V(d, result);
|
V(d, result);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// sqdmulh_advsimd_vec.html#SQDMULH_asisdsame_only
|
||||||
|
public static void Sqdmulh_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||||
|
{
|
||||||
|
const bool U = false;
|
||||||
|
|
||||||
|
/* Decode Scalar */
|
||||||
|
int d = (int)UInt(Rd);
|
||||||
|
int n = (int)UInt(Rn);
|
||||||
|
int m = (int)UInt(Rm);
|
||||||
|
|
||||||
|
/* if size == '11' || size == '00' then ReservedValue(); */
|
||||||
|
|
||||||
|
int esize = 8 << (int)UInt(size);
|
||||||
|
int datasize = esize;
|
||||||
|
int elements = 1;
|
||||||
|
|
||||||
|
bool rounding = (U == true);
|
||||||
|
|
||||||
|
/* Operation */
|
||||||
|
/* CheckFPAdvSIMDEnabled64(); */
|
||||||
|
|
||||||
|
Bits result = new Bits(datasize);
|
||||||
|
Bits operand1 = V(datasize, n);
|
||||||
|
Bits operand2 = V(datasize, m);
|
||||||
|
BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0);
|
||||||
|
BigInteger element1;
|
||||||
|
BigInteger element2;
|
||||||
|
BigInteger product;
|
||||||
|
bool sat;
|
||||||
|
|
||||||
|
for (int e = 0; e <= elements - 1; e++)
|
||||||
|
{
|
||||||
|
element1 = SInt(Elem(operand1, e, esize));
|
||||||
|
element2 = SInt(Elem(operand2, e, esize));
|
||||||
|
|
||||||
|
product = (2 * element1 * element2) + round_const;
|
||||||
|
|
||||||
|
(Bits _result, bool _sat) = SignedSatQ(product >> esize, esize);
|
||||||
|
Elem(result, e, esize, _result);
|
||||||
|
sat = _sat;
|
||||||
|
|
||||||
|
if (sat)
|
||||||
|
{
|
||||||
|
/* FPSR.QC = '1'; */
|
||||||
|
FPSR[27] = true; // TODO: Add named fields.
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
V(d, result);
|
||||||
|
}
|
||||||
|
|
||||||
|
// sqdmulh_advsimd_vec.html#SQDMULH_asimdsame_only
|
||||||
|
public static void Sqdmulh_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||||
|
{
|
||||||
|
const bool U = false;
|
||||||
|
|
||||||
|
/* Decode Vector */
|
||||||
|
int d = (int)UInt(Rd);
|
||||||
|
int n = (int)UInt(Rn);
|
||||||
|
int m = (int)UInt(Rm);
|
||||||
|
|
||||||
|
/* if size == '11' || size == '00' then ReservedValue(); */
|
||||||
|
|
||||||
|
int esize = 8 << (int)UInt(size);
|
||||||
|
int datasize = (Q ? 128 : 64);
|
||||||
|
int elements = datasize / esize;
|
||||||
|
|
||||||
|
bool rounding = (U == true);
|
||||||
|
|
||||||
|
/* Operation */
|
||||||
|
/* CheckFPAdvSIMDEnabled64(); */
|
||||||
|
|
||||||
|
Bits result = new Bits(datasize);
|
||||||
|
Bits operand1 = V(datasize, n);
|
||||||
|
Bits operand2 = V(datasize, m);
|
||||||
|
BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0);
|
||||||
|
BigInteger element1;
|
||||||
|
BigInteger element2;
|
||||||
|
BigInteger product;
|
||||||
|
bool sat;
|
||||||
|
|
||||||
|
for (int e = 0; e <= elements - 1; e++)
|
||||||
|
{
|
||||||
|
element1 = SInt(Elem(operand1, e, esize));
|
||||||
|
element2 = SInt(Elem(operand2, e, esize));
|
||||||
|
|
||||||
|
product = (2 * element1 * element2) + round_const;
|
||||||
|
|
||||||
|
(Bits _result, bool _sat) = SignedSatQ(product >> esize, esize);
|
||||||
|
Elem(result, e, esize, _result);
|
||||||
|
sat = _sat;
|
||||||
|
|
||||||
|
if (sat)
|
||||||
|
{
|
||||||
|
/* FPSR.QC = '1'; */
|
||||||
|
FPSR[27] = true; // TODO: Add named fields.
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
V(d, result);
|
||||||
|
}
|
||||||
|
|
||||||
|
// sqrdmulh_advsimd_vec.html#SQRDMULH_asisdsame_only
|
||||||
|
public static void Sqrdmulh_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||||
|
{
|
||||||
|
const bool U = true;
|
||||||
|
|
||||||
|
/* Decode Scalar */
|
||||||
|
int d = (int)UInt(Rd);
|
||||||
|
int n = (int)UInt(Rn);
|
||||||
|
int m = (int)UInt(Rm);
|
||||||
|
|
||||||
|
/* if size == '11' || size == '00' then ReservedValue(); */
|
||||||
|
|
||||||
|
int esize = 8 << (int)UInt(size);
|
||||||
|
int datasize = esize;
|
||||||
|
int elements = 1;
|
||||||
|
|
||||||
|
bool rounding = (U == true);
|
||||||
|
|
||||||
|
/* Operation */
|
||||||
|
/* CheckFPAdvSIMDEnabled64(); */
|
||||||
|
|
||||||
|
Bits result = new Bits(datasize);
|
||||||
|
Bits operand1 = V(datasize, n);
|
||||||
|
Bits operand2 = V(datasize, m);
|
||||||
|
BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0);
|
||||||
|
BigInteger element1;
|
||||||
|
BigInteger element2;
|
||||||
|
BigInteger product;
|
||||||
|
bool sat;
|
||||||
|
|
||||||
|
for (int e = 0; e <= elements - 1; e++)
|
||||||
|
{
|
||||||
|
element1 = SInt(Elem(operand1, e, esize));
|
||||||
|
element2 = SInt(Elem(operand2, e, esize));
|
||||||
|
|
||||||
|
product = (2 * element1 * element2) + round_const;
|
||||||
|
|
||||||
|
(Bits _result, bool _sat) = SignedSatQ(product >> esize, esize);
|
||||||
|
Elem(result, e, esize, _result);
|
||||||
|
sat = _sat;
|
||||||
|
|
||||||
|
if (sat)
|
||||||
|
{
|
||||||
|
/* FPSR.QC = '1'; */
|
||||||
|
FPSR[27] = true; // TODO: Add named fields.
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
V(d, result);
|
||||||
|
}
|
||||||
|
|
||||||
|
// sqrdmulh_advsimd_vec.html#SQRDMULH_asimdsame_only
|
||||||
|
public static void Sqrdmulh_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||||
|
{
|
||||||
|
const bool U = true;
|
||||||
|
|
||||||
|
/* Decode Vector */
|
||||||
|
int d = (int)UInt(Rd);
|
||||||
|
int n = (int)UInt(Rn);
|
||||||
|
int m = (int)UInt(Rm);
|
||||||
|
|
||||||
|
/* if size == '11' || size == '00' then ReservedValue(); */
|
||||||
|
|
||||||
|
int esize = 8 << (int)UInt(size);
|
||||||
|
int datasize = (Q ? 128 : 64);
|
||||||
|
int elements = datasize / esize;
|
||||||
|
|
||||||
|
bool rounding = (U == true);
|
||||||
|
|
||||||
|
/* Operation */
|
||||||
|
/* CheckFPAdvSIMDEnabled64(); */
|
||||||
|
|
||||||
|
Bits result = new Bits(datasize);
|
||||||
|
Bits operand1 = V(datasize, n);
|
||||||
|
Bits operand2 = V(datasize, m);
|
||||||
|
BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0);
|
||||||
|
BigInteger element1;
|
||||||
|
BigInteger element2;
|
||||||
|
BigInteger product;
|
||||||
|
bool sat;
|
||||||
|
|
||||||
|
for (int e = 0; e <= elements - 1; e++)
|
||||||
|
{
|
||||||
|
element1 = SInt(Elem(operand1, e, esize));
|
||||||
|
element2 = SInt(Elem(operand2, e, esize));
|
||||||
|
|
||||||
|
product = (2 * element1 * element2) + round_const;
|
||||||
|
|
||||||
|
(Bits _result, bool _sat) = SignedSatQ(product >> esize, esize);
|
||||||
|
Elem(result, e, esize, _result);
|
||||||
|
sat = _sat;
|
||||||
|
|
||||||
|
if (sat)
|
||||||
|
{
|
||||||
|
/* FPSR.QC = '1'; */
|
||||||
|
FPSR[27] = true; // TODO: Add named fields.
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
V(d, result);
|
||||||
|
}
|
||||||
|
|
||||||
// sqsub_advsimd.html#SQSUB_asisdsame_only
|
// sqsub_advsimd.html#SQSUB_asisdsame_only
|
||||||
public static void Sqsub_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
|
public static void Sqsub_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||||
{
|
{
|
||||||
|
@ -1,20 +1,25 @@
|
|||||||
<Project Sdk="Microsoft.NET.Sdk">
|
<Project Sdk="Microsoft.NET.Sdk">
|
||||||
|
|
||||||
<PropertyGroup>
|
<PropertyGroup>
|
||||||
<TargetFramework>netcoreapp2.1</TargetFramework>
|
<TargetFramework>netcoreapp2.1</TargetFramework>
|
||||||
<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
|
<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
|
||||||
<OutputType>Exe</OutputType>
|
<OutputType>Exe</OutputType>
|
||||||
<IsPackable>false</IsPackable>
|
<IsPackable>false</IsPackable>
|
||||||
</PropertyGroup>
|
</PropertyGroup>
|
||||||
|
|
||||||
<PropertyGroup>
|
<PropertyGroup>
|
||||||
<GenerateAssemblyInfo>false</GenerateAssemblyInfo>
|
<GenerateAssemblyInfo>false</GenerateAssemblyInfo>
|
||||||
</PropertyGroup>
|
</PropertyGroup>
|
||||||
|
|
||||||
<ItemGroup>
|
<ItemGroup>
|
||||||
<PackageReference Include="Microsoft.NET.Test.Sdk" Version="15.7.0" />
|
<PackageReference Include="Microsoft.NET.Test.Sdk" Version="15.8.0" />
|
||||||
<PackageReference Include="NUnit" Version="3.10.1" />
|
<PackageReference Include="NUnit" Version="3.10.1" />
|
||||||
<PackageReference Include="NUnit3TestAdapter" Version="3.10.0" />
|
<PackageReference Include="NUnit3TestAdapter" Version="3.10.0" />
|
||||||
<PackageReference Include="System.Runtime.Intrinsics.Experimental" Version="4.5.0-rc1" />
|
<PackageReference Include="System.Runtime.Intrinsics.Experimental" Version="4.5.0-rc1" />
|
||||||
</ItemGroup>
|
</ItemGroup>
|
||||||
|
|
||||||
<ItemGroup>
|
<ItemGroup>
|
||||||
<ProjectReference Include="..\ChocolArm64\ChocolArm64.csproj" />
|
<ProjectReference Include="..\ChocolArm64\ChocolArm64.csproj" />
|
||||||
</ItemGroup>
|
</ItemGroup>
|
||||||
|
|
||||||
</Project>
|
</Project>
|
||||||
|
@ -1,23 +1,28 @@
|
|||||||
<Project Sdk="Microsoft.NET.Sdk">
|
<Project Sdk="Microsoft.NET.Sdk">
|
||||||
|
|
||||||
<PropertyGroup>
|
<PropertyGroup>
|
||||||
<OutputType>Exe</OutputType>
|
|
||||||
<TargetFramework>netcoreapp2.1</TargetFramework>
|
<TargetFramework>netcoreapp2.1</TargetFramework>
|
||||||
<AllowUnsafeBlocks>true</AllowUnsafeBlocks>
|
|
||||||
<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
|
<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
|
||||||
|
<OutputType>Exe</OutputType>
|
||||||
|
<AllowUnsafeBlocks>true</AllowUnsafeBlocks>
|
||||||
</PropertyGroup>
|
</PropertyGroup>
|
||||||
|
|
||||||
<ItemGroup>
|
<ItemGroup>
|
||||||
<PackageReference Include="OpenTK.NetStandard" Version="1.0.4" />
|
<PackageReference Include="OpenTK.NetStandard" Version="1.0.4" />
|
||||||
<PackageReference Include="System.Runtime.CompilerServices.Unsafe" Version="4.4.0" />
|
<PackageReference Include="System.Runtime.CompilerServices.Unsafe" Version="4.4.0" />
|
||||||
</ItemGroup>
|
</ItemGroup>
|
||||||
|
|
||||||
<ItemGroup>
|
<ItemGroup>
|
||||||
<ProjectReference Include="..\ChocolArm64\ChocolArm64.csproj" />
|
<ProjectReference Include="..\ChocolArm64\ChocolArm64.csproj" />
|
||||||
<ProjectReference Include="..\Ryujinx.Audio\Ryujinx.Audio.csproj" />
|
<ProjectReference Include="..\Ryujinx.Audio\Ryujinx.Audio.csproj" />
|
||||||
<ProjectReference Include="..\Ryujinx.HLE\Ryujinx.HLE.csproj" />
|
|
||||||
<ProjectReference Include="..\Ryujinx.Graphics\Ryujinx.Graphics.csproj" />
|
<ProjectReference Include="..\Ryujinx.Graphics\Ryujinx.Graphics.csproj" />
|
||||||
|
<ProjectReference Include="..\Ryujinx.HLE\Ryujinx.HLE.csproj" />
|
||||||
</ItemGroup>
|
</ItemGroup>
|
||||||
|
|
||||||
<ItemGroup>
|
<ItemGroup>
|
||||||
<None Update="Ryujinx.conf">
|
<None Update="Ryujinx.conf">
|
||||||
<CopyToOutputDirectory>PreserveNewest</CopyToOutputDirectory>
|
<CopyToOutputDirectory>PreserveNewest</CopyToOutputDirectory>
|
||||||
</None>
|
</None>
|
||||||
</ItemGroup>
|
</ItemGroup>
|
||||||
</Project>
|
|
||||||
|
</Project>
|
||||||
|
Loading…
Reference in New Issue
Block a user