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Add FCVTL and FCVTN instruction (no Half support yet), stub SvcClearEvent
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@ -161,8 +161,10 @@ namespace ChocolArm64
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Set("000111100x10001xx10000xxxxxxxxxx", AInstEmit.Fcvt_S, typeof(AOpCodeSimd));
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Set("x00111100x100100000000xxxxxxxxxx", AInstEmit.Fcvtas_Gp, typeof(AOpCodeSimdCvt));
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Set("x00111100x100101000000xxxxxxxxxx", AInstEmit.Fcvtau_Gp, typeof(AOpCodeSimdCvt));
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Set("0x0011100x100001011110xxxxxxxxxx", AInstEmit.Fcvtl_V, typeof(AOpCodeSimd));
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Set("x00111100x110000000000xxxxxxxxxx", AInstEmit.Fcvtms_Gp, typeof(AOpCodeSimdCvt));
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Set("x00111100x110001000000xxxxxxxxxx", AInstEmit.Fcvtmu_Gp, typeof(AOpCodeSimdCvt));
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Set("0x0011100x100001011010xxxxxxxxxx", AInstEmit.Fcvtn_V, typeof(AOpCodeSimd));
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Set("x00111100x101000000000xxxxxxxxxx", AInstEmit.Fcvtps_Gp, typeof(AOpCodeSimdCvt));
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Set("x00111100x101001000000xxxxxxxxxx", AInstEmit.Fcvtpu_Gp, typeof(AOpCodeSimdCvt));
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Set("x00111100x111000000000xxxxxxxxxx", AInstEmit.Fcvtzs_Gp, typeof(AOpCodeSimdCvt));
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@ -31,6 +31,36 @@ namespace ChocolArm64.Instruction
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EmitFcvt_u_Gp(Context, () => EmitRoundMathCall(Context, MidpointRounding.AwayFromZero));
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}
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public static void Fcvtl_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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int Elems = 4 >> SizeF;
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int Part = Context.CurrOp.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
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for (int Index = 0; Index < Elems; Index++)
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{
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if (SizeF == 0)
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{
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//TODO: This need the half precision floating point type,
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//that is not yet supported on .NET. We should probably
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//do our own implementation on the meantime.
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throw new NotImplementedException();
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}
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else /* if (SizeF == 1) */
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{
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EmitVectorExtractF(Context, Op.Rn, Part + Index, 0);
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Context.Emit(OpCodes.Conv_R8);
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}
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EmitVectorInsertF(Context, Op.Rd, Index, SizeF);
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}
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}
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public static void Fcvtms_Gp(AILEmitterCtx Context)
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{
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EmitFcvt_s_Gp(Context, () => EmitUnaryMathCall(Context, nameof(Math.Floor)));
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@ -41,6 +71,36 @@ namespace ChocolArm64.Instruction
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EmitFcvt_u_Gp(Context, () => EmitUnaryMathCall(Context, nameof(Math.Floor)));
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}
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public static void Fcvtn_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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int Elems = 4 >> SizeF;
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int Part = Context.CurrOp.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtractF(Context, Op.Rd, Index, SizeF);
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if (SizeF == 0)
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{
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//TODO: This need the half precision floating point type,
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//that is not yet supported on .NET. We should probably
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//do our own implementation on the meantime.
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throw new NotImplementedException();
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}
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else /* if (SizeF == 1) */
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{
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Context.Emit(OpCodes.Conv_R4);
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EmitVectorInsertF(Context, Op.Rd, Part + Index, 0);
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}
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}
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}
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public static void Fcvtps_Gp(AILEmitterCtx Context)
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{
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EmitFcvt_s_Gp(Context, () => EmitUnaryMathCall(Context, nameof(Math.Ceiling)));
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@ -36,6 +36,7 @@ namespace Ryujinx.Core.OsHle.Svc
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{ 0x0c, SvcGetThreadPriority },
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{ 0x0d, SvcSetThreadPriority },
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{ 0x0f, SvcSetThreadCoreMask },
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{ 0x12, SvcClearEvent },
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{ 0x13, SvcMapSharedMemory },
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{ 0x14, SvcUnmapSharedMemory },
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{ 0x15, SvcCreateTransferMemory },
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@ -20,6 +20,15 @@ namespace Ryujinx.Core.OsHle.Svc
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Ns.Os.ExitProcess(ThreadState.ProcessId);
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}
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private void SvcClearEvent(AThreadState ThreadState)
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{
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int Handle = (int)ThreadState.X0;
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//TODO: Implement events.
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ThreadState.X0 = (int)SvcResult.Success;
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}
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private void SvcCloseHandle(AThreadState ThreadState)
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{
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int Handle = (int)ThreadState.X0;
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