mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-09-10 13:43:17 +02:00
Fix for some SIMD issues
This commit is contained in:
parent
f469b968a8
commit
1c44d9f66d
@ -139,8 +139,8 @@ namespace ChocolArm64
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Set("0>101110<<100000100110xxxxxxxxxx", AInstEmit.Cmle_V, typeof(AOpCodeSimd));
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Set("0>001110<<100000101010xxxxxxxxxx", AInstEmit.Cmlt_V, typeof(AOpCodeSimd));
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Set("0x00111000100000010110xxxxxxxxxx", AInstEmit.Cnt_V, typeof(AOpCodeSimd));
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Set("01011110000xxxxx000001xxxxxxxxxx", AInstEmit.Dup_S, typeof(AOpCodeSimdIns));
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Set("0x001110000xxxxx000011xxxxxxxxxx", AInstEmit.Dup_Gp, typeof(AOpCodeSimdIns));
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Set("01011110000xxxxx000001xxxxxxxxxx", AInstEmit.Dup_S, typeof(AOpCodeSimdIns));
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Set("0x001110000xxxxx000001xxxxxxxxxx", AInstEmit.Dup_V, typeof(AOpCodeSimdIns));
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Set("0x101110001xxxxx000111xxxxxxxxxx", AInstEmit.Eor_V, typeof(AOpCodeSimdReg));
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Set("00011110xx100000110000xxxxxxxxxx", AInstEmit.Fabs_S, typeof(AOpCodeSimd));
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@ -8,10 +8,10 @@ namespace ChocolArm64
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{
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class ATranslator
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{
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private Dictionary<long, ATranslatedSub> CachedSubs;
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public AThread Thread { get; private set; }
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private Dictionary<long, ATranslatedSub> CachedSubs;
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private bool KeepRunning;
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public ATranslator(AThread Parent)
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@ -27,11 +27,9 @@ namespace ChocolArm64.Decoder
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switch (Scale)
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{
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case 0: Index >>= 0; break;
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case 1:
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{
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if ((Index & 1) != 0)
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if ((Size & 1) != 0)
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{
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Inst = AInst.Undefined;
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@ -45,23 +43,23 @@ namespace ChocolArm64.Decoder
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case 2:
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{
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if ((Index & 2) != 0 ||
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((Index & 1) != 0 && S != 0))
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if ((Size & 2) != 0 ||
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((Size & 1) != 0 && S != 0))
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{
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Inst = AInst.Undefined;
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return;
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}
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if ((Index & 1) != 0)
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if ((Size & 1) != 0)
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{
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Index >>= 3;
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Scale = 3;
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}
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else
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{
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Index >>= 2;
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Scale = 3;
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}
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break;
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@ -246,6 +246,11 @@ namespace ChocolArm64.Instruction
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EmitScalarFcvtu(Context, Op.Size, Op.FBits);
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}
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if (Context.CurrOp.RegisterSize == ARegisterSize.Int32)
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{
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Context.Emit(OpCodes.Conv_U8);
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}
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Context.EmitStintzr(Op.Rd);
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}
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@ -314,6 +319,11 @@ namespace ChocolArm64.Instruction
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: nameof(ASoftFallback.SatF64ToU64));
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}
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if (SizeF == 0)
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{
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Context.Emit(OpCodes.Conv_U8);
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}
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EmitVectorInsert(Context, Op.Rd, Index, SizeI);
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}
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@ -210,17 +210,17 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
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EmitVectorOpF(Context, Emit, OperFlags.RnRm, Op.Index);
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EmitVectorOpByElemF(Context, Emit, Op.Index);
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}
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public static void EmitVectorTernaryOpByElemF(AILEmitterCtx Context, Action Emit)
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{
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AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
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EmitVectorOpF(Context, Emit, OperFlags.RdRnRm, Op.Index);
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EmitVectorOpByElemF(Context, Emit, Op.Index);
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}
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public static void EmitVectorOpF(AILEmitterCtx Context, Action Emit, OperFlags Opers, int Elem = -1)
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public static void EmitVectorOpF(AILEmitterCtx Context, Action Emit, OperFlags Opers)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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@ -242,14 +242,7 @@ namespace ChocolArm64.Instruction
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if (Opers.HasFlag(OperFlags.Rm))
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{
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if (Elem != -1)
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{
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EmitVectorExtractF(Context, Op.Rm, Elem, SizeF);
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}
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else
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{
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EmitVectorExtractF(Context, Op.Rm, Index, SizeF);
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}
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EmitVectorExtractF(Context, Op.Rm, Index, SizeF);
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}
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Emit();
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@ -263,6 +256,33 @@ namespace ChocolArm64.Instruction
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}
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}
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public static void EmitVectorOpByElemF(AILEmitterCtx Context, Action Emit, int Elem)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int SizeF = Op.Size & 1;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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for (int Index = 0; Index < (Bytes >> SizeF + 2); Index++)
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{
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EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
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EmitVectorExtractF(Context, Op.Rm, Elem, SizeF);
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Emit();
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EmitVectorInsertTmpF(Context, Index, SizeF);
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}
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void EmitVectorUnaryOpSx(AILEmitterCtx Context, Action Emit)
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{
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EmitVectorOp(Context, Emit, OperFlags.Rn, true);
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@ -534,5 +554,26 @@ namespace ChocolArm64.Instruction
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Context.EmitStvec(Reg);
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}
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public static void EmitVectorInsertTmpF(AILEmitterCtx Context, int Index, int Size)
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{
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Context.EmitLdvectmp();
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Context.EmitLdc_I4(Index);
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if (Size == 0)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorInsertSingle));
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}
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else if (Size == 1)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorInsertDouble));
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}
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else
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{
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throw new ArgumentOutOfRangeException(nameof(Size));
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}
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Context.EmitStvectmp();
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}
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}
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}
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@ -85,6 +85,8 @@ namespace ChocolArm64.Instruction
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EmitVectorExtractZx(Context, Op.Rn, 0, 3);
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EmitIntZeroHigherIfNeeded(Context);
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Context.EmitStintzr(Op.Rd);
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}
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@ -94,6 +96,8 @@ namespace ChocolArm64.Instruction
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EmitVectorExtractZx(Context, Op.Rn, 1, 3);
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EmitIntZeroHigherIfNeeded(Context);
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Context.EmitStintzr(Op.Rd);
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}
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@ -103,6 +107,8 @@ namespace ChocolArm64.Instruction
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Context.EmitLdintzr(Op.Rn);
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EmitIntZeroHigherIfNeeded(Context);
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EmitScalarSet(Context, Op.Rd, 3);
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}
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@ -112,6 +118,8 @@ namespace ChocolArm64.Instruction
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Context.EmitLdintzr(Op.Rn);
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EmitIntZeroHigherIfNeeded(Context);
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EmitVectorInsert(Context, Op.Rd, 1, 3);
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}
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@ -137,12 +145,19 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimdImm Op = (AOpCodeSimdImm)Context.CurrOp;
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for (int Index = 0; Index < (4 >> Op.Size); Index++)
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int Elems = Op.RegisterSize == ARegisterSize.SIMD128 ? 4 : 2;
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for (int Index = 0; Index < (Elems >> Op.Size); Index++)
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{
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Context.EmitLdc_I8(Op.Imm);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size + 2);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void Ins_Gp(AILEmitterCtx Context)
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@ -248,6 +263,15 @@ namespace ChocolArm64.Instruction
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}
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}
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private static void EmitIntZeroHigherIfNeeded(AILEmitterCtx Context)
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{
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if (Context.CurrOp.RegisterSize == ARegisterSize.Int32)
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{
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Context.Emit(OpCodes.Conv_U4);
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Context.Emit(OpCodes.Conv_U8);
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}
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}
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private static void EmitVectorUnzip(AILEmitterCtx Context, int Part)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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@ -2,6 +2,7 @@ using ChocolArm64.Exceptions;
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using ChocolArm64.State;
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using System;
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using System.Collections.Generic;
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using System.Runtime.CompilerServices;
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namespace ChocolArm64.Memory
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{
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@ -138,6 +139,7 @@ namespace ChocolArm64.Memory
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public int ReadInt32(long Position) => (int)ReadUInt32(Position);
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public long ReadInt64(long Position) => (long)ReadUInt64(Position);
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public byte ReadByte(long Position)
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{
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#if DEBUG
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@ -147,6 +149,7 @@ namespace ChocolArm64.Memory
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return *((byte*)(RamPtr + (uint)Position));
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public ushort ReadUInt16(long Position)
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{
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#if DEBUG
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@ -156,6 +159,7 @@ namespace ChocolArm64.Memory
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return *((ushort*)(RamPtr + (uint)Position));
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public uint ReadUInt32(long Position)
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{
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#if DEBUG
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@ -165,6 +169,7 @@ namespace ChocolArm64.Memory
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return *((uint*)(RamPtr + (uint)Position));
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public ulong ReadUInt64(long Position)
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{
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#if DEBUG
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@ -174,6 +179,7 @@ namespace ChocolArm64.Memory
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return *((ulong*)(RamPtr + (uint)Position));
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public AVec ReadVector8(long Position)
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{
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#if DEBUG
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@ -183,6 +189,7 @@ namespace ChocolArm64.Memory
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return new AVec() { B0 = ReadByte(Position) };
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public AVec ReadVector16(long Position)
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{
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#if DEBUG
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@ -192,6 +199,7 @@ namespace ChocolArm64.Memory
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return new AVec() { H0 = ReadUInt16(Position) };
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public AVec ReadVector32(long Position)
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{
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#if DEBUG
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@ -201,6 +209,7 @@ namespace ChocolArm64.Memory
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return new AVec() { W0 = ReadUInt32(Position) };
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public AVec ReadVector64(long Position)
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{
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#if DEBUG
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@ -210,6 +219,7 @@ namespace ChocolArm64.Memory
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return new AVec() { X0 = ReadUInt64(Position) };
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public AVec ReadVector128(long Position)
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{
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#if DEBUG
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@ -228,6 +238,7 @@ namespace ChocolArm64.Memory
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public void WriteInt32(long Position, int Value) => WriteUInt32(Position, (uint)Value);
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public void WriteInt64(long Position, long Value) => WriteUInt64(Position, (ulong)Value);
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public void WriteByte(long Position, byte Value)
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{
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#if DEBUG
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@ -237,6 +248,7 @@ namespace ChocolArm64.Memory
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*((byte*)(RamPtr + (uint)Position)) = Value;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public void WriteUInt16(long Position, ushort Value)
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{
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#if DEBUG
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@ -246,6 +258,7 @@ namespace ChocolArm64.Memory
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*((ushort*)(RamPtr + (uint)Position)) = Value;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public void WriteUInt32(long Position, uint Value)
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{
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#if DEBUG
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@ -255,6 +268,7 @@ namespace ChocolArm64.Memory
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*((uint*)(RamPtr + (uint)Position)) = Value;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public void WriteUInt64(long Position, ulong Value)
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{
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#if DEBUG
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@ -264,6 +278,7 @@ namespace ChocolArm64.Memory
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*((ulong*)(RamPtr + (uint)Position)) = Value;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public void WriteVector8(long Position, AVec Value)
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{
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#if DEBUG
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@ -273,6 +288,7 @@ namespace ChocolArm64.Memory
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WriteByte(Position, Value.B0);
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public void WriteVector16(long Position, AVec Value)
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{
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#if DEBUG
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@ -282,6 +298,7 @@ namespace ChocolArm64.Memory
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WriteUInt16(Position, Value.H0);
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public void WriteVector32(long Position, AVec Value)
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{
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#if DEBUG
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@ -291,6 +308,7 @@ namespace ChocolArm64.Memory
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WriteUInt32(Position, Value.W0);
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public void WriteVector64(long Position, AVec Value)
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{
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#if DEBUG
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@ -300,6 +318,7 @@ namespace ChocolArm64.Memory
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WriteUInt64(Position, Value.X0);
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public void WriteVector128(long Position, AVec Value)
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{
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#if DEBUG
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@ -26,7 +26,7 @@ namespace ChocolArm64.Translation
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{
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if (ILEmitter is AILOpCodeLoad Ld && AILEmitter.IsRegIndex(Ld.Index))
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{
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switch (Ld.IoType & AIoType.Mask)
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switch (Ld.IoType)
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{
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case AIoType.Flag: IntInputs |= ((1L << Ld.Index) << 32) & ~IntOutputs; break;
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case AIoType.Int: IntInputs |= (1L << Ld.Index) & ~IntOutputs; break;
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@ -37,7 +37,7 @@ namespace ChocolArm64.Translation
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{
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if (AILEmitter.IsRegIndex(St.Index))
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{
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switch (St.IoType & AIoType.Mask)
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switch (St.IoType)
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{
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case AIoType.Flag: IntOutputs |= (1L << St.Index) << 32; break;
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case AIoType.Int: IntOutputs |= 1L << St.Index; break;
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@ -22,7 +22,7 @@ namespace ChocolArm64.Translation
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public void Emit(AILEmitter Context)
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{
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switch (IoType & AIoType.Mask)
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switch (IoType)
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{
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case AIoType.Arg: Context.Generator.EmitLdarg(Index); break;
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@ -22,7 +22,7 @@ namespace ChocolArm64.Translation
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public void Emit(AILEmitter Context)
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{
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switch (IoType & AIoType.Mask)
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switch (IoType)
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{
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case AIoType.Arg: Context.Generator.EmitStarg(Index); break;
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@ -10,9 +10,6 @@ namespace ChocolArm64.Translation
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Flag,
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Int,
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Float,
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Vector,
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Mask = 0xff,
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VectorI = Vector | 1 << 8,
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VectorF = Vector | 1 << 9
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Vector
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}
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}
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@ -25,10 +25,10 @@ Controls_Left_FakeJoycon_Stick_Down = 93
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Controls_Left_FakeJoycon_Stick_Left = 92
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Controls_Left_FakeJoycon_Stick_Right = 94
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Controls_Left_FakeJoycon_Stick_Button = 0
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Controls_Left_FakeJoycon_DPad_Up = 0
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Controls_Left_FakeJoycon_DPad_Down = 0
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Controls_Left_FakeJoycon_DPad_Left = 0
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Controls_Left_FakeJoycon_DPad_Right = 0
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Controls_Left_FakeJoycon_DPad_Up = 45
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Controls_Left_FakeJoycon_DPad_Down = 46
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Controls_Left_FakeJoycon_DPad_Left = 47
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Controls_Left_FakeJoycon_DPad_Right = 48
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Controls_Left_FakeJoycon_Button_Minus = 52
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Controls_Left_FakeJoycon_Button_L = 0
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Controls_Left_FakeJoycon_Button_ZL = 0
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@ -6,7 +6,6 @@ using Gal;
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using OpenTK;
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using OpenTK.Graphics;
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using OpenTK.Graphics.OpenGL;
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using Ryujinx.OsHle;
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using System;
|
||||
|
||||
namespace Ryujinx
|
||||
|
Loading…
Reference in New Issue
Block a user