mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-09-10 13:43:17 +02:00
Improve access to system registers by using properties, also use exclusive region granularity on exclusive load/stores, and ensure that acquires without releases won't hold the address forever, remove unused ALU rev method
This commit is contained in:
parent
6ae5587b5e
commit
2347c44bbf
@ -175,17 +175,6 @@ namespace ChocolArm64.Instruction
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Context.EmitStintzr(Op.Rd);
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}
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private static void EmitRev(AILEmitterCtx Context, string Name)
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{
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AOpCodeAlu Op = (AOpCodeAlu)Context.CurrOp;
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Context.EmitLdintzr(Op.Rn);
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ASoftFallback.EmitCall(Context, Name);
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Context.EmitStintzr(Op.Rd);
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}
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public static void Rorv(AILEmitterCtx Context)
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{
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EmitDataLoadRn(Context);
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@ -1,6 +1,8 @@
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using ChocolArm64.Decoder;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection;
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using System.Reflection.Emit;
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namespace ChocolArm64.Instruction
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@ -13,13 +15,30 @@ namespace ChocolArm64.Instruction
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Context.EmitLdarg(ATranslatedSub.RegistersArgIdx);
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Context.EmitLdc_I4(Op.Op0);
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Context.EmitLdc_I4(Op.Op1);
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Context.EmitLdc_I4(Op.CRn);
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Context.EmitLdc_I4(Op.CRm);
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Context.EmitLdc_I4(Op.Op2);
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string PropName;
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Context.EmitCall(typeof(ARegisters), nameof(ARegisters.GetSystemReg));
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switch (GetPackedId(Op))
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{
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case 0b11_011_0000_0000_001: PropName = nameof(ARegisters.CtrEl0); break;
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case 0b11_011_0000_0000_111: PropName = nameof(ARegisters.DczidEl0); break;
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case 0b11_011_0100_0100_000: PropName = nameof(ARegisters.Fpcr); break;
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case 0b11_011_0100_0100_001: PropName = nameof(ARegisters.Fpsr); break;
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case 0b11_011_1101_0000_010: PropName = nameof(ARegisters.TpidrEl0); break;
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case 0b11_011_1101_0000_011: PropName = nameof(ARegisters.Tpidr); break;
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case 0b11_011_1110_0000_001: PropName = nameof(ARegisters.CntpctEl0); break;
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default: throw new NotImplementedException($"Unknown MRS at {Op.Position:x16}");
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}
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Context.EmitCallPropGet(typeof(ARegisters), PropName);
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PropertyInfo PropInfo = typeof(ARegisters).GetProperty(PropName);
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if (PropInfo.PropertyType != typeof(long) &&
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PropInfo.PropertyType != typeof(ulong))
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{
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Context.Emit(OpCodes.Conv_U8);
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}
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Context.EmitStintzr(Op.Rt);
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}
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@ -29,15 +48,28 @@ namespace ChocolArm64.Instruction
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AOpCodeSystem Op = (AOpCodeSystem)Context.CurrOp;
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Context.EmitLdarg(ATranslatedSub.RegistersArgIdx);
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Context.EmitLdc_I4(Op.Op0);
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Context.EmitLdc_I4(Op.Op1);
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Context.EmitLdc_I4(Op.CRn);
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Context.EmitLdc_I4(Op.CRm);
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Context.EmitLdc_I4(Op.Op2);
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Context.EmitLdintzr(Op.Rt);
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Context.EmitCall(typeof(ARegisters), nameof(ARegisters.SetSystemReg));
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string PropName;
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switch (GetPackedId(Op))
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{
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case 0b11_011_0100_0100_000: PropName = nameof(ARegisters.Fpcr); break;
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case 0b11_011_0100_0100_001: PropName = nameof(ARegisters.Fpsr); break;
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case 0b11_011_1101_0000_010: PropName = nameof(ARegisters.TpidrEl0); break;
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default: throw new NotImplementedException($"Unknown MSR at {Op.Position:x16}");
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}
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PropertyInfo PropInfo = typeof(ARegisters).GetProperty(PropName);
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if (PropInfo.PropertyType != typeof(long) &&
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PropInfo.PropertyType != typeof(ulong))
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{
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Context.Emit(OpCodes.Conv_U4);
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}
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Context.EmitCallPropSet(typeof(ARegisters), PropName);
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}
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public static void Nop(AILEmitterCtx Context)
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@ -52,19 +84,12 @@ namespace ChocolArm64.Instruction
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//We treat it as no-op here since we don't have any cache being emulated anyway.
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AOpCodeSystem Op = (AOpCodeSystem)Context.CurrOp;
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int Id;
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Id = Op.Op2 << 0;
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Id |= Op.CRm << 3;
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Id |= Op.CRn << 7;
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Id |= Op.Op1 << 11;
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switch (Id)
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switch (GetPackedId(Op))
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{
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case 0b011_0111_0100_001:
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case 0b11_011_0111_0100_001:
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{
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//DC ZVA
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for (int Offs = 0; Offs < 64; Offs += 8)
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for (int Offs = 0; Offs < (4 << ARegisters.DczSizeLog2); Offs += 8)
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{
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Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
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Context.EmitLdint(Op.Rt);
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@ -80,5 +105,18 @@ namespace ChocolArm64.Instruction
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}
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}
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}
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private static int GetPackedId(AOpCodeSystem Op)
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{
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int Id;
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Id = Op.Op2 << 0;
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Id |= Op.CRm << 3;
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Id |= Op.CRn << 7;
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Id |= Op.Op1 << 11;
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Id |= Op.Op0 << 14;
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return Id;
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}
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}
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}
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@ -6,6 +6,8 @@ namespace ChocolArm64.Memory
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{
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public unsafe class AMemory
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{
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private const long ErgMask = (4 << ARegisters.ErgSizeLog2) - 1;
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public AMemoryMgr Manager { get; private set; }
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private struct ExMonitor
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@ -52,6 +54,11 @@ namespace ChocolArm64.Memory
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{
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lock (Monitors)
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{
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if (Monitors.TryGetValue(ThreadId, out ExMonitor Monitor))
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{
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ExAddrs.Remove(Monitor.Position);
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}
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Monitors.Remove(ThreadId);
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}
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}
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@ -60,14 +67,16 @@ namespace ChocolArm64.Memory
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{
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lock (Monitors)
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{
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bool ExState = !ExAddrs.Contains(Position);
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Position &= ~ErgMask;
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if (ExState)
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if (Monitors.TryGetValue(Registers.ThreadId, out ExMonitor Monitor))
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{
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ExAddrs.Add(Position);
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ExAddrs.Remove(Monitor.Position);
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}
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ExMonitor Monitor = new ExMonitor(Position, ExState);
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bool ExState = ExAddrs.Add(Position);
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Monitor = new ExMonitor(Position, ExState);
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if (!Monitors.TryAdd(Registers.ThreadId, Monitor))
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{
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@ -80,6 +89,8 @@ namespace ChocolArm64.Memory
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{
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lock (Monitors)
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{
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Position &= ~ErgMask;
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if (!Monitors.TryGetValue(Registers.ThreadId, out ExMonitor Monitor))
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{
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return false;
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@ -1,8 +0,0 @@
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namespace ChocolArm64.State
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{
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public enum ACoreType
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{
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CortexA53,
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CortexA57
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}
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}
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@ -7,6 +7,12 @@ namespace ChocolArm64.State
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internal const int LRIndex = 30;
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internal const int ZRIndex = 31;
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internal const int ErgSizeLog2 = 4;
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internal const int DczSizeLog2 = 4;
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private const long TicksPerS = 19_200_000;
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private const long TicksPerMS = TicksPerS / 1_000;
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public ulong X0, X1, X2, X3, X4, X5, X6, X7,
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X8, X9, X10, X11, X12, X13, X14, X15,
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X16, X17, X18, X19, X20, X21, X22, X23,
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@ -24,95 +30,21 @@ namespace ChocolArm64.State
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public int ProcessId;
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public int ThreadId;
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public long TlsAddrEl0;
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public long TlsAddr;
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private int FPCR;
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private int FPSR;
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public long TpidrEl0 { get; set; }
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public long Tpidr { get; set; }
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public ACoreType CoreType;
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public int Fpcr { get; set; }
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public int Fpsr { get; set; }
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private const ulong A53DczidEl0 = 4;
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private const ulong A53CtrEl0 = 0x84448004;
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private const ulong A57CtrEl0 = 0x8444c004;
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public uint CtrEl0 => 0x8444c004;
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public uint DczidEl0 => 0x00000004;
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private const ulong TicksPerS = 19_200_000;
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private const ulong TicksPerMS = TicksPerS / 1_000;
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public long CntpctEl0 => Environment.TickCount * TicksPerMS;
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public event EventHandler<SvcEventArgs> SvcCall;
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public event EventHandler<EventArgs> Undefined;
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public ulong GetSystemReg(int Op0, int Op1, int CRn, int CRm, int Op2)
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{
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switch (PackRegId(Op0, Op1, CRn, CRm, Op2))
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{
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case 0b11_011_0000_0000_001: return GetCtrEl0();
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case 0b11_011_0000_0000_111: return GetDczidEl0();
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case 0b11_011_0100_0100_000: return (ulong)PackFPCR();
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case 0b11_011_0100_0100_001: return (ulong)PackFPSR();
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case 0b11_011_1101_0000_010: return (ulong)TlsAddrEl0;
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case 0b11_011_1101_0000_011: return (ulong)TlsAddr;
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case 0b11_011_1110_0000_001: return (ulong)Environment.TickCount * TicksPerMS;
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default: throw new ArgumentException();
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}
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}
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public void SetSystemReg(int Op0, int Op1, int CRn, int CRm, int Op2, ulong Value)
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{
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switch (PackRegId(Op0, Op1, CRn, CRm, Op2))
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{
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case 0b11_011_0100_0100_000: UnpackFPCR((int)Value); break;
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case 0b11_011_0100_0100_001: UnpackFPSR((int)Value); break;
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case 0b11_011_1101_0000_010: TlsAddrEl0 = (long)Value; break;
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default: throw new ArgumentException();
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}
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}
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private int PackRegId(int Op0, int Op1, int CRn, int CRm, int Op2)
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{
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int Id;
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Id = Op2 << 0;
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Id |= CRm << 3;
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Id |= CRn << 7;
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Id |= Op1 << 11;
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Id |= Op0 << 14;
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return Id;
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}
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public ulong GetCtrEl0()
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{
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return CoreType == ACoreType.CortexA53 ? A53CtrEl0 : A57CtrEl0;
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}
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public ulong GetDczidEl0()
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{
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return A53DczidEl0;
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}
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public int PackFPCR()
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{
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return FPCR; //TODO
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}
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public int PackFPSR()
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{
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return FPSR; //TODO
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}
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public void UnpackFPCR(int Value)
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{
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FPCR = Value;
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}
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public void UnpackFPSR(int Value)
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{
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FPSR = Value;
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}
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public void OnSvcCall(int Imm)
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{
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SvcCall?.Invoke(this, new SvcEventArgs(Imm));
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@ -467,11 +467,41 @@ namespace ChocolArm64.Translation
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throw new ArgumentOutOfRangeException(nameof(Size));
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}
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public void EmitCall(Type MthdType, string MthdName)
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public void EmitCallPropGet(Type ObjType, string PropName)
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{
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if (MthdType == null)
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if (ObjType == null)
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{
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throw new ArgumentNullException(nameof(MthdType));
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throw new ArgumentNullException(nameof(ObjType));
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}
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if (PropName == null)
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{
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throw new ArgumentNullException(nameof(PropName));
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}
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EmitCall(ObjType.GetMethod($"get_{PropName}"));
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}
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public void EmitCallPropSet(Type ObjType, string PropName)
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{
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if (ObjType == null)
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{
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throw new ArgumentNullException(nameof(ObjType));
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}
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if (PropName == null)
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{
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throw new ArgumentNullException(nameof(PropName));
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}
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EmitCall(ObjType.GetMethod($"set_{PropName}"));
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}
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public void EmitCall(Type ObjType, string MthdName)
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{
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if (ObjType == null)
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{
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throw new ArgumentNullException(nameof(ObjType));
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}
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if (MthdName == null)
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@ -479,7 +509,7 @@ namespace ChocolArm64.Translation
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throw new ArgumentNullException(nameof(MthdName));
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}
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EmitCall(MthdType.GetMethod(MthdName));
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EmitCall(ObjType.GetMethod(MthdName));
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}
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public void EmitCall(MethodInfo MthdInfo)
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@ -138,7 +138,7 @@ namespace Ryujinx.OsHle
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Thread.Registers.SvcCall += SvcHandler.SvcCall;
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Thread.Registers.ProcessId = ProcessId;
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Thread.Registers.ThreadId = Ns.Os.IdGen.GenerateId();
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Thread.Registers.TlsAddr = TlsPageAddr + TlsSlot * TlsSize;
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Thread.Registers.Tpidr = TlsPageAddr + TlsSlot * TlsSize;
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Thread.Registers.X0 = (ulong)ArgsPtr;
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Thread.Registers.X1 = (ulong)Handle;
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Thread.Registers.X31 = (ulong)StackTop;
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@ -165,7 +165,7 @@ namespace Ryujinx.OsHle
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{
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if (sender is AThread Thread)
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{
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TlsSlots.TryRemove(GetTlsSlot(Thread.Registers.TlsAddr), out _);
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TlsSlots.TryRemove(GetTlsSlot(Thread.Registers.Tpidr), out _);
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Ns.Os.IdGen.DeleteId(Thread.ThreadId);
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}
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@ -39,7 +39,7 @@ namespace Ryujinx.OsHle.Svc
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private static void SvcGetSystemTick(Switch Ns, ARegisters Registers, AMemory Memory)
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{
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Registers.X0 = (ulong)Registers.GetSystemReg(3, 3, 14, 0, 1);
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Registers.X0 = (ulong)Registers.CntpctEl0;
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}
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private static void SvcConnectToNamedPort(Switch Ns, ARegisters Registers, AMemory Memory)
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@ -70,7 +70,7 @@ namespace Ryujinx.OsHle.Svc
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private static void SendSyncRequest(Switch Ns, ARegisters Registers, AMemory Memory, bool IsUser)
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{
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long CmdPtr = Registers.TlsAddr;
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long CmdPtr = Registers.Tpidr;
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long Size = 0x100;
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int Handle = 0;
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